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Mon, 27 Apr 2026 22:30:02 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Dragos Tatulea , Moshe Shemesh , Nimrod Oren Subject: [PATCH net-next 1/3] net/mlx5: wire frag buf pools lifecycle hooks Date: Tue, 28 Apr 2026 08:29:18 +0300 Message-ID: <20260428052920.219201-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260428052920.219201-1-tariqt@nvidia.com> References: <20260428052920.219201-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F3E:EE_|DM4PR12MB8558:EE_ X-MS-Office365-Filtering-Correlation-Id: e72a2a88-05bd-4e00-f91f-08dea4e73fd8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|82310400026|376014|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: tQLwoK+Xsu2sSdcDu8MGeXq6zjLtG1U3+2KjhNkIher+YAhtvYnYRSXSULJS5E2WnLWzRggCD7pcjx9L7btp0iNr6RZNKe2sQdZXNOqozGyvhFNNOVVg04Gs+GxemhCUl3pUQt4IseUE8ycUQI7Tjvt86PXVkiShUEMYSzGVyy3W+wTV+VU+3JEgPkgg8VKDfmzi9xFFjKM6AGSNEUs4eBXL8cfPq8qKy5XAFj8IjehrOcTEFKmTkLNdyCojoUGfHALpfsgicI/UMCPJmIHZinAOH1LNwYqXgrXss6mtQcIyFJOMtnaMxQq8RGwL0swCc4CV5SWBez2agbi0Tw4fMnJEIXBKw4FCYEDlJBA3QnTPHy4PMNthmjUUehl35p2mY36/byCAcvGsObAWjCVqoj4Nj9ywQA9lD105raSQ86Zlv3bAbT7Jvb1CIdqM1EEZTEEtlP+QvG/jPAR6RYkJBw2NDP209UQ6AeQzDEFyOWtKGa4NWyCmqlmuvoJvXs0iE6ECM6mUDd6v4oZ4g+VXY13jT71SRAy/BtixvRCle5U9r1EET6zdRymqPYKsbrogOgVxoOKJk6U+VgTDwp7npt+XqvPP3Zjg/yxd652mOLn3yObKgLrOrEf7sFlRC4R78KsPKzU1rFPC6SoekLq8rOMg34LRX3lx/H9S8VWF1zm4Lma9s3exHPP9+/vjOu+uA4T9IgrqgxlUTOV508iaUG+jxcb2+ius3Ll2/Wm6D+acq6KVi1DK6KVm3SELRySk+N9rthUr1SrXk74627M1EQ== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(82310400026)(376014)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: OjB0DmdtPxb9uUIGgjfs6TVGM8vjm2lYzS5zqsIoDRnWLdXGEl8VjQDWyhn9bVR63+VX6sQgm+vN9qlYRyL6DldMVpb0clEzrMiioFd7OP6Qt9hrxyx9V2BxANYceijkr3RcHyt1k8wgViz5XOufebbIFtWVGIvJc2sWJuq+GWgbyNbGyIL7Sb8dLF2AAEBwBT9+pCp4Fm/S2arYKrWXmpIFl1EiLnqA7eyfSTWUvouv33jXf8FgY2LvFIUJiEImQCgPlhYZ3D20E5O0H9Fictdc7VPrDMFkhJHKeXHllKKGsAbgZhIlZnAmkOddARUwDc2FaYm+mRBhrr7ulS8xYYZNc3r6yX9kFiMYEi7rahF26QR9TgeprjT2GoWH/cuncLNsQQGN6wmolZyopB/5eiM0pB2i7gi4LMZgp9/s1FZzmKxRdXiUqwvi3LmOXFOe X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2026 05:30:24.7384 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e72a2a88-05bd-4e00-f91f-08dea4e73fd8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F3E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8558 Content-Type: text/plain; charset="utf-8" From: Nimrod Oren Wire mlx5_frag_buf pools init/cleanup hooks into mlx5_mdev_init()/uninit() and the init unwind path. Keep temporary no-op stubs in alloc.c so lifecycle ordering is in place before the coherent DMA sub-page allocator implementation is added in follow-up patches. Signed-off-by: Nimrod Oren Signed-off-by: Tariq Toukan --- drivers/net/ethernet/mellanox/mlx5/core/alloc.c | 11 +++++++++++ drivers/net/ethernet/mellanox/mlx5/core/main.c | 7 +++++++ drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h | 2 ++ 3 files changed, 20 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/alloc.c b/drivers/net/= ethernet/mellanox/mlx5/core/alloc.c index 202feab1558a..cebb3559d2c9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/alloc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/alloc.c @@ -71,6 +71,17 @@ static void *mlx5_dma_zalloc_coherent_node(struct mlx5_c= ore_dev *dev, return cpu_handle; } =20 +/* Implemented later in the series */ +void mlx5_frag_buf_pools_cleanup(struct mlx5_core_dev *dev) +{ +} + +/* Implemented later in the series */ +int mlx5_frag_buf_pools_init(struct mlx5_core_dev *dev) +{ + return 0; +} + int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, struct mlx5_frag_buf *buf, int node) { diff --git a/drivers/net/ethernet/mellanox/mlx5/core/main.c b/drivers/net/e= thernet/mellanox/mlx5/core/main.c index 74827e8ca125..b1b9ebfd3866 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/main.c @@ -1817,6 +1817,10 @@ int mlx5_mdev_init(struct mlx5_core_dev *dev, int pr= ofile_idx) priv->dbg.dbg_root =3D debugfs_create_dir(dev_name(dev->device), mlx5_debugfs_root); =20 + err =3D mlx5_frag_buf_pools_init(dev); + if (err) + goto err_frag_buf_pools_init; + INIT_LIST_HEAD(&priv->traps); =20 err =3D mlx5_cmd_init(dev); @@ -1878,6 +1882,8 @@ int mlx5_mdev_init(struct mlx5_core_dev *dev, int pro= file_idx) err_timeout_init: mlx5_cmd_cleanup(dev); err_cmd_init: + mlx5_frag_buf_pools_cleanup(dev); +err_frag_buf_pools_init: debugfs_remove(dev->priv.dbg.dbg_root); mutex_destroy(&priv->pgdir_mutex); mutex_destroy(&priv->alloc_mutex); @@ -1902,6 +1908,7 @@ void mlx5_mdev_uninit(struct mlx5_core_dev *dev) mlx5_health_cleanup(dev); mlx5_tout_cleanup(dev); mlx5_cmd_cleanup(dev); + mlx5_frag_buf_pools_cleanup(dev); debugfs_remove_recursive(dev->priv.dbg.dbg_root); mutex_destroy(&priv->pgdir_mutex); mutex_destroy(&priv->alloc_mutex); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/= net/ethernet/mellanox/mlx5/core/mlx5_core.h index 1507e881d962..87f01c4e8d65 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -436,6 +436,8 @@ mlx5_sf_coredev_to_adev(struct mlx5_core_dev *mdev) =20 int mlx5_mdev_init(struct mlx5_core_dev *dev, int profile_idx); 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Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Dragos Tatulea , Moshe Shemesh , Nimrod Oren Subject: [PATCH net-next 2/3] net/mlx5: add frag buf pools create/destroy paths Date: Tue, 28 Apr 2026 08:29:19 +0300 Message-ID: <20260428052920.219201-3-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260428052920.219201-1-tariqt@nvidia.com> References: <20260428052920.219201-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00036F40:EE_|CY3PR12MB9655:EE_ X-MS-Office365-Filtering-Correlation-Id: 481488a6-ceaf-491a-6780-08dea4e742e1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|56012099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: AUswuXAM36gxX2tBf2xFwileE/uIdEVwLO0QaLhW2OJ3LAY087zEY3VVSpdGlSQwmi6/dsdbdNmBa3MOCgaCI+b8t4L9cb0b+Xv7zsifc06uibsD5ecs/h0up75HivE+dufRdqbwK3sU0uHv7RxCAPq9ZG1FBljfjdstWcOPyq5cA+jxtyVKAVkVfdX4XXeMdaPCbBqozmFT43BZCniC5jukwpejoPHSvFvni9AxaIZsnyLMEZeQQpQ1vn/ZYazojmGqPMBrxaYujFcyevwwsEMHiyRtaEuTdM4mjbPbDYHRwMLU8xlrtOFPnZGX81wYtf9YdLMOxbDc5SiTSRcpOvbSGUDmxaGTJ4nPr+mVzOpXYscFnGLDp7YmhnJtsjjICOkoVuc1/UtNVx74ft7gtLzfClwyuGkFEFagg20R/7bNPUhRzE9uyAfSOMHFx00xj2yPpmVbivkjzcmrX1P67FR6uewqYRstz7d1KfuqEO5T6hEfJnIM94mYhlXWXDyAn690nqWJkhOlvQBWgLmQhiI9ssiA6y+m0dhPfTZp5KjtKKcO2T1xkRC8DvyFzWek+D8vPVPuilCdJVE7HQ0Q/28PtzMxeZvlyuGz7bErNPP5uNXIDXAev8wqk6dNCFXUEZiy3Xb85yoAMMVTwfi6KzkWM9rqJ3UUmFG85CXe3HfHqMWnVqapsX2ky31YcXMYKaL4KYnyE3NWjKJJD1ttnRlVNveaEMa8jq1GX8/QFBiHP4A+C2In49R/epYDyt2zTLOW0Udi0yq0pRbBNOVJhQ== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: pOuyEAd6b3JtSJXKuk6MxOYkS96MWxihBflUmyY9jM9CeR+0MA+TEa3s6qalZqJEGn3C/bAf5AZBpQsZ4HxU7taEo4nx7fB1ZQydDMLzcvk2Fj6ne5WeCzmS23WqveGDBMqFPhoaM1zyhCf6h+0x65FKc9u8LXSefbCe26SajoZUFaM8vif3j6I24tkdsv52c9D+Zr3LLZrO0ILase/igtc/nP0gfl2ADIrY8bpZnwGLyeJM6DUKUUZJWtCMd3/G3gLhHU/vMalTkJSjP86ShUMgdcZaxNr5LLQfHBuX+9ceTGq6YrGe9XgMHNSDmDzlfTjjXxbs92BoO//FIb2x/jlDrG9KpWqKfqLaI9enaii+Z/HysU1qfBLhk6kFCSRXp9RnhCKMa+Fn/+5ttyFpALT0jaI+fy8WwcmiXpLikdLZRkeUaad1z+jDhJgMfl5b X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2026 05:30:29.8247 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 481488a6-ceaf-491a-6780-08dea4e742e1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00036F40.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9655 Content-Type: text/plain; charset="utf-8" From: Nimrod Oren Introduce mlx5 DMA pool and pool-page data structures, and add the creation and teardown paths. Each NUMA node owns a set of mlx5_dma_pool instances, each one with a different block size. The sizes are defined as all powers of two starting from MLX5_ADAPTER_PAGE_SHIFT and up to PAGE_SHIFT. Since mlx5_frag_bufs are used to back objects whose sizes are encoded relative to MLX5_ADAPTER_PAGE_SHIFT, a smaller block_shift value cannot be used. Requests larger than PAGE_SIZE continue to be handled as page-sized fragments, as in the existing frag-buf allocation model. Signed-off-by: Nimrod Oren Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/alloc.c | 136 +++++++++++++++++- include/linux/mlx5/driver.h | 7 +- 2 files changed, 140 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/alloc.c b/drivers/net/= ethernet/mellanox/mlx5/core/alloc.c index cebb3559d2c9..918cf027bcbc 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/alloc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/alloc.c @@ -37,10 +37,15 @@ #include #include #include +#include #include =20 #include "mlx5_core.h" =20 +#define MLX5_FRAG_BUF_POOL_MIN_BLOCK_SHIFT MLX5_ADAPTER_PAGE_SHIFT +#define MLX5_FRAG_BUF_POOLS_NUM \ + (PAGE_SHIFT - MLX5_FRAG_BUF_POOL_MIN_BLOCK_SHIFT + 1) + struct mlx5_db_pgdir { struct list_head list; unsigned long *bitmap; @@ -48,6 +53,27 @@ struct mlx5_db_pgdir { dma_addr_t db_dma; }; =20 +struct mlx5_dma_pool { + /* Protects page_list and per-page allocation bitmaps. */ + struct mutex lock; + struct list_head page_list; + struct mlx5_core_dev *dev; + int node; + u8 block_shift; +}; + +struct mlx5_dma_pool_page { + struct mlx5_dma_pool *pool; + struct list_head pool_link; + unsigned long *bitmap; + void *buf; + dma_addr_t dma; +}; + +struct mlx5_frag_buf_node_pools { + struct mlx5_dma_pool *pools[MLX5_FRAG_BUF_POOLS_NUM]; +}; + /* Handling for queue buffers -- we allocate a bunch of memory and * register it in a memory region at HCA virtual address 0. */ @@ -72,13 +98,121 @@ static void *mlx5_dma_zalloc_coherent_node(struct mlx5= _core_dev *dev, } =20 /* Implemented later in the series */ +static void mlx5_dma_pool_page_free(struct mlx5_core_dev *dev, + struct mlx5_dma_pool_page *page) +{ +} + +static void mlx5_dma_pool_destroy(struct mlx5_dma_pool *pool) +{ + struct list_head *page_list =3D &pool->page_list; + struct mlx5_dma_pool_page *page, *tmp; + + if (WARN(!list_empty(page_list), + "mlx5 dma pool destroy with non-empty pool: block_shift=3D%u\n", + pool->block_shift)) + list_for_each_entry_safe(page, tmp, page_list, pool_link) { + list_del(&page->pool_link); + mlx5_dma_pool_page_free(pool->dev, page); + } + + mutex_destroy(&pool->lock); + kfree(pool); +} + +static struct mlx5_dma_pool *mlx5_dma_pool_create(struct mlx5_core_dev *de= v, + int node, u8 block_shift) +{ + struct mlx5_dma_pool *pool; + + if (WARN_ONCE(block_shift > PAGE_SHIFT, + "mlx5 dma pool invalid block_shift: %u (max %d)\n", + block_shift, PAGE_SHIFT)) + return NULL; + + pool =3D kzalloc_obj(*pool); + if (!pool) + return NULL; + + INIT_LIST_HEAD(&pool->page_list); + mutex_init(&pool->lock); + pool->dev =3D dev; + pool->node =3D node; + pool->block_shift =3D block_shift; + return pool; +} + +static void +mlx5_frag_buf_node_pools_destroy(struct mlx5_frag_buf_node_pools *node_poo= ls) +{ + for (int i =3D 0; i < MLX5_FRAG_BUF_POOLS_NUM; i++) + if (node_pools->pools[i]) + mlx5_dma_pool_destroy(node_pools->pools[i]); + kfree(node_pools); +} + +static struct mlx5_frag_buf_node_pools * +mlx5_frag_buf_node_pools_create(struct mlx5_core_dev *dev, int node) +{ + struct mlx5_frag_buf_node_pools *node_pools; + + node_pools =3D kzalloc_obj(*node_pools); + if (!node_pools) + return NULL; + + for (int i =3D 0; i < MLX5_FRAG_BUF_POOLS_NUM; i++) { + u8 block_shift =3D MLX5_FRAG_BUF_POOL_MIN_BLOCK_SHIFT + i; + + node_pools->pools[i] =3D mlx5_dma_pool_create(dev, node, + block_shift); + if (!node_pools->pools[i]) { + mlx5_frag_buf_node_pools_destroy(node_pools); + return NULL; + } + } + + return node_pools; +} + void mlx5_frag_buf_pools_cleanup(struct mlx5_core_dev *dev) { + struct mlx5_priv *priv =3D &dev->priv; + int node; + + for_each_node_state(node, N_POSSIBLE) { + struct mlx5_frag_buf_node_pools *node_pools; + + node_pools =3D priv->frag_buf_node_pools[node]; + if (!node_pools) + continue; + mlx5_frag_buf_node_pools_destroy(node_pools); + } + + kfree(priv->frag_buf_node_pools); + priv->frag_buf_node_pools =3D NULL; } =20 -/* Implemented later in the series */ int mlx5_frag_buf_pools_init(struct mlx5_core_dev *dev) { + struct mlx5_priv *priv =3D &dev->priv; + int node; + + priv->frag_buf_node_pools =3D kzalloc_objs(*priv->frag_buf_node_pools, + nr_node_ids); + if (!priv->frag_buf_node_pools) + return -ENOMEM; + + for_each_node_state(node, N_POSSIBLE) { + struct mlx5_frag_buf_node_pools *node_pools; + + node_pools =3D mlx5_frag_buf_node_pools_create(dev, node); + if (!node_pools) { + mlx5_frag_buf_pools_cleanup(dev); + return -ENOMEM; + } + priv->frag_buf_node_pools[node] =3D node_pools; + } + return 0; } =20 diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 04b96c5abb57..71f7615ab553 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -558,6 +558,7 @@ enum mlx5_func_type { MLX5_FUNC_TYPE_NUM, }; =20 +struct mlx5_frag_buf_node_pools; struct mlx5_ft_pool; struct mlx5_priv { /* IRQ table valid only for real pci devices PF or VF */ @@ -581,14 +582,16 @@ struct mlx5_priv { =20 struct mlx5_debugfs_entries dbg; =20 - /* start: alloc staff */ + /* start: alloc stuff */ /* protect buffer allocation according to numa node */ struct mutex alloc_mutex; int numa_node; =20 struct mutex pgdir_mutex; struct list_head pgdir_list; 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Mon, 27 Apr 2026 22:30:11 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , , , , Gal Pressman , Dragos Tatulea , Moshe Shemesh , Nimrod Oren Subject: [PATCH net-next 3/3] net/mlx5: use internal dma pools for frag buf alloc Date: Tue, 28 Apr 2026 08:29:20 +0300 Message-ID: <20260428052920.219201-4-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20260428052920.219201-1-tariqt@nvidia.com> References: <20260428052920.219201-1-tariqt@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001CF:EE_|MN2PR12MB4094:EE_ X-MS-Office365-Filtering-Correlation-Id: 8944020b-59f4-47d8-d847-08dea4e748cd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|18096099003|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: di6ZKjDy1Cg7FSdLoiA0YOfiisMKGR9ex0WiRk6rxmCT6sHf5BaguqA2NjlfKm9lLRC2COlkPDjx139e6fjnc15IpbJS292SobuVtLA0dbfVtlbRlQxjNtIRwBuKzGdYfB1PePhTYiv/DWDjVZE1JZ5nW1GYUnva3TYBNZwLcaEeWXZafnFd6y7wiGuAhN+qYirNvulNbBUjlyQyWSfYTRmWwIdJTSUN79stOSWjcxHTgACoAh31CmDZOcnAV/vDjJmwZoiR5cG3RLeXn4MdXbyfzVD6o1SWvAawM6QYTW6QQtlxzSQfbYQXbRdo3amzAP8DeNFJZxFQRauic1g5+zeQNl6IDdFvmkCHj1oDgl2o4j8fgFBFStwZLA7vyIwZqt8MDqdAAjVx0bLR9bHkeBpg0xeAImrqLMaJkkPfozpjqUYn7nrti5nXBOalAEx/u5wkX7L10n/FrsY/jlU9nXm1UTyUK0KiJaQyOJlW13fYp0+7lveSw/M61TgBKCKstit9pUJ7Zoo4I6ad7zUlejGyk/Rd6poww00CajuXHcegXxU0tI3elIqkXkiwP5V9aeJcRlsUhURExH7B38sP64HZoCWxgA1Z+G81BG/cnLcWgyTu4NNvyw+nlzR2zvCFcDyQ5ROBvV1BHjMbNEVMzBCVR/kXvntjoEJ76nQ/CAa5tRQfsqXEbnd1J0+8Axa0zaCA5do73XVW38wkVBTtHZe96uhLstBxmeheKe1NK2KjzfyxUgDam3g6pvo5rHetln2PsydasaFeUoVGnQJtMg== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(18096099003)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: mJdos45eqV6etMJz/fClM0UMIi8VIcHnd3Qu2P4ilnldhGjxn2TZSJ1ygcelx2dOAG3o/wgt2VaYV6Bh8JooCxBnkDxTS3O6krf+FCOnuIMJY3c0T8eip3QC6ekpZjzwX0sr7niGo4l5P7KcOk0/I7AnADdegnOi3v88xR/XAEVsR6T++4EA4YUXNYI+Jht448ru1jH5krX8uc9GcBz8a1OJ1CE9lY16YuxTqB/rzVNx4r3KxPEol2+0cMhiml5frLwhKu6KM8f/wDvKZUp0qmglfW1u0kSePsiVCSfHR9BNMCf4EnoeaaNPd6pbhin4qNLBZ/qQxKAb+G56VZII2hgeefi61DjRQ5GszhBMbg/Xf9urN0CKt3yN1ZgF3t0rwGwJNFU54xF9iQKK6mmtcQM8z79QDHmAOHhzRsEBdlFCEtm0Kq4xP230BNrp4DGn X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Apr 2026 05:30:39.7705 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8944020b-59f4-47d8-d847-08dea4e748cd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001CF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4094 Content-Type: text/plain; charset="utf-8" From: Nimrod Oren Add mlx5_dma_pool alloc/free paths, and wire mlx5_frag_buf allocation and free paths to use them. mlx5_frag_buf_alloc_node() now selects an mlx5_dma_pool to allocate fragments from, instead of directly allocating full coherent pages. mlx5_frag_buf_free() frees from the respective pool. mlx5_dma_pool_alloc() keeps allocation fast by maintaining pages with available indexes at the head of the list, so the common allocation path can take a free index immediately. New backing pages are allocated only when no free index is available. mlx5_dma_pool_free() returns released indexes to the pool and frees a backing page once all of its indexes become free. This avoids keeping fully free pages for the lifetime of the pool and reduces coherent DMA memory footprint. Signed-off-by: Nimrod Oren Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/alloc.c | 185 ++++++++++++++---- include/linux/mlx5/driver.h | 2 + 2 files changed, 154 insertions(+), 33 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/alloc.c b/drivers/net/= ethernet/mellanox/mlx5/core/alloc.c index 918cf027bcbc..5cced45caf36 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/alloc.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/alloc.c @@ -97,10 +97,44 @@ static void *mlx5_dma_zalloc_coherent_node(struct mlx5_= core_dev *dev, return cpu_handle; } =20 -/* Implemented later in the series */ +static struct mlx5_dma_pool_page * +mlx5_dma_pool_page_alloc(struct mlx5_dma_pool *pool) +{ + int blocks_per_page =3D BIT(PAGE_SHIFT - pool->block_shift); + struct mlx5_dma_pool_page *page; + + page =3D kzalloc_obj(*page); + if (!page) + goto err_out; + + page->pool =3D pool; + page->bitmap =3D bitmap_zalloc(blocks_per_page, GFP_KERNEL); + if (!page->bitmap) + goto err_free_page; + + bitmap_fill(page->bitmap, blocks_per_page); + page->buf =3D mlx5_dma_zalloc_coherent_node(pool->dev, PAGE_SIZE, + &page->dma, pool->node); + if (!page->buf) + goto err_free_bitmap; + + return page; + +err_free_bitmap: + bitmap_free(page->bitmap); +err_free_page: + kfree(page); +err_out: + return NULL; +} + static void mlx5_dma_pool_page_free(struct mlx5_core_dev *dev, struct mlx5_dma_pool_page *page) { + dma_free_coherent(mlx5_core_dma_dev(dev), PAGE_SIZE, page->buf, + page->dma); + bitmap_free(page->bitmap); + kfree(page); } =20 static void mlx5_dma_pool_destroy(struct mlx5_dma_pool *pool) @@ -142,6 +176,83 @@ static struct mlx5_dma_pool *mlx5_dma_pool_create(stru= ct mlx5_core_dev *dev, return pool; } =20 +static int mlx5_dma_pool_alloc_from_page(struct mlx5_dma_pool *pool, + struct mlx5_dma_pool_page *page, + unsigned long *idx_out) +{ + int blocks_per_page =3D BIT(PAGE_SHIFT - pool->block_shift); + + *idx_out =3D find_first_bit(page->bitmap, blocks_per_page); + if (*idx_out >=3D blocks_per_page) + return -ENOMEM; + + __clear_bit(*idx_out, page->bitmap); + + if (bitmap_empty(page->bitmap, blocks_per_page)) + list_move_tail(&page->pool_link, &pool->page_list); + + return 0; +} + +static struct mlx5_dma_pool_page * +mlx5_dma_pool_alloc(struct mlx5_dma_pool *pool, unsigned long *idx_out) +{ + struct mlx5_dma_pool_page *page; + + mutex_lock(&pool->lock); + + page =3D list_first_entry_or_null(&pool->page_list, + struct mlx5_dma_pool_page, pool_link); + if (page && !mlx5_dma_pool_alloc_from_page(pool, page, idx_out)) + goto unlock; /* successfully allocated from existing page */ + + page =3D mlx5_dma_pool_page_alloc(pool); + if (!page) + goto unlock; + + list_add(&page->pool_link, &pool->page_list); + mlx5_dma_pool_alloc_from_page(pool, page, idx_out); + +unlock: + mutex_unlock(&pool->lock); + return page; +} + +static void mlx5_dma_pool_free(struct mlx5_dma_pool *pool, + struct mlx5_dma_pool_page *page, + unsigned long idx) +{ + int blocks_per_page =3D BIT(PAGE_SHIFT - pool->block_shift); + bool was_full; + + if (WARN_ONCE(idx >=3D blocks_per_page, + "mlx5 dma pool invalid idx: %lu (max %d)\n", + idx, blocks_per_page - 1)) + return; + + mutex_lock(&pool->lock); + if (WARN_ONCE(test_bit(idx, page->bitmap), + "mlx5 dma pool double free: idx=3D%lu block_shift=3D%u\n", + idx, pool->block_shift)) + goto unlock; + + was_full =3D bitmap_empty(page->bitmap, blocks_per_page); + __set_bit(idx, page->bitmap); + + if (bitmap_full(page->bitmap, blocks_per_page)) { + list_del(&page->pool_link); + mlx5_dma_pool_page_free(pool->dev, page); + } else { + memset((u8 *)page->buf + (idx << pool->block_shift), 0, + BIT(pool->block_shift)); + if (was_full) + list_move(&page->pool_link, &pool->page_list); + } + +unlock: + mutex_unlock(&pool->lock); +} + static void mlx5_frag_buf_node_pools_destroy(struct mlx5_frag_buf_node_pools *node_poo= ls) { @@ -219,56 +330,64 @@ int mlx5_frag_buf_pools_init(struct mlx5_core_dev *de= v) int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, struct mlx5_frag_buf *buf, int node) { - int i; + struct mlx5_dma_pool *pool; + int pool_idx; + + if (WARN_ONCE(size <=3D 0, "mlx5_frag_buf non-positive size: %d\n", size)) + return -EINVAL; + + node =3D node =3D=3D NUMA_NO_NODE ? first_online_node : node; + + if (WARN_ONCE(node < 0 || node >=3D nr_node_ids || !node_possible(node), + "mlx5_frag_buf invalid node ID: %d\n", node)) + return -EINVAL; =20 buf->size =3D size; buf->npages =3D DIV_ROUND_UP(size, PAGE_SIZE); - buf->page_shift =3D PAGE_SHIFT; - buf->frags =3D kzalloc_objs(struct mlx5_buf_list, buf->npages); + buf->page_shift =3D clamp_t(int, order_base_2(size), + MLX5_FRAG_BUF_POOL_MIN_BLOCK_SHIFT, + PAGE_SHIFT); + buf->frags =3D kcalloc_node(buf->npages, sizeof(*buf->frags), + GFP_KERNEL, node); if (!buf->frags) - goto err_out; + return -ENOMEM; =20 - for (i =3D 0; i < buf->npages; i++) { + pool_idx =3D buf->page_shift - MLX5_FRAG_BUF_POOL_MIN_BLOCK_SHIFT; + pool =3D dev->priv.frag_buf_node_pools[node]->pools[pool_idx]; + for (int i =3D 0; i < buf->npages; i++) { struct mlx5_buf_list *frag =3D &buf->frags[i]; - int frag_sz =3D min_t(int, size, PAGE_SIZE); + struct mlx5_dma_pool_page *page; + unsigned long idx; =20 - frag->buf =3D mlx5_dma_zalloc_coherent_node(dev, frag_sz, - &frag->map, node); - if (!frag->buf) - goto err_free_buf; - if (frag->map & ((1 << buf->page_shift) - 1)) { - dma_free_coherent(mlx5_core_dma_dev(dev), frag_sz, - buf->frags[i].buf, buf->frags[i].map); - mlx5_core_warn(dev, "unexpected map alignment: %pad, page_shift=3D%d\n", - &frag->map, buf->page_shift); - goto err_free_buf; + page =3D mlx5_dma_pool_alloc(pool, &idx); + if (!page) { + mlx5_frag_buf_free(dev, buf); + return -ENOMEM; } - size -=3D frag_sz; + frag->buf =3D (u8 *)page->buf + (idx << pool->block_shift); + frag->map =3D page->dma + (idx << pool->block_shift); + frag->frag_page =3D page; } =20 return 0; - -err_free_buf: - while (i--) - dma_free_coherent(mlx5_core_dma_dev(dev), PAGE_SIZE, buf->frags[i].buf, - buf->frags[i].map); - kfree(buf->frags); -err_out: - return -ENOMEM; } EXPORT_SYMBOL_GPL(mlx5_frag_buf_alloc_node); =20 void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *b= uf) { - int size =3D buf->size; - int i; + for (int i =3D 0; i < buf->npages; i++) { + struct mlx5_buf_list *frag =3D &buf->frags[i]; + struct mlx5_dma_pool_page *page; + struct mlx5_dma_pool *pool; + unsigned long idx; =20 - for (i =3D 0; i < buf->npages; i++) { - int frag_sz =3D min_t(int, size, PAGE_SIZE); + if (!frag->buf) + continue; =20 - dma_free_coherent(mlx5_core_dma_dev(dev), frag_sz, buf->frags[i].buf, - buf->frags[i].map); - size -=3D frag_sz; + page =3D frag->frag_page; + pool =3D page->pool; + idx =3D (frag->map - page->dma) >> pool->block_shift; + mlx5_dma_pool_free(pool, page, idx); } kfree(buf->frags); } diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 71f7615ab553..531ce66fc8ef 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -343,9 +343,11 @@ struct mlx5_cmd_mailbox { struct mlx5_cmd_mailbox *next; }; =20 +struct mlx5_dma_pool_page; struct mlx5_buf_list { void *buf; dma_addr_t map; + struct mlx5_dma_pool_page *frag_page; }; =20 struct mlx5_frag_buf { --=20 2.44.0