From nobody Wed Jun 17 01:32:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C30DB466B6C; Tue, 28 Apr 2026 16:12:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777392757; cv=none; b=NAEgttnGGGJ1a2I8lN5aHoS5e+WA4rdep+6XK3TV0Bn4E40Oh8EFkNOD6kkFR+mNrXgWHvRckzJ8T5E325DX+tOje0AzPtXOFfr3qAXaPMyaVdvKBpwj/TSE0URij3OEa6wkawpOTYT1sWLjY5outxQa03RBuiFjhcuyA8OuXx4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777392757; c=relaxed/simple; bh=9Q6uV8cKHad5ySSh3Qs/emYBBb+y+VKWfJEEabOhhLQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VgHR2l8jOTRDfId7Rf9hOWX3hHctbbO3OcExpi9Y+fhr8/b+18cXulp/UONzA8KbfPcTgOPbPeJmJl4nMbAkoo9tb7FZq2lLTDKRfj3VLMNpmwBL2h9Xz1OYK4XX1EABw6GFl/muUbzw7HYrPoYLxUczqsyuDlWHPlqiPDzIufk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GKPD44dd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GKPD44dd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F546C2BCB7; Tue, 28 Apr 2026 16:12:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777392757; bh=9Q6uV8cKHad5ySSh3Qs/emYBBb+y+VKWfJEEabOhhLQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GKPD44ddg81+hmbOp0rlAw36AFFOrm6LrIJe3e6gAjC9k9vYce2OzzYmTUESiWiNA 69SmnVh56UyOT6bxb5Bo4i712UyaH2nxKWADzIvqGCg1rRoKsiccJnSRnPPQJ0MZg2 ccSDjyi8lJOPblR/42XdpiuamjAgPNN6dT0QEz/b+DXadE+3NB1sQAyOpAQiYbbdcV 9aNe8WKQ/HAjXcScFUnYJ27u1lb5Lx6MIjYZM8JqJCFkY59VE12UCKqqLc6BAXIZrp tN9vno7jjEUTr+Q0AhO9XbZcZRAaagAThhefk0uu2tOdpcnoipjgHFqNS1E67Ot3t+ kqeBqFT01l5Ow== From: Conor Dooley To: broonie@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Cyril Jean , Valentina.FernandezAlanis@microchip.com, linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH v2 1/3] spi: microchip-core-qspi: control built-in cs manually Date: Tue, 28 Apr 2026 17:12:05 +0100 Message-ID: <20260428-perceive-kettle-d42b33eb62bc@spud> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260428-plexiglas-smith-6ae4e9ba8abd@spud> References: <20260428-plexiglas-smith-6ae4e9ba8abd@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6855; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=iAT8mZu73GAc16eXh1LQW5xBkIPRUwf7fIgsuFj5Lzs=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkf7iSw9iaq7ent65h7eabf/JdXVumrGh1c+Pmt/Jr0Q 9YL4lt3d5SyMIhxMciKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiGZ8ZGZ4medzKnlgZcd9Z ZnWR7btzd7p+leWGfTQ+bbFMt77A6C0jw+vI0IT+5sq7b87J6d4WKvq+mE3Rb3Kjpli+gNn3ezt PcAMA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The coreQSPI IP supports only a single chip select, which is automagically operated by the hardware - set low when the transmit buffer first gets written to and set high when the number of bytes written to the TOTALBYTES field of the FRAMES register have been sent on the bus. Additional devices must use GPIOs for their chip selects. It was reported to me that if there are two devices attached to this QSPI controller that the in-built chip select is set low while linux tries to access the device attached to the GPIO. This went undetected as the boards that connected multiple devices to the SPI controller all exclusively used GPIOs for chip selects, not relying on the built-in chip select at all. It turns out that this was because the built-in chip select, when controlled automagically, is set low when active and high when inactive, thereby ruling out its use for active-high devices or devices that need to transmit with the chip select disabled. Modify the driver so that it controls chip select directly, retaining the behaviour for mem_ops of setting the chip select active for the entire duration of the transfer in the exec_op callback. For regular transfers, implement the set_cs callback for the core to use. As part of this, the existing setup callback, mchp_coreqspi_setup_op(), is removed. Modifying the CLKIDLE field is not safe to do during operation when there are multiple devices, so this code is removed entirely. Setting the MASTER and ENABLE fields is something that can be done once at probe, it doesn't need to be re-run for each device. Instead the new setup callback sets the built-in chip select to its inactive state for active-low devices, as the reset value of the chip select in software controlled mode is low. Fixes: 8f9cf02c88528 ("spi: microchip-core-qspi: Add regular transfers") Fixes: 8596124c4c1bc ("spi: microchip-core-qspi: Add support for microchip = fpga qspi controllers") CC: stable@vger.kernel.org Signed-off-by: Conor Dooley --- drivers/spi/spi-microchip-core-qspi.c | 82 ++++++++++++++++++++++----- 1 file changed, 67 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microc= hip-core-qspi.c index eab059fb0bc2c..7bd2c9dcd4771 100644 --- a/drivers/spi/spi-microchip-core-qspi.c +++ b/drivers/spi/spi-microchip-core-qspi.c @@ -74,6 +74,13 @@ #define STATUS_FLAGSX4 BIT(8) #define STATUS_MASK GENMASK(8, 0) =20 +/* + * QSPI Direct Access register defines + */ +#define DIRECT_ACCESS_EN_SSEL BIT(0) +#define DIRECT_ACCESS_OP_SSEL BIT(1) +#define DIRECT_ACCESS_OP_SSEL_SHIFT 1 + #define BYTESUPPER_MASK GENMASK(31, 16) #define BYTESLOWER_MASK GENMASK(15, 0) =20 @@ -158,6 +165,41 @@ static int mchp_coreqspi_set_mode(struct mchp_coreqspi= *qspi, const struct spi_m return 0; } =20 +static void mchp_coreqspi_set_cs(struct spi_device *spi, bool enable) +{ + struct mchp_coreqspi *qspi =3D spi_controller_get_devdata(spi->controller= ); + u32 val; + + val =3D readl(qspi->regs + REG_DIRECT_ACCESS); + + val &=3D ~BIT(1); + if (spi->mode & SPI_CS_HIGH) + val |=3D enable << DIRECT_ACCESS_OP_SSEL_SHIFT; + else + val |=3D !enable << DIRECT_ACCESS_OP_SSEL_SHIFT; + + writel(val, qspi->regs + REG_DIRECT_ACCESS); +} + +static int mchp_coreqspi_setup(struct spi_device *spi) +{ + struct mchp_coreqspi *qspi =3D spi_controller_get_devdata(spi->controller= ); + u32 val; + + /* + * Active low devices need to be specifically set to their inactive + * states during probe. + */ + if (spi->mode & SPI_CS_HIGH) + return 0; + + val =3D readl(qspi->regs + REG_DIRECT_ACCESS); + val |=3D DIRECT_ACCESS_OP_SSEL; + writel(val, qspi->regs + REG_DIRECT_ACCESS); + + return 0; +} + static inline void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi) { u32 control, data; @@ -380,19 +422,6 @@ static int mchp_coreqspi_setup_clock(struct mchp_coreq= spi *qspi, struct spi_devi return 0; } =20 -static int mchp_coreqspi_setup_op(struct spi_device *spi_dev) -{ - struct spi_controller *ctlr =3D spi_dev->controller; - struct mchp_coreqspi *qspi =3D spi_controller_get_devdata(ctlr); - u32 control =3D readl_relaxed(qspi->regs + REG_CONTROL); - - control |=3D (CONTROL_MASTER | CONTROL_ENABLE); - control &=3D ~CONTROL_CLKIDLE; - writel_relaxed(control, qspi->regs + REG_CONTROL); - - return 0; -} - static inline void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, con= st struct spi_mem_op *op) { u32 idle_cycles =3D 0; @@ -483,6 +512,7 @@ static int mchp_coreqspi_exec_op(struct spi_mem *mem, c= onst struct spi_mem_op *o =20 reinit_completion(&qspi->data_completion); mchp_coreqspi_config_op(qspi, op); + mchp_coreqspi_set_cs(mem->spi, true); if (op->cmd.opcode) { qspi->txbuf =3D &opcode; qspi->rxbuf =3D NULL; @@ -523,6 +553,7 @@ static int mchp_coreqspi_exec_op(struct spi_mem *mem, c= onst struct spi_mem_op *o err =3D -ETIMEDOUT; =20 error: + mchp_coreqspi_set_cs(mem->spi, false); mutex_unlock(&qspi->op_lock); mchp_coreqspi_disable_ints(qspi); =20 @@ -686,6 +717,7 @@ static int mchp_coreqspi_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; int ret; + u32 num_cs, val; =20 ctlr =3D devm_spi_alloc_host(&pdev->dev, sizeof(*qspi)); if (!ctlr) @@ -718,10 +750,18 @@ static int mchp_coreqspi_probe(struct platform_device= *pdev) return ret; } =20 + /* + * The IP core only has a single CS, any more have to be provided via + * gpios + */ + if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs)) + num_cs =3D 1; + + ctlr->num_chipselect =3D num_cs; + ctlr->bits_per_word_mask =3D SPI_BPW_MASK(8); ctlr->mem_ops =3D &mchp_coreqspi_mem_ops; ctlr->mem_caps =3D &mchp_coreqspi_mem_caps; - ctlr->setup =3D mchp_coreqspi_setup_op; ctlr->mode_bits =3D SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; ctlr->dev.of_node =3D np; @@ -729,9 +769,21 @@ static int mchp_coreqspi_probe(struct platform_device = *pdev) ctlr->prepare_message =3D mchp_coreqspi_prepare_message; ctlr->unprepare_message =3D mchp_coreqspi_unprepare_message; ctlr->transfer_one =3D mchp_coreqspi_transfer_one; - ctlr->num_chipselect =3D 2; + ctlr->setup =3D mchp_coreqspi_setup; + ctlr->set_cs =3D mchp_coreqspi_set_cs; ctlr->use_gpio_descriptors =3D true; =20 + val =3D readl_relaxed(qspi->regs + REG_CONTROL); + val |=3D (CONTROL_MASTER | CONTROL_ENABLE); + writel_relaxed(val, qspi->regs + REG_CONTROL); + + /* + * Put cs into software controlled mode + */ + val =3D readl_relaxed(qspi->regs + REG_DIRECT_ACCESS); + val |=3D DIRECT_ACCESS_EN_SSEL; + writel(val, qspi->regs + REG_DIRECT_ACCESS); + ret =3D spi_register_controller(ctlr); if (ret) return dev_err_probe(&pdev->dev, ret, --=20 2.53.0 From nobody Wed Jun 17 01:32:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24F2C3C1406; Tue, 28 Apr 2026 16:12:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777392760; cv=none; b=EZrr+E7odIBGkp5A+sKsvEgpYnchsGtD0QFS1D4zIBnCK/eRzaVQ2fLQvoTq0VFdHWckNMEQvtbuPHq3Y6bRCB8pYvdA09F6F+ZTqsGBkz9stePwBvPh/hW/eAnlTQtdhAgYrITK6pIuAwrF9GOF6EIS9ZXGB64ePhPo70l4nB8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777392760; c=relaxed/simple; bh=kxxeRh+fiRBAkPPQ6Ege8TcSd/UDjWuIziK+9tp8mck=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tLamg0aOnJcp1g/UNDIJnP7Vl0xejyPoc7lakC2VsbL/Y1fPXd2+ISinjOR3ThADNE6JGF1ln8JbB7xo5cXlSbCO0x39JMwOI/MOM5eMV3LdLH/ud+RXxIrAOnwvSAQALdddXh8fUzoa3NKM/PWnTF273v4uIy0+O006m6Y/GaQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Zr5uUgjA; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Zr5uUgjA" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CC618C2BCB5; Tue, 28 Apr 2026 16:12:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777392759; bh=kxxeRh+fiRBAkPPQ6Ege8TcSd/UDjWuIziK+9tp8mck=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Zr5uUgjAiwDDNiO5RdBkwMQqczxPCPHO8vmjveAqjkFhvjgL1qKFOsnf5BCTmdp40 NDbbhIkbfGDlnpZdrhDwfo/y8Zx/jyTsaFJyLQDoFQ3/uCPKbzZGzo/enWsgT30JrB ct6s6Wrvolvm9BIPAj46bK72BjJjSwMPSdlh8rvlOTzC8w8D+fZuDWvccC72Oq7BTN IYWnqc+F/b+Yo9UvHvbAfvoMD19uheFZRamYFKg9fqCw5oSyriK1rIR09NCRY9IFmX ccphEexyQpOF5vv945jVUOBmm5he616hUzVKUsIPzJgHlM3HYKy5ItwlOje2JDSNLR yks4T5YWJ2UEw== From: Conor Dooley To: broonie@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Cyril Jean , Valentina.FernandezAlanis@microchip.com, linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH v2 2/3] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations Date: Tue, 28 Apr 2026 17:12:06 +0100 Message-ID: <20260428-directly-stroller-f6551c3dca16@spud> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260428-plexiglas-smith-6ae4e9ba8abd@spud> References: <20260428-plexiglas-smith-6ae4e9ba8abd@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1832; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=659GQtxfjWiZygrLJrj8jZ6QG6PovzBK+5ouTwOvfAE=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkf7iQ6T/rAp1WhaGNTK3tC7EQiG0NR0nqvOU+V+S23R R9VsdnQUcrCIMbFICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgInUtzMytEzQPZtxoU/LazHD MsWEjsMT2xd26bJ6++71mrWifdcvA4Y/fAlv9jUe6PYNeRd4/F7svnWOna5ru96m3KsxnO//hms iHwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The core will deal with reads by creating clock cycles itself, there's no need to generate clock cycles by transmitting garbage data at the driver level. Further, transmitting garbage data just bricks the transfer since QSPI doesn't have a dedicated master-out line like MOSI in regular SPI. I'm not entirely sure if the transfer is bricked because of the garbage data being transmitted on the bus or because the core loses track of whether it is supposed to be sending or receiving data. Fixes: 8f9cf02c88528 ("spi: microchip-core-qspi: Add regular transfers") CC: stable@vger.kernel.org Signed-off-by: Conor Dooley --- drivers/spi/spi-microchip-core-qspi.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microc= hip-core-qspi.c index 7bd2c9dcd4771..dd3644ee80c6f 100644 --- a/drivers/spi/spi-microchip-core-qspi.c +++ b/drivers/spi/spi-microchip-core-qspi.c @@ -693,18 +693,28 @@ static int mchp_coreqspi_transfer_one(struct spi_cont= roller *ctlr, struct spi_de struct spi_transfer *t) { struct mchp_coreqspi *qspi =3D spi_controller_get_devdata(ctlr); + bool dual_quad =3D false; =20 qspi->tx_len =3D t->len; =20 + if (t->tx_nbits =3D=3D SPI_NBITS_QUAD || t->rx_nbits =3D=3D SPI_NBITS_QUA= D || + t->tx_nbits =3D=3D SPI_NBITS_DUAL || + t->rx_nbits =3D=3D SPI_NBITS_DUAL) + dual_quad =3D true; + if (t->tx_buf) qspi->txbuf =3D (u8 *)t->tx_buf; =20 if (!t->rx_buf) { mchp_coreqspi_write_op(qspi); - } else { + } else if (!dual_quad) { qspi->rxbuf =3D (u8 *)t->rx_buf; qspi->rx_len =3D t->len; mchp_coreqspi_write_read_op(qspi); + } else { + qspi->rxbuf =3D (u8 *)t->rx_buf; + qspi->rx_len =3D t->len; + mchp_coreqspi_read_op(qspi); } =20 return 0; --=20 2.53.0 From nobody Wed Jun 17 01:32:51 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6263546AF35; Tue, 28 Apr 2026 16:12:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777392762; cv=none; b=n9lILJ44ULuC+3x3H1VIUsWR6F0uwW9DTtmuKc7BIVC6qBzGzBYM4aRRzMxlFDcRnhFMD0DpL8WfcpCA+mEfg7KH1yqT+CMgsOfkkPyNQEFLJ11O3pIs4YJi8W99lT34bZNQUuwkqki3CKO4Znl1GOcJn2zWq4WEd/d++A8XoMU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777392762; c=relaxed/simple; bh=dhffF3ZrJYq66Fq83zPDuRzj54IhmH5nUsYS1m4ih+o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Kr/IU8eprXsdjLV3hrYbyqHqFIO+byD6vH3ETpR1+kDs/zK/THatWFNUr4gY8J1Z9h0XphnstvWbb7uWlnGjP8HTG9feijJVHv5TTP+cCo7Ttv8Ou09q0z/QxyAPQqoJvc+35nHDEtNqgbT1PAuRGUxCKBkJhTmGYJWGZbSxtKk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=osTcUcN2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="osTcUcN2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 34B8EC2BCAF; Tue, 28 Apr 2026 16:12:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777392762; bh=dhffF3ZrJYq66Fq83zPDuRzj54IhmH5nUsYS1m4ih+o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=osTcUcN2LylikR7wp+pHUM0f5BPypaqsCxDAv4lNwPeg6bvKUnv8V3vjCNQSPAxer t2X7bg9YKhl+dF9Z5lgmYdc3iZEy8qeNItQa2kwaDguXMX0vSBCsxLfuDU0qSRTSWv Vn+1qvWWMHzdP7Ty2EROcCHTH2OV5Oh9QcW5h14Dx3iCekOWCLq/iOyG3ZzOJPYuvx VtDMrKGhkCJw4ZqKRITnHarI1y9Uz/HV5uzwzZrzpruCZe/sMtux5ViTN9t8iDiT08 ljCmQcVsSLVNiTXkM/8DgqKpA+9uY2wDnoqALkpmmDGwwK/jugci+OCg70wGnPFInW nE6AAh6nxoMfQ== From: Conor Dooley To: broonie@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Cyril Jean , Valentina.FernandezAlanis@microchip.com, linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] spi: microchip-core-qspi: remove some inline markings Date: Tue, 28 Apr 2026 17:12:07 +0100 Message-ID: <20260428-acting-yearning-24bfa6d66c7e@spud> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260428-plexiglas-smith-6ae4e9ba8abd@spud> References: <20260428-plexiglas-smith-6ae4e9ba8abd@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1848; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=/xpbTb3+/lPBLIXkcANfDJ1Gn4CZegvxDmd2/FsdDZk=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkf7iTWWf5Zw69usvn0twVldVf4/848NO+Z6Q+9mqYbd 56ukxH/1VHKwiDGxSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJzJBjZNh5gS1BmvHYgVVJ +Yk3ltxgFexL0blwu2bxe41iR4YrEhsYGd5feq1stOfEtpPFN0NXahVpmm79HCj5ok9M1brER4G 5hgkA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Remove inline markings from a number of functions that are called as part of mem ops callbacks. None of them are either particularly trivial or sensitive to overhead of a function call. Just let the compiler decide what to do with them. Signed-off-by: Conor Dooley --- drivers/spi/spi-microchip-core-qspi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microc= hip-core-qspi.c index dd3644ee80c6f..d15cf5664da5e 100644 --- a/drivers/spi/spi-microchip-core-qspi.c +++ b/drivers/spi/spi-microchip-core-qspi.c @@ -200,7 +200,7 @@ static int mchp_coreqspi_setup(struct spi_device *spi) return 0; } =20 -static inline void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi) +static void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi) { u32 control, data; =20 @@ -236,7 +236,7 @@ static inline void mchp_coreqspi_read_op(struct mchp_co= reqspi *qspi) } } =20 -static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi) +static void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi) { u32 control, data; =20 @@ -264,7 +264,7 @@ static inline void mchp_coreqspi_write_op(struct mchp_c= oreqspi *qspi) } } =20 -static inline void mchp_coreqspi_write_read_op(struct mchp_coreqspi *qspi) +static void mchp_coreqspi_write_read_op(struct mchp_coreqspi *qspi) { u32 control, data; =20 @@ -422,7 +422,7 @@ static int mchp_coreqspi_setup_clock(struct mchp_coreqs= pi *qspi, struct spi_devi return 0; } =20 -static inline void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, con= st struct spi_mem_op *op) +static void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, const stru= ct spi_mem_op *op) { u32 idle_cycles =3D 0; int total_bytes, cmd_bytes, frames, ctrl; --=20 2.53.0