From nobody Wed Jun 17 04:16:06 2026 Received: from smtpout-04.galae.net (smtpout-04.galae.net [185.171.202.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E19DD3D7D97 for ; Tue, 28 Apr 2026 08:53:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.171.202.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777366433; cv=none; b=ROfSok6LwL9FXpYKNFeJSyr5Ksai5IzlVr4sJC5KEWaJdIVMkHunTLGUlgNyE9bIWmRP1x3yARQOpialssr/JKWi/Il4IvBmmnb6nWhmKAYQa2Jiab/IohHiR/RDHGrVo03RFpPb3+4/q+b4vg3UV/wHu4Gxd+dw2Ntks6MFd1I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777366433; c=relaxed/simple; bh=sY9+3bENskEECqy179xCrubdH5603AcfuuXqXbiU1Ts=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:To:Cc; b=Te8XE7alyZXP0yLsvAiS9DUv6wg5DwjJy9ZFDH9YfC9I+yygbOXnoBI+g6GqDsiljT1eMzMSlF9edIKCuKM7N792nAh1nQFjvCFWTia0XqLHm13qs+7ovuoIIlU/mJY1ZB1iAqeVUW4VOGPF9arCd7pWIPb6v6pT+UvqLHbKQLc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=hMmHvkOp; arc=none smtp.client-ip=185.171.202.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="hMmHvkOp" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-04.galae.net (Postfix) with ESMTPS id D2FAFC5CD52; Tue, 28 Apr 2026 08:54:33 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 480C6601D0; Tue, 28 Apr 2026 08:53:50 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id CAC41107284E5; Tue, 28 Apr 2026 10:53:45 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1777366429; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding; bh=ot9nm/pABtLTPSGzXe0swiSAfOvabkyS/b+zLNGI4wM=; b=hMmHvkOpAARovz4G6rVIkwrisOvaml+RgESItu+Mu9YZE8vZ+hqc/1/L3Tod43SgmQn1uL hz/RPLq28++lpLFTfigtI0YvwSO5R7pUIKVwYWUNgUKdqp+qI8SX2qFbBj/S7nU0op/nIg 4cRaL0xVcT7HHUJNJhgr4UeJvravpS57n8/bThh+AHro2KYpcDsG7mIheGsJ6K4A4V0uLu YmJIuRSmrWynkWfvx73P19M8nuupJvmOo1TzU8pdRRlhFsG0RZ8CL/BmMTwczFJJZmcfg0 5EgWOws940xEht6Pmfh7rtzI1zxTlf8TZyelxAX2ZrYwf02AcwzOZNGJUucDfA== From: "Thomas Richard (TI)" Date: Tue, 28 Apr 2026 10:53:41 +0200 Subject: [PATCH] arm64: dts: ti: k3-j721s2-som-p0: add bootph-pre-ram property to pmic@4c Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260428-k3-j721s2-som-bootph-pre-ram-pmic-4c-v1-1-e8202ce955a0@bootlin.com> X-B4-Tracking: v=1; b=H4sIAJR18GkC/x2NwQrCMBAFf6Xs2QfpNhr0V8RDErd2lTQhERFK/ 93gcRiY2ahJVWl0GTaq8tGmee0wHgaKi18fAr13JjZ8MpYdXhOejsfGaDkh5PwuC0oVVJ9Qkkb YCGftHM4mmKOfqKe6n/X731xv+/4DqU5SFXYAAAA= X-Change-ID: 20260427-k3-j721s2-som-bootph-pre-ram-pmic-4c-744fb90b05a3 To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Thomas Petazzoni , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, gregory.clement@bootlin.com, richard.genoud@bootlin.com, u-kumar1@ti.com, a-kumar2@ti.com, "Thomas Richard (TI)" X-Mailer: b4 0.14.3 X-Last-TLS-Session-Version: TLSv1.3 On j721s2, pmic@4c is needed to exit the DDR from retention after suspend-to-ram. Add bootph-pre-ram property to make pmic@4c available to the bootloader in the phase that sets up the DDR. Signed-off-by: Thomas Richard (TI) --- arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi b/arch/arm64/boot= /dts/ti/k3-j721s2-som-p0.dtsi index 12a38dd1514b..a19e535f4946 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi @@ -250,6 +250,7 @@ buckb1: buck1 { regulator-max-microvolt =3D <1800000>; regulator-always-on; regulator-boot-on; + bootph-pre-ram; }; =20 buckb2: buck2 { --- base-commit: 59b04cb2325c07ddc1cc7d984bd8c8f89f161746 change-id: 20260427-k3-j721s2-som-bootph-pre-ram-pmic-4c-744fb90b05a3 Best regards, --=20 Thomas Richard (TI)