From nobody Wed Jun 17 01:38:04 2026 Received: from s106b.cyber-folks.pl (s106b.cyber-folks.pl [195.78.66.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF5DADDA9; Tue, 28 Apr 2026 16:29:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.78.66.88 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777393773; cv=none; b=mNUgPfn44NhkFo/24ofuenUxfp1a5RSDDTlvYsmOKrzvpbPRZRzkLaiI7ER/rvGQz25jlWHws1YSCLCEQ6+GGHPI2roQn4/HOciV1EYVYDMhrAusej7zmYItkD6KJZkIL8n3/1OQwzDnGjXClCkJIwsJNljwvEdpMxNC1F5u6ts= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777393773; c=relaxed/simple; bh=qh9sEc57bKsGot5lE2/m8eNigSmNqLcdmef/IL3Fdfc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=A9n2su2gOc4caIIblrfASNNJ4VhRNjWT7TD/cEq8RG6zUvJXDAkAyOSarIW7vU2mnw8xaEej4YHI2lOz81nbQ7au1IoMg6soRBtnaBXlUAXoiGIXPLLbaGKVoXVSPNGNm6QfaF5XJwHMay1kMKF3YE6qHpUHG1/LXXqGge1GywU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=mmpsystems.pl; spf=pass smtp.mailfrom=mmpsystems.pl; dkim=pass (2048-bit key) header.d=mmpsystems.pl header.i=@mmpsystems.pl header.b=x8GowFnr; arc=none smtp.client-ip=195.78.66.88 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=mmpsystems.pl Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mmpsystems.pl Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=mmpsystems.pl header.i=@mmpsystems.pl header.b="x8GowFnr" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mmpsystems.pl; s=x; h=Cc:To:In-Reply-To:References:Message-Id: Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date:From:Sender: Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender :Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=Qe8+erd3ATmRXcw/RE05XoQwx+r6eTzDQ+NZAClJ7ws=; b=x8GowFnrAjfX8ib/qwlXmO6cnM wwzYEean0JaCy0vYjT6nXjrGzDQelBRPnVfAZkWUjte2g4BWVtYKsp06Z8PfcJsHP9VFWd/u9ZeUI 1R2cst1qfcASPkDEwxpHMu7f8aj2psVx546rdPO0hqWCHvAf8X3f+DzLXonr2L9B0aJPt2sre8mlG IYAaeo0Y15C4gomD9fZj9J04u6NiJ5yULl6n8VG7rrmuU+PH+MVhi7zO+YghmxieQuoEme5WTqjB8 tJeUn9MojQPlK5xnlbmoK18Xg2q+Tfn+0NK146Oz6uOAkUn7iuVNLzNTf70drDmHHt9JfSfztEnk1 /3URn4kA==; Received: from user-188-33-36-99.play-internet.pl ([188.33.36.99] helo=localhost) by s106.cyber-folks.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wHlJQ-0000000Ay6i-1iSc; Tue, 28 Apr 2026 18:29:28 +0200 From: Michal Piekos Date: Tue, 28 Apr 2026 18:26:58 +0200 Subject: [PATCH v3 1/4] dt-bindings: timer: allwinner,sun5i-a13-hstimer: add H616 and D1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260428-h616-t113s-hstimer-v3-1-7e02178a93ee@mmpsystems.pl> References: <20260428-h616-t113s-hstimer-v3-0-7e02178a93ee@mmpsystems.pl> In-Reply-To: <20260428-h616-t113s-hstimer-v3-0-7e02178a93ee@mmpsystems.pl> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard Cc: Michal Piekos , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Andre Przywara , Conor Dooley X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777393718; l=1635; i=michal.piekos@mmpsystems.pl; s=20260301; h=from:subject:message-id; bh=qh9sEc57bKsGot5lE2/m8eNigSmNqLcdmef/IL3Fdfc=; b=qZpLCw+wrAJsF4G8/+1yRLu0Hy+1pGSqIursXJzKh2gfawBEHa96O7LKTtjNdtJ3/lkXgakcC ggXYALl7/QBClz8aezK217dHYM0oQZH0QAzwDhORe1NZCfFzvo7j7tA X-Developer-Key: i=michal.piekos@mmpsystems.pl; a=ed25519; pk=Aixyx03If7ZDamiKKN0lsa+0mtA+WjIuIf2ZQVYNBqg= X-Authenticated-Id: michal.piekos@mmpsystems.pl D1 is similar to existing sun5i, but with different register offsets. H616 uses same offsets as D1. Add allwinner,sun20i-d1-hstimer Add allwinner,sun50i-h616-hstimer with fallback to allwinner,sun20i-d1-hstimer Extend schema condition for interrupts to cover D1 compatible variant. Signed-off-by: Michal Piekos Acked-by: Conor Dooley --- .../devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml | 9 +++++= +++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hs= timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hs= timer.yaml index f1853daec2f9..3e2725c56995 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.y= aml +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.y= aml @@ -15,9 +15,13 @@ properties: oneOf: - const: allwinner,sun5i-a13-hstimer - const: allwinner,sun7i-a20-hstimer + - const: allwinner,sun20i-d1-hstimer - items: - const: allwinner,sun6i-a31-hstimer - const: allwinner,sun7i-a20-hstimer + - items: + - const: allwinner,sun50i-h616-hstimer + - const: allwinner,sun20i-d1-hstimer =20 reg: maxItems: 1 @@ -45,7 +49,10 @@ required: if: properties: compatible: - const: allwinner,sun5i-a13-hstimer + anyOf: + - const: allwinner,sun5i-a13-hstimer + - contains: + const: allwinner,sun20i-d1-hstimer =20 then: properties: --=20 2.43.0 From nobody Wed Jun 17 01:38:04 2026 Received: from s106b.cyber-folks.pl (s106b.cyber-folks.pl [195.78.66.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C07192DF717; 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Received: from user-188-33-36-99.play-internet.pl ([188.33.36.99] helo=localhost) by s106.cyber-folks.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wHlJR-0000000Ay8E-0x82; Tue, 28 Apr 2026 18:29:29 +0200 From: Michal Piekos Date: Tue, 28 Apr 2026 18:26:59 +0200 Subject: [PATCH v3 2/4] clocksource/drivers/sun5i: add D1 hstimer support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260428-h616-t113s-hstimer-v3-2-7e02178a93ee@mmpsystems.pl> References: <20260428-h616-t113s-hstimer-v3-0-7e02178a93ee@mmpsystems.pl> In-Reply-To: <20260428-h616-t113s-hstimer-v3-0-7e02178a93ee@mmpsystems.pl> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard Cc: Michal Piekos , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Andre Przywara X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777393718; l=6812; i=michal.piekos@mmpsystems.pl; s=20260301; h=from:subject:message-id; bh=1L3rHOJVuAnpxzydteKfdfNTRtbJkFSx+Yr9EHtcqh8=; b=zi0Ki2SpVY7XaTjmE9tVQjQqPcFQw2hU5vlPZJ0slaIW1d3YB08n16yFEgcpXIFp3Ivb1e0V8 B5gtqbzKuf6CX3DUdacsu3AJ3sfG8loq4voSrau2tZfWIn0pE7xE7ah X-Developer-Key: i=michal.piekos@mmpsystems.pl; a=ed25519; pk=Aixyx03If7ZDamiKKN0lsa+0mtA+WjIuIf2ZQVYNBqg= X-Authenticated-Id: michal.piekos@mmpsystems.pl D1 high speed timer differs from existing timer-sun5i by register base offset. Add sunxi quirks to handle D1 specific offset. Add D1 compatible string to OF match table. Signed-off-by: Michal Piekos Reviewed-by: Chen-Yu Tsai --- drivers/clocksource/timer-sun5i.c | 84 ++++++++++++++++++++++++++++++-----= ---- 1 file changed, 65 insertions(+), 19 deletions(-) diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-= sun5i.c index f827d3f98f60..517c048a4870 100644 --- a/drivers/clocksource/timer-sun5i.c +++ b/drivers/clocksource/timer-sun5i.c @@ -18,21 +18,30 @@ #include #include =20 -#define TIMER_IRQ_EN_REG 0x00 +#define TIMER_IRQ_EN_REG 0x00 #define TIMER_IRQ_EN(val) BIT(val) -#define TIMER_IRQ_ST_REG 0x04 -#define TIMER_CTL_REG(val) (0x20 * (val) + 0x10) +#define TIMER_IRQ_ST_REG 0x04 +#define TIMER_CTL_REG(val, offset) (0x20 * (val) + 0x10 + (offset)) #define TIMER_CTL_ENABLE BIT(0) #define TIMER_CTL_RELOAD BIT(1) #define TIMER_CTL_CLK_PRES(val) (((val) & 0x7) << 4) #define TIMER_CTL_ONESHOT BIT(7) -#define TIMER_INTVAL_LO_REG(val) (0x20 * (val) + 0x14) -#define TIMER_INTVAL_HI_REG(val) (0x20 * (val) + 0x18) -#define TIMER_CNTVAL_LO_REG(val) (0x20 * (val) + 0x1c) -#define TIMER_CNTVAL_HI_REG(val) (0x20 * (val) + 0x20) +#define TIMER_INTVAL_LO_REG(val, offset) (0x20 * (val) + 0x14 + (offset)) +#define TIMER_INTVAL_HI_REG(val, offset) (0x20 * (val) + 0x18 + (offset)) +#define TIMER_CNTVAL_LO_REG(val, offset) (0x20 * (val) + 0x1c + (offset)) +#define TIMER_CNTVAL_HI_REG(val, offset) (0x20 * (val) + 0x20 + (offset)) =20 #define TIMER_SYNC_TICKS 3 =20 +/** + * struct sunxi_timer_quirks - Differences between SoC variants. + * + * @from_ctl_base_offset: offset applied from ctl register onwards + */ +struct sunxi_timer_quirks { + u32 from_ctl_base_offset; +}; + struct sun5i_timer { void __iomem *base; struct clk *clk; @@ -40,6 +49,7 @@ struct sun5i_timer { u32 ticks_per_jiffy; struct clocksource clksrc; struct clock_event_device clkevt; + const struct sunxi_timer_quirks *quirks; }; =20 #define nb_to_sun5i_timer(x) \ @@ -57,28 +67,36 @@ struct sun5i_timer { */ static void sun5i_clkevt_sync(struct sun5i_timer *ce) { - u32 old =3D readl(ce->base + TIMER_CNTVAL_LO_REG(1)); + u32 offset =3D ce->quirks->from_ctl_base_offset; + u32 old =3D readl(ce->base + TIMER_CNTVAL_LO_REG(1, offset)); =20 - while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1))) < TIMER_SYNC_TICK= S) + while ((old - readl(ce->base + TIMER_CNTVAL_LO_REG(1, offset))) < + TIMER_SYNC_TICKS) cpu_relax(); } =20 static void sun5i_clkevt_time_stop(struct sun5i_timer *ce, u8 timer) { - u32 val =3D readl(ce->base + TIMER_CTL_REG(timer)); - writel(val & ~TIMER_CTL_ENABLE, ce->base + TIMER_CTL_REG(timer)); + u32 offset =3D ce->quirks->from_ctl_base_offset; + u32 val =3D readl(ce->base + TIMER_CTL_REG(timer, offset)); + + writel(val & ~TIMER_CTL_ENABLE, + ce->base + TIMER_CTL_REG(timer, offset)); =20 sun5i_clkevt_sync(ce); } =20 static void sun5i_clkevt_time_setup(struct sun5i_timer *ce, u8 timer, u32 = delay) { - writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer)); + u32 offset =3D ce->quirks->from_ctl_base_offset; + + writel(delay, ce->base + TIMER_INTVAL_LO_REG(timer, offset)); } =20 static void sun5i_clkevt_time_start(struct sun5i_timer *ce, u8 timer, bool= periodic) { - u32 val =3D readl(ce->base + TIMER_CTL_REG(timer)); + u32 offset =3D ce->quirks->from_ctl_base_offset; + u32 val =3D readl(ce->base + TIMER_CTL_REG(timer, offset)); =20 if (periodic) val &=3D ~TIMER_CTL_ONESHOT; @@ -86,7 +104,7 @@ static void sun5i_clkevt_time_start(struct sun5i_timer *= ce, u8 timer, bool perio val |=3D TIMER_CTL_ONESHOT; =20 writel(val | TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, - ce->base + TIMER_CTL_REG(timer)); + ce->base + TIMER_CTL_REG(timer, offset)); } =20 static int sun5i_clkevt_shutdown(struct clock_event_device *clkevt) @@ -141,8 +159,9 @@ static irqreturn_t sun5i_timer_interrupt(int irq, void = *dev_id) static u64 sun5i_clksrc_read(struct clocksource *clksrc) { struct sun5i_timer *cs =3D clksrc_to_sun5i_timer(clksrc); + u32 offset =3D cs->quirks->from_ctl_base_offset; =20 - return ~readl(cs->base + TIMER_CNTVAL_LO_REG(1)); + return ~readl(cs->base + TIMER_CNTVAL_LO_REG(1, offset)); } =20 static int sun5i_rate_cb(struct notifier_block *nb, @@ -173,12 +192,13 @@ static int sun5i_setup_clocksource(struct platform_de= vice *pdev, unsigned long rate) { struct sun5i_timer *cs =3D platform_get_drvdata(pdev); + u32 offset =3D cs->quirks->from_ctl_base_offset; void __iomem *base =3D cs->base; int ret; =20 - writel(~0, base + TIMER_INTVAL_LO_REG(1)); + writel(~0, base + TIMER_INTVAL_LO_REG(1, offset)); writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD, - base + TIMER_CTL_REG(1)); + base + TIMER_CTL_REG(1, offset)); =20 cs->clksrc.name =3D pdev->dev.of_node->name; cs->clksrc.rating =3D 340; @@ -237,6 +257,7 @@ static int sun5i_setup_clockevent(struct platform_devic= e *pdev, =20 static int sun5i_timer_probe(struct platform_device *pdev) { + const struct sunxi_timer_quirks *quirks; struct device *dev =3D &pdev->dev; struct sun5i_timer *st; struct reset_control *rstc; @@ -273,11 +294,18 @@ static int sun5i_timer_probe(struct platform_device *= pdev) return -EINVAL; } =20 + quirks =3D of_device_get_match_data(&pdev->dev); + if (!quirks) { + dev_err(&pdev->dev, "Failed to determine the quirks to use\n"); + return -ENODEV; + } + st->base =3D timer_base; st->ticks_per_jiffy =3D DIV_ROUND_UP(rate, HZ); st->clk =3D clk; st->clk_rate_cb.notifier_call =3D sun5i_rate_cb; st->clk_rate_cb.next =3D NULL; + st->quirks =3D quirks; =20 ret =3D devm_clk_notifier_register(dev, clk, &st->clk_rate_cb); if (ret) { @@ -311,9 +339,27 @@ static void sun5i_timer_remove(struct platform_device = *pdev) clocksource_unregister(&st->clksrc); } =20 +static const struct sunxi_timer_quirks sun5i_sun7i_hstimer_quirks =3D { + .from_ctl_base_offset =3D 0x0, +}; + +static const struct sunxi_timer_quirks sun20i_d1_hstimer_quirks =3D { + .from_ctl_base_offset =3D 0x10, +}; + static const struct of_device_id sun5i_timer_of_match[] =3D { - { .compatible =3D "allwinner,sun5i-a13-hstimer" }, - { .compatible =3D "allwinner,sun7i-a20-hstimer" }, + { + .compatible =3D "allwinner,sun5i-a13-hstimer", + .data =3D &sun5i_sun7i_hstimer_quirks, + }, + { + .compatible =3D "allwinner,sun7i-a20-hstimer", + .data =3D &sun5i_sun7i_hstimer_quirks, + }, + { + .compatible =3D "allwinner,sun20i-d1-hstimer", + .data =3D &sun20i_d1_hstimer_quirks, + }, {}, }; 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a=ed25519-sha256; t=1777393718; l=1131; i=michal.piekos@mmpsystems.pl; s=20260301; h=from:subject:message-id; bh=WB+FLCQ1pB6/hLLpL8qe5azyJH79mgJP5EWQCmjzLQg=; b=3GNyRfpjDbtcqK/LKJuzrzfNjknCnh257Oxx/AACPv/6jmBonzBlC/rUmweHPXkCCV2s9ovxW +RWr7slZII6AWiXogzBlFfjGAxODMDIGJnMukfzR5ZNI2rzhBaiw/26 X-Developer-Key: i=michal.piekos@mmpsystems.pl; a=ed25519; pk=Aixyx03If7ZDamiKKN0lsa+0mtA+WjIuIf2ZQVYNBqg= X-Authenticated-Id: michal.piekos@mmpsystems.pl Describe high speed timer block on Allwinner T113-S3. Tested on LCPI-PC-T113/F113: - hstimer is registered as clocksource - switching clocksource at runtime works - after rating increase hstimer operates as a broadcast clockevent device Signed-off-by: Michal Piekos Reviewed-by: Chen-Yu Tsai --- arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi b/arch/arm/boot/d= ts/allwinner/sun8i-t113s.dtsi index 424f4a2487e2..40e76cfc8a1d 100644 --- a/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi +++ b/arch/arm/boot/dts/allwinner/sun8i-t113s.dtsi @@ -34,6 +34,17 @@ cpu1: cpu@1 { }; }; =20 + soc { + hstimer@3008000 { + compatible =3D "allwinner,sun20i-d1-hstimer"; + reg =3D <0x03008000 0x1000>; + interrupts =3D , + ; + clocks =3D <&ccu CLK_BUS_HSTIMER>; + resets =3D <&ccu RST_BUS_HSTIMER>; + }; + }; + gic: interrupt-controller@1c81000 { compatible =3D "arm,gic-400"; reg =3D <0x03021000 0x1000>, --=20 2.43.0 From nobody Wed Jun 17 01:38:04 2026 Received: from s106b.cyber-folks.pl (s106b.cyber-folks.pl [195.78.66.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 17E442FFF81; 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Received: from user-188-33-36-99.play-internet.pl ([188.33.36.99] helo=localhost) by s106.cyber-folks.pl with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wHlJS-0000000AyAH-33fe; Tue, 28 Apr 2026 18:29:30 +0200 From: Michal Piekos Date: Tue, 28 Apr 2026 18:27:01 +0200 Subject: [PATCH v3 4/4] arm64: dts: allwinner: h616: add hstimer node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260428-h616-t113s-hstimer-v3-4-7e02178a93ee@mmpsystems.pl> References: <20260428-h616-t113s-hstimer-v3-0-7e02178a93ee@mmpsystems.pl> In-Reply-To: <20260428-h616-t113s-hstimer-v3-0-7e02178a93ee@mmpsystems.pl> To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard Cc: Michal Piekos , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Andre Przywara X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777393718; l=1212; i=michal.piekos@mmpsystems.pl; s=20260301; h=from:subject:message-id; bh=cCHCvUuPpHPu5/1mgf/ezZ1u0bRGr6TqCo7i9RhbRKk=; b=eFK3ao3uugOuv143hz0liRBNNc2Xesw0yOGSCckqUgPwCm5JUa2FLamO0kXHGhWPW9uAVb/3s 0sqvXLmq0WhBVS/BrEBPdbZ4YK6th3qxM4WgPB7NxXjKfqpDzkuhzZz X-Developer-Key: i=michal.piekos@mmpsystems.pl; a=ed25519; pk=Aixyx03If7ZDamiKKN0lsa+0mtA+WjIuIf2ZQVYNBqg= X-Authenticated-Id: michal.piekos@mmpsystems.pl Describe high speed timer block on Allwinner H616. Tested on Orange Pi Zero 3: - hstimer is registered as clocksource - switching clocksource at runtime works - after rating increase hstimer operates as a broadcast clockevent device Signed-off-by: Michal Piekos Reviewed-by: Chen-Yu Tsai --- arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun50i-h616.dtsi index bf054869e78b..1356e5df2562 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi @@ -237,6 +237,16 @@ timer0: timer@3009000 { clocks =3D <&osc24M>; }; =20 + hstimer@3005000 { + compatible =3D "allwinner,sun50i-h616-hstimer", + "allwinner,sun20i-d1-hstimer"; + reg =3D <0x03005000 0x1000>; + interrupts =3D , + ; + clocks =3D <&ccu CLK_BUS_HSTIMER>; + resets =3D <&ccu RST_BUS_HSTIMER>; + }; + watchdog: watchdog@30090a0 { compatible =3D "allwinner,sun50i-h616-wdt", "allwinner,sun6i-a31-wdt"; --=20 2.43.0