From nobody Wed Jun 17 06:18:36 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EBCC33A032; Mon, 27 Apr 2026 15:29:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777303798; cv=none; b=bzDLVBH8CfQK4NlTPYQ6PjhcmKQRjMkiVTXWaNDdxkKhxBFULB/4S3A5AEBZGmbu4VYCKJJvBU7Jr54d6ffcZS1BycJfk13E1Jvtnrb5HgIRoBhuQ1sem8WZzn6Q+siz4AG3bM2ir7DmCZmPnXCNmC3bFpZHpK1aJBXVUfaFxo0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777303798; c=relaxed/simple; bh=cMHGd1RCHKvDbkatFDIXhY5EIvv2vux4haon5GzPpJc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jvTjwaw+utk0jW/WR2kkJvMId/TOzhtH1wbz9goDj1CTKZAHt92vmkrEyWce1zqIBjmxwcBF+IhV91nBlyPRFQcYlnG5odtUiWkqK6Qa+0MmA2LWj+FVJ68J97FA3RLX+5x6DXNQO7qJTm8kMGA5FWlkaAfqPwhFRunern2zsoA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CzYX3Dlz; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CzYX3Dlz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777303797; x=1808839797; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cMHGd1RCHKvDbkatFDIXhY5EIvv2vux4haon5GzPpJc=; b=CzYX3DlzQX54YCitoAxHT8YfhQM5lfwLNH+zjRK3tGg7Db0IXfnkzjP9 XtoWg6AAJSQpZgal8GKl/BToxP5nOPyy5SH4ga/RNCxosnPYtmbCJnk4y 6vx3bLXwxgevmjeAetP5EOwHThhthILOi3kKs05Tw7t1ZJPL4aLAQ7SjB N7x/7jmSM1UOaRTmLh6lxVaJoEh2H8lftYWMsdIpn5N24nzttq8IbA/PK X9EP0Avemor3qRGj/fd+1KdBmhKY1snkWPQXSbrUzrXLdVqRuicL/py80 lbkAosQ7dE75ijl6pZYIJr632oK/6QrAICVCDTLQJwXQ2q9vgfOs2redw A==; X-CSE-ConnectionGUID: jbhbBkS3STaXYnmXNaae1Q== X-CSE-MsgGUID: HMVns4tHSa+eKpQOR1iatg== X-IronPort-AV: E=McAfee;i="6800,10657,11769"; a="77900636" X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="77900636" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:29:54 -0700 X-CSE-ConnectionGUID: JLaOaWknQKOFpD+pdzqHXg== X-CSE-MsgGUID: 2SDggNzgTXu1BPUjKoO80w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673194" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:29:53 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Zhenzhong Duan , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH v8 01/21] x86/virt/tdx: Move low level SEAMCALL helpers out of Date: Mon, 27 Apr 2026 08:27:55 -0700 Message-ID: <20260427152854.101171-2-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Kai Huang TDX host core code implements three seamcall*() helpers to make SEAMCALLs to the TDX module. Currently, they are implemented in and are exposed to other kernel code which includes . However, other than the TDX host core, seamcall*() are not expected to be used by other kernel code directly. For instance, for all SEAMCALLs that are used by KVM, the TDX host core exports a wrapper function for each of them. Move seamcall*() and related code out of and make them only visible to TDX host core. Since TDX host core tdx.c is already very heavy, don't put low level seamcall*() code there but to a new dedicated "seamcall_internal.h". Also, currently tdx.c has seamcall_prerr*() helpers which additionally print error message when calling seamcall*() fails. Move them to "seamcall_internal.h" as well. In such way all low level SEAMCALL helpers are in a dedicated place, which is much more readable. Copy the copyright notice from the original files and consolidate the date ranges to: Copyright (C) 2021-2023 Intel Corporation Signed-off-by: Kai Huang Signed-off-by: Chao Gao Reviewed-by: Zhenzhong Duan Reviewed-by: Binbin Wu Reviewed-by: Tony Lindgren Reviewed-by: Kiryl Shutsemau (Meta) Reviewed-by: Xiaoyao Li Acked-by: Dave Hansen Reviewed-by: Vishal Annapurve --- v8: - s/SEAMCALL/SEAMCALLs [Rick] --- arch/x86/include/asm/tdx.h | 47 ---------- arch/x86/virt/vmx/tdx/seamcall_internal.h | 109 ++++++++++++++++++++++ arch/x86/virt/vmx/tdx/tdx.c | 47 +--------- 3 files changed, 111 insertions(+), 92 deletions(-) create mode 100644 arch/x86/virt/vmx/tdx/seamcall_internal.h diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index a149740b24e8..31e01ab8b01a 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -97,54 +97,7 @@ static inline long tdx_kvm_hypercall(unsigned int nr, un= signed long p1, #endif /* CONFIG_INTEL_TDX_GUEST && CONFIG_KVM_GUEST */ =20 #ifdef CONFIG_INTEL_TDX_HOST -u64 __seamcall(u64 fn, struct tdx_module_args *args); -u64 __seamcall_ret(u64 fn, struct tdx_module_args *args); -u64 __seamcall_saved_ret(u64 fn, struct tdx_module_args *args); void tdx_init(void); - -#include -#include -#include - -typedef u64 (*sc_func_t)(u64 fn, struct tdx_module_args *args); - -static __always_inline u64 __seamcall_dirty_cache(sc_func_t func, u64 fn, - struct tdx_module_args *args) -{ - lockdep_assert_preemption_disabled(); - - /* - * SEAMCALLs are made to the TDX module and can generate dirty - * cachelines of TDX private memory. Mark cache state incoherent - * so that the cache can be flushed during kexec. - * - * This needs to be done before actually making the SEAMCALL, - * because kexec-ing CPU could send NMI to stop remote CPUs, - * in which case even disabling IRQ won't help here. - */ - this_cpu_write(cache_state_incoherent, true); - - return func(fn, args); -} - -static __always_inline u64 sc_retry(sc_func_t func, u64 fn, - struct tdx_module_args *args) -{ - int retry =3D RDRAND_RETRY_LOOPS; - u64 ret; - - do { - preempt_disable(); - ret =3D __seamcall_dirty_cache(func, fn, args); - preempt_enable(); - } while (ret =3D=3D TDX_RND_NO_ENTROPY && --retry); - - return ret; -} - -#define seamcall(_fn, _args) sc_retry(__seamcall, (_fn), (_args)) -#define seamcall_ret(_fn, _args) sc_retry(__seamcall_ret, (_fn), (_args)) -#define seamcall_saved_ret(_fn, _args) sc_retry(__seamcall_saved_ret, (_fn= ), (_args)) const char *tdx_dump_mce_info(struct mce *m); const struct tdx_sys_info *tdx_get_sysinfo(void); =20 diff --git a/arch/x86/virt/vmx/tdx/seamcall_internal.h b/arch/x86/virt/vmx/= tdx/seamcall_internal.h new file mode 100644 index 000000000000..be5f446467df --- /dev/null +++ b/arch/x86/virt/vmx/tdx/seamcall_internal.h @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * SEAMCALL utilities for TDX host-side operations. + * + * Provides convenient wrappers around SEAMCALL assembly with retry logic, + * error reporting and cache coherency tracking. + * + * Copyright (C) 2021-2023 Intel Corporation + */ + +#ifndef _X86_VIRT_SEAMCALL_INTERNAL_H +#define _X86_VIRT_SEAMCALL_INTERNAL_H + +#include +#include +#include +#include +#include + +u64 __seamcall(u64 fn, struct tdx_module_args *args); +u64 __seamcall_ret(u64 fn, struct tdx_module_args *args); +u64 __seamcall_saved_ret(u64 fn, struct tdx_module_args *args); + +typedef u64 (*sc_func_t)(u64 fn, struct tdx_module_args *args); + +static __always_inline u64 __seamcall_dirty_cache(sc_func_t func, u64 fn, + struct tdx_module_args *args) +{ + lockdep_assert_preemption_disabled(); + + /* + * SEAMCALLs are made to the TDX module and can generate dirty + * cachelines of TDX private memory. Mark cache state incoherent + * so that the cache can be flushed during kexec. + * + * This needs to be done before actually making the SEAMCALL, + * because kexec-ing CPU could send NMI to stop remote CPUs, + * in which case even disabling IRQ won't help here. + */ + this_cpu_write(cache_state_incoherent, true); + + return func(fn, args); +} + +static __always_inline u64 sc_retry(sc_func_t func, u64 fn, + struct tdx_module_args *args) +{ + int retry =3D RDRAND_RETRY_LOOPS; + u64 ret; + + do { + preempt_disable(); + ret =3D __seamcall_dirty_cache(func, fn, args); + preempt_enable(); + } while (ret =3D=3D TDX_RND_NO_ENTROPY && --retry); + + return ret; +} + +#define seamcall(_fn, _args) sc_retry(__seamcall, (_fn), (_args)) +#define seamcall_ret(_fn, _args) sc_retry(__seamcall_ret, (_fn), (_args)) +#define seamcall_saved_ret(_fn, _args) sc_retry(__seamcall_saved_ret, (_fn= ), (_args)) + +typedef void (*sc_err_func_t)(u64 fn, u64 err, struct tdx_module_args *arg= s); + +static inline void seamcall_err(u64 fn, u64 err, struct tdx_module_args *a= rgs) +{ + pr_err("SEAMCALL (0x%016llx) failed: 0x%016llx\n", fn, err); +} + +static inline void seamcall_err_ret(u64 fn, u64 err, + struct tdx_module_args *args) +{ + seamcall_err(fn, err, args); + pr_err("RCX 0x%016llx RDX 0x%016llx R08 0x%016llx\n", + args->rcx, args->rdx, args->r8); + pr_err("R09 0x%016llx R10 0x%016llx R11 0x%016llx\n", + args->r9, args->r10, args->r11); +} + +static __always_inline int sc_retry_prerr(sc_func_t func, + sc_err_func_t err_func, + u64 fn, struct tdx_module_args *args) +{ + u64 sret =3D sc_retry(func, fn, args); + + if (sret =3D=3D TDX_SUCCESS) + return 0; + + if (sret =3D=3D TDX_SEAMCALL_VMFAILINVALID) + return -ENODEV; + + if (sret =3D=3D TDX_SEAMCALL_GP) + return -EOPNOTSUPP; + + if (sret =3D=3D TDX_SEAMCALL_UD) + return -EACCES; + + err_func(fn, sret, args); + return -EIO; +} + +#define seamcall_prerr(__fn, __args) \ + sc_retry_prerr(__seamcall, seamcall_err, (__fn), (__args)) + +#define seamcall_prerr_ret(__fn, __args) \ + sc_retry_prerr(__seamcall_ret, seamcall_err_ret, (__fn), (__args)) + +#endif /* _X86_VIRT_SEAMCALL_INTERNAL_H */ diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index cb9b3210ab71..7fe4b9234c72 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -41,6 +41,8 @@ #include #include #include + +#include "seamcall_internal.h" #include "tdx.h" =20 static u32 tdx_global_keyid __ro_after_init; @@ -59,51 +61,6 @@ static LIST_HEAD(tdx_memlist); static struct tdx_sys_info tdx_sysinfo __ro_after_init; static bool tdx_module_initialized __ro_after_init; =20 -typedef void (*sc_err_func_t)(u64 fn, u64 err, struct tdx_module_args *arg= s); - -static inline void seamcall_err(u64 fn, u64 err, struct tdx_module_args *a= rgs) -{ - pr_err("SEAMCALL (0x%016llx) failed: 0x%016llx\n", fn, err); -} - -static inline void seamcall_err_ret(u64 fn, u64 err, - struct tdx_module_args *args) -{ - seamcall_err(fn, err, args); - pr_err("RCX 0x%016llx RDX 0x%016llx R08 0x%016llx\n", - args->rcx, args->rdx, args->r8); - pr_err("R09 0x%016llx R10 0x%016llx R11 0x%016llx\n", - args->r9, args->r10, args->r11); -} - -static __always_inline int sc_retry_prerr(sc_func_t func, - sc_err_func_t err_func, - u64 fn, struct tdx_module_args *args) -{ - u64 sret =3D sc_retry(func, fn, args); - - if (sret =3D=3D TDX_SUCCESS) - return 0; - - if (sret =3D=3D TDX_SEAMCALL_VMFAILINVALID) - return -ENODEV; - - if (sret =3D=3D TDX_SEAMCALL_GP) - return -EOPNOTSUPP; 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d="scan'208";a="232673205" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:29:55 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Dan Williams , Jonathan Cameron , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH v8 02/21] coco/tdx-host: Introduce a "tdx_host" device Date: Mon, 27 Apr 2026 08:27:56 -0700 Message-ID: <20260427152854.101171-3-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TDX depends on a platform firmware module that is invoked via instructions similar to vmenter (i.e. enter into a new privileged "root-mode" context to manage private memory and private device mechanisms). It is a software construct that depends on the CPU vmxon state to enable invocation of TDX module ABIs. Unlike other Trusted Execution Environment (TEE) platform implementations that employ a firmware module running on a PCI device with an MMIO mailbox for communication, TDX has no hardware device to point to as the TEE Secure Manager (TSM). Create a virtual device not only to align with other implementations but also to make it easier to - expose metadata (e.g., TDX module version, seamldr version etc) to the userspace as device attributes - implement firmware uploader APIs which are tied to a device. This is needed to support TDX module runtime updates - enable TDX Connect which will share a common infrastructure with other platform implementations. In the TDX Connect context, every architecture has a TSM, represented by a PCIe or virtual device. The new "tdx_host" device will serve the TSM role. A faux device is used for TDX because the TDX module is singular within the system and lacks associated platform resources. Using a faux device eliminates the need to create a stub bus. The call to tdx_get_sysinfo() ensures that the TDX module is ready to provide services. Note that AMD has a PCI device for the PSP for SEV and ARM CCA will likely have a faux device [1]. Co-developed-by: Xu Yilun Signed-off-by: Xu Yilun Signed-off-by: Dan Williams Signed-off-by: Chao Gao Reviewed-by: Jonathan Cameron Reviewed-by: Tony Lindgren Reviewed-by: Xu Yilun Reviewed-by: Kai Huang Reviewed-by: Kiryl Shutsemau (Meta) Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/all/2025073035-bulginess-rematch-b92e@gregkh/= # [1] --- arch/x86/virt/vmx/tdx/tdx.c | 2 +- drivers/virt/coco/Kconfig | 2 ++ drivers/virt/coco/Makefile | 1 + drivers/virt/coco/tdx-host/Kconfig | 10 +++++++ drivers/virt/coco/tdx-host/Makefile | 1 + drivers/virt/coco/tdx-host/tdx-host.c | 43 +++++++++++++++++++++++++++ 6 files changed, 58 insertions(+), 1 deletion(-) create mode 100644 drivers/virt/coco/tdx-host/Kconfig create mode 100644 drivers/virt/coco/tdx-host/Makefile create mode 100644 drivers/virt/coco/tdx-host/tdx-host.c diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 7fe4b9234c72..05d241626e48 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -1487,7 +1487,7 @@ const struct tdx_sys_info *tdx_get_sysinfo(void) =20 return (const struct tdx_sys_info *)&tdx_sysinfo; } -EXPORT_SYMBOL_FOR_KVM(tdx_get_sysinfo); +EXPORT_SYMBOL_FOR_MODULES(tdx_get_sysinfo, "kvm-intel,tdx-host"); =20 u32 tdx_get_nr_guest_keyids(void) { diff --git a/drivers/virt/coco/Kconfig b/drivers/virt/coco/Kconfig index df1cfaf26c65..f7691f64fbe3 100644 --- a/drivers/virt/coco/Kconfig +++ b/drivers/virt/coco/Kconfig @@ -17,5 +17,7 @@ source "drivers/virt/coco/arm-cca-guest/Kconfig" source "drivers/virt/coco/guest/Kconfig" endif =20 +source "drivers/virt/coco/tdx-host/Kconfig" + config TSM bool diff --git a/drivers/virt/coco/Makefile b/drivers/virt/coco/Makefile index cb52021912b3..b323b0ae4f82 100644 --- a/drivers/virt/coco/Makefile +++ b/drivers/virt/coco/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_EFI_SECRET) +=3D efi_secret/ obj-$(CONFIG_ARM_PKVM_GUEST) +=3D pkvm-guest/ obj-$(CONFIG_SEV_GUEST) +=3D sev-guest/ obj-$(CONFIG_INTEL_TDX_GUEST) +=3D tdx-guest/ +obj-$(CONFIG_INTEL_TDX_HOST) +=3D tdx-host/ obj-$(CONFIG_ARM_CCA_GUEST) +=3D arm-cca-guest/ obj-$(CONFIG_TSM) +=3D tsm-core.o obj-$(CONFIG_TSM_GUEST) +=3D guest/ diff --git a/drivers/virt/coco/tdx-host/Kconfig b/drivers/virt/coco/tdx-hos= t/Kconfig new file mode 100644 index 000000000000..d35d85ef91c0 --- /dev/null +++ b/drivers/virt/coco/tdx-host/Kconfig @@ -0,0 +1,10 @@ +config TDX_HOST_SERVICES + tristate "TDX Host Services Driver" + depends on INTEL_TDX_HOST + default m + help + Enable access to TDX host services like module update and + extensions (e.g. TDX Connect). + + Say y or m if enabling support for confidential virtual machine + support (CONFIG_INTEL_TDX_HOST). The module is called tdx_host.ko. diff --git a/drivers/virt/coco/tdx-host/Makefile b/drivers/virt/coco/tdx-ho= st/Makefile new file mode 100644 index 000000000000..e61e749a8dff --- /dev/null +++ b/drivers/virt/coco/tdx-host/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_TDX_HOST_SERVICES) +=3D tdx-host.o diff --git a/drivers/virt/coco/tdx-host/tdx-host.c b/drivers/virt/coco/tdx-= host/tdx-host.c new file mode 100644 index 000000000000..c77885392b09 --- /dev/null +++ b/drivers/virt/coco/tdx-host/tdx-host.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * TDX host user interface driver + * + * Copyright (C) 2025 Intel Corporation + */ + +#include +#include +#include + +#include +#include + +static const struct x86_cpu_id tdx_host_ids[] =3D { + X86_MATCH_FEATURE(X86_FEATURE_TDX_HOST_PLATFORM, NULL), + {} +}; +MODULE_DEVICE_TABLE(x86cpu, tdx_host_ids); + +static struct faux_device *fdev; + +static int __init tdx_host_init(void) +{ + if (!x86_match_cpu(tdx_host_ids) || !tdx_get_sysinfo()) + return -ENODEV; + + fdev =3D faux_device_create(KBUILD_MODNAME, NULL, NULL); + if (!fdev) + return -ENODEV; + + return 0; +} +module_init(tdx_host_init); + +static void __exit tdx_host_exit(void) +{ + faux_device_destroy(fdev); +} +module_exit(tdx_host_exit); + +MODULE_DESCRIPTION("TDX Host Services"); +MODULE_LICENSE("GPL"); --=20 2.47.1 From nobody Wed Jun 17 06:18:36 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA9DA340A43; Mon, 27 Apr 2026 15:29:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777303801; cv=none; b=lQB+GAnJHbSLdwyyR6/qb+Yn/rrcH0IKYxS2GvIDphSZrgnTXKj0HUc27kdLC/fRKVauGrhnej0++qviAtQVuRZ5WBxeeWy/uRvCm+FOF27g7LBoIxcC9uVpFYABwiYUnxr3G7adJXp1acZrhAlTAU7TnqUE/iXikrum7mtu320= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777303801; c=relaxed/simple; bh=mJL0HrIfYigm26+ukOV7zKxecKipW8/aS1AqLP6VJuQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YdcTTQfcHXpWckIAoU9BBQ2yjMr67t0rXFhA5DfkUzTcgGFYMijnBlaJuB+fnEAtRYN1jqpVEbKN0gkY56NNEpmkPzrYY2lK2rKJ2evqXcwKe6hDC7MpMHf1bgN1ExffH41VpJYXmlRXQQkgpW1PguQq6e03d3xy95+pIUidwIc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=B7EmIbjE; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="B7EmIbjE" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777303799; x=1808839799; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mJL0HrIfYigm26+ukOV7zKxecKipW8/aS1AqLP6VJuQ=; b=B7EmIbjEBDtWg2wmY532+HDKjgyV4mp0l/84EdJ3It0IQqOQOMZQBo62 V4dJCS1afRx12BoeOIMaC1pDt8XV02yNYRI7MU1Ysd/I2qeJJmsEnX8MN f4+Bgf/iqYoywZp81SXWdRLnfZ6NRPRgwE7v+RswatJnfWPeaKoDweRtr 1mHF4ZQj/T9QPzGkSG2hHu2tCalauNxmTKZmUNGYlcCSEAI3Clhy4mrqU PnUy90VRSXZatE/CnAeOqeWiFI7TA3cjfofLjd1pLjm4cB4o4OZvSahxv mSsu/kMzFss6tGXkFbN6btZ2Sqp18SnIFpEdjJTP2DNGLwsrAT0qdViZX g==; X-CSE-ConnectionGUID: 6E9+szlERDu4g98vTgKY/g== X-CSE-MsgGUID: n5Vkaud2Qra1GiehYcDx8w== X-IronPort-AV: E=McAfee;i="6800,10657,11769"; a="77900658" X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="77900658" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:29:56 -0700 X-CSE-ConnectionGUID: kexiZTIIRqON3I6ncLXKqw== X-CSE-MsgGUID: jtZouHpESvq5pMVILj2m5Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673216" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:29:56 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH v8 03/21] coco/tdx-host: Expose TDX module version Date: Mon, 27 Apr 2026 08:27:57 -0700 Message-ID: <20260427152854.101171-4-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For TDX module updates, userspace needs to select compatible update versions based on the current module version. This design delegates module selection complexity to userspace because TDX module update policies are complex and version series are platform-specific. For example, the 1.5.x series is for certain platform generations, while the 2.0.x series is intended for others. And TDX module 1.5.x may be updated to 1.5.y but not to 1.5.y+1. Expose the TDX module version to userspace via sysfs to aid module selection. Since the TDX faux device will drive module updates, expose the version as its attribute. One bonus of exposing TDX module version via sysfs is: TDX module version information remains available even after dmesg logs are cleared. Define TDX_VERSION_FMT macro for the TDX version format since it will be used multiple times. Also convert an existing print statement to use it. =3D=3D Background =3D=3D The "faux device + device attribute" approach compares to other update mechanisms as follows: 1. AMD SEV leverages an existing PCI device for the PSP to expose metadata. TDX uses a faux device as it doesn't have PCI device in its architecture. 2. Microcode uses per-CPU virtual devices to report microcode revisions because CPUs can have different revisions. But, there is only a single TDX module, so exposing the TDX module version through a global TDX faux device is appropriate 3. ARM's CCA implementation isn't in-tree yet, but will likely follow a similar faux device approach, though it's unclear whether they need to expose firmware version information Signed-off-by: Chao Gao Reviewed-by: Binbin Wu Reviewed-by: Tony Lindgren Reviewed-by: Xu Yilun Reviewed-by: Kai Huang Reviewed-by: Kiryl Shutsemau (Meta) Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/all/2025073035-bulginess-rematch-b92e@gregkh/= # [1] --- .../ABI/testing/sysfs-devices-faux-tdx-host | 6 +++++ arch/x86/include/asm/tdx.h | 6 +++++ arch/x86/virt/vmx/tdx/tdx_global_metadata.c | 2 +- drivers/virt/coco/tdx-host/tdx-host.c | 26 ++++++++++++++++++- 4 files changed, 38 insertions(+), 2 deletions(-) create mode 100644 Documentation/ABI/testing/sysfs-devices-faux-tdx-host diff --git a/Documentation/ABI/testing/sysfs-devices-faux-tdx-host b/Docume= ntation/ABI/testing/sysfs-devices-faux-tdx-host new file mode 100644 index 000000000000..2cf682b65acf --- /dev/null +++ b/Documentation/ABI/testing/sysfs-devices-faux-tdx-host @@ -0,0 +1,6 @@ +What: /sys/devices/faux/tdx_host/version +Contact: linux-coco@lists.linux.dev +Description: (RO) Report the version of the loaded TDX module. The TDX mod= ule + version is formatted as x.y.z, where "x" is the major version, + "y" is the minor version and "z" is the update version. Versions + are used for bug reporting, TDX module updates etc. diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index 31e01ab8b01a..2afa8dde72e0 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -38,6 +38,12 @@ #include #include =20 +/* + * TDX module and P-SEAMLDR version convention: "major.minor.update" + * (e.g., "1.5.08") with zero-padded two-digit update field. + */ +#define TDX_VERSION_FMT "%u.%u.%02u" + /* * Used by the #VE exception handler to gather the #VE exception * info from the TDX module. This is a software only structure diff --git a/arch/x86/virt/vmx/tdx/tdx_global_metadata.c b/arch/x86/virt/vm= x/tdx/tdx_global_metadata.c index c7db393a9cfb..d54d4227990c 100644 --- a/arch/x86/virt/vmx/tdx/tdx_global_metadata.c +++ b/arch/x86/virt/vmx/tdx/tdx_global_metadata.c @@ -106,7 +106,7 @@ static __init int get_tdx_sys_info(struct tdx_sys_info = *sysinfo) =20 ret =3D ret ?: get_tdx_sys_info_version(&sysinfo->version); =20 - pr_info("Module version: %u.%u.%02u\n", + pr_info("Module version: " TDX_VERSION_FMT "\n", sysinfo->version.major_version, sysinfo->version.minor_version, sysinfo->version.update_version); diff --git a/drivers/virt/coco/tdx-host/tdx-host.c b/drivers/virt/coco/tdx-= host/tdx-host.c index c77885392b09..ef117a836b3a 100644 --- a/drivers/virt/coco/tdx-host/tdx-host.c +++ b/drivers/virt/coco/tdx-host/tdx-host.c @@ -8,6 +8,7 @@ #include #include #include +#include =20 #include #include @@ -18,6 +19,29 @@ static const struct x86_cpu_id tdx_host_ids[] =3D { }; MODULE_DEVICE_TABLE(x86cpu, tdx_host_ids); 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a="77900666" X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="77900666" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:29:56 -0700 X-CSE-ConnectionGUID: jsxvCs41Q8WM8isQeMyi0Q== X-CSE-MsgGUID: Xeg4itTHSLWXtfYHrPPPMQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673221" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:29:56 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org, linux-rt-devel@lists.linux.dev Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt Subject: [PATCH v8 04/21] x86/virt/seamldr: Introduce a wrapper for P-SEAMLDR SEAMCALLs Date: Mon, 27 Apr 2026 08:27:58 -0700 Message-ID: <20260427152854.101171-5-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The TDX architecture uses the "SEAMCALL" instruction to communicate with SEAM mode software. Right now, the only SEAM mode software that the kernel communicates with is the TDX module. But, there is actually another component that runs in SEAM mode but it is separate from the TDX module: the persistent SEAM loader or "P-SEAMLDR". Right now, the only component that communicates with it is the BIOS which loads the TDX module itself at boot. But, to support updating the TDX module, the kernel now needs to be able to talk to it. P-SEAMLDR SEAMCALLs differ from TDX module SEAMCALLs in areas such as concurrency requirements. Add a P-SEAMLDR wrapper to handle these differences and prepare for implementing concrete functions. Use seamcall_prerr() (not '_ret') because current P-SEAMLDR calls do not use any output registers other than RAX. Note that unlike P-SEAMLDR, there is also a non-persistent SEAM loader ("NP-SEAMLDR"). This is an authenticated code module (ACM) that is not callable at runtime. Only BIOS launches it to load P-SEAMLDR at boot; the kernel does not need to interact with it for runtime update. Signed-off-by: Chao Gao Reviewed-by: Binbin Wu Reviewed-by: Kai Huang Reviewed-by: Kiryl Shutsemau (Meta) Reviewed-by: Xiaoyao Li Reviewed-by: Rick Edgecombe Link: https://cdrdv2.intel.com/v1/dl/getContent/733582 # [1] --- arch/x86/virt/vmx/tdx/Makefile | 2 +- arch/x86/virt/vmx/tdx/seamldr.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 arch/x86/virt/vmx/tdx/seamldr.c diff --git a/arch/x86/virt/vmx/tdx/Makefile b/arch/x86/virt/vmx/tdx/Makefile index 90da47eb85ee..d1dbc5cc5697 100644 --- a/arch/x86/virt/vmx/tdx/Makefile +++ b/arch/x86/virt/vmx/tdx/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y +=3D seamcall.o tdx.o +obj-y +=3D seamcall.o seamldr.o tdx.o diff --git a/arch/x86/virt/vmx/tdx/seamldr.c b/arch/x86/virt/vmx/tdx/seamld= r.c new file mode 100644 index 000000000000..65616dd2f4d2 --- /dev/null +++ b/arch/x86/virt/vmx/tdx/seamldr.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * P-SEAMLDR support for TDX module management features like runtime updat= es + * + * Copyright (C) 2025 Intel Corporation + */ +#define pr_fmt(fmt) "seamldr: " fmt + +#include + +#include "seamcall_internal.h" + +/* + * Serialize P-SEAMLDR calls since the hardware only allows a single CPU to + * interact with P-SEAMLDR simultaneously. Use raw version as the calls can + * be made with interrupts disabled, where plain spinlocks are prohibited = in + * PREEMPT_RT kernels as they become sleeping locks. + */ +static DEFINE_RAW_SPINLOCK(seamldr_lock); + +static __maybe_unused int seamldr_call(u64 fn, struct tdx_module_args *arg= s) +{ + guard(raw_spinlock)(&seamldr_lock); + return seamcall_prerr(fn, args); +} --=20 2.47.1 From nobody Wed Jun 17 06:18:36 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14BB2342177; Mon, 27 Apr 2026 15:30:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777303802; cv=none; b=N2KiEdM137gwUEVX703AKXPOs6HcTbDTTpsHXPxIdM7QrKMF3T9hNOGcYEarcaDI13o+63iAbfR339j9ifjZvxKZmEvl2HAGiPfontwg8071xJ90jLqHBNVFxYWyuAor6j2ioMoCaapnTy7M9kfXXt/VPJN5L0Km5SBbKo8aRFg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777303802; c=relaxed/simple; bh=7jJ7eblQ5a5Un2crtpNxhvp6+2PVrme2ig2h67JHyH4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=d1/EYmrgqT53J3qKy6SwTM08wMH0H4cYfI1a9IqA5KnKADLHhaxjntHHKpAWGozMgl7t2WYsdhg0Ro4eFSIu1I7lAE5rJlmI5VDgGMgUOFD9JUE/Jpw4b8Mnis+GXYeoWlIo65HLBbU178+eENY2mTCAGwfiyC0HHcdewB6zZKo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=bAJ8R1rP; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="bAJ8R1rP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777303800; x=1808839800; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7jJ7eblQ5a5Un2crtpNxhvp6+2PVrme2ig2h67JHyH4=; b=bAJ8R1rPwZl6Mi6am2dAgx3O+ddA9DbHvqWV6el+dIkVqIzjlYMgcUY4 Dm17bVZEYSfa1/d+kRDIbcicwMRTm6so91dI9d1c8Iy41WG5i87AY76nn EbPLNIJKLcuX0ZyszrtPi59/DQXuIGBhkM+fxDUywOUr1FtJBGA4A0xsF 8UK5QKslr+aRLCNdtgYO9I4JD2xY0xEJtHzkvqNgSsKQu7jflcMtdkBOJ cUpkJBrBE+uzBDjq97upDLbdRRmaJCE2hy1z7VhsaKI9TLJOXaOF5rg8U PSMAYEsJb/jDp+H/GoKHOw8X6vWC3i2BdVGFypJCkjVkDm0zAxLdz6ClW Q==; X-CSE-ConnectionGUID: aXM5UN6aRNOgrHtg8wPlhw== X-CSE-MsgGUID: CkQvhOdXRYyiq/8ReIJ7Ig== X-IronPort-AV: E=McAfee;i="6800,10657,11769"; a="77900678" X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="77900678" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:29:57 -0700 X-CSE-ConnectionGUID: JA9RVQmKSkG+1Qc82mzNdQ== X-CSE-MsgGUID: 5KJncBUWRwC/9oNpjMI1hw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673227" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:29:57 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH v8 05/21] x86/virt/seamldr: Add a helper to retrieve P-SEAMLDR information Date: Mon, 27 Apr 2026 08:27:59 -0700 Message-ID: <20260427152854.101171-6-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable P-SEAMLDR reports its state via SEAMLDR.INFO, including its version and the number of remaining runtime updates. This information is useful for userspace. For example, the admin can use the P-SEAMLDR version to determine whether a candidate TDX module is compatible with the running loader, and can use the remaining update count to determine whether another runtime update is still possible. Add a helper to retrieve P-SEAMLDR information in preparation for exposing P-SEAMLDR version and other necessary information to userspace. Export the new kAPI for use by tdx-host.ko. Note that there are two distinct P-SEAMLDR APIs with similar names: SEAMLDR.INFO: Returns a SEAMLDR_INFO structure containing SEAMLDR information such as version and remaining updates. SEAMLDR.SEAMINFO: Returns a SEAMLDR_SEAMINFO structure containing SEAM and system information such as Convertible Memory Regions (CMRs) and number of CPUs and sockets. The former is used here. For details, see "Intel=C2=AE Trust Domain Extensions - SEAM Loader (SEAMLD= R) Interface Specification". Signed-off-by: Chao Gao Reviewed-by: Kai Huang Reviewed-by: Kiryl Shutsemau (Meta) Reviewed-by: Xiaoyao Li Reviewed-by: Rick Edgecombe --- arch/x86/include/asm/seamldr.h | 36 +++++++++++++++++++++++++++++++++ arch/x86/virt/vmx/tdx/seamldr.c | 20 +++++++++++++++++- 2 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 arch/x86/include/asm/seamldr.h diff --git a/arch/x86/include/asm/seamldr.h b/arch/x86/include/asm/seamldr.h new file mode 100644 index 000000000000..c67e5bc910a9 --- /dev/null +++ b/arch/x86/include/asm/seamldr.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_X86_SEAMLDR_H +#define _ASM_X86_SEAMLDR_H + +#include + +/* + * This is called the "SEAMLDR_INFO" data structure and is defined + * in "SEAM Loader (SEAMLDR) Interface Specification". + * + * The SEAMLDR.INFO documentation requires this to be aligned to a + * 256-byte boundary. + */ +struct seamldr_info { + u32 version; + u32 attributes; + u32 vendor_id; + u32 build_date; + u16 build_num; + u16 minor_version; + u16 major_version; + u16 update_version; + u32 acm_x2apicid; + u32 num_remaining_updates; + u8 seam_info[128]; + u8 seam_ready; + u8 seam_debug; + u8 p_seam_ready; + u8 reserved[93]; +} __packed __aligned(256); + +static_assert(sizeof(struct seamldr_info) =3D=3D 256); + +int seamldr_get_info(struct seamldr_info *seamldr_info); + +#endif /* _ASM_X86_SEAMLDR_H */ diff --git a/arch/x86/virt/vmx/tdx/seamldr.c b/arch/x86/virt/vmx/tdx/seamld= r.c index 65616dd2f4d2..7269a239bc22 100644 --- a/arch/x86/virt/vmx/tdx/seamldr.c +++ b/arch/x86/virt/vmx/tdx/seamldr.c @@ -8,8 +8,13 @@ =20 #include =20 +#include + #include "seamcall_internal.h" =20 +/* P-SEAMLDR SEAMCALL leaf function */ +#define P_SEAMLDR_INFO 0x8000000000000000 + /* * Serialize P-SEAMLDR calls since the hardware only allows a single CPU to * interact with P-SEAMLDR simultaneously. Use raw version as the calls can @@ -18,8 +23,21 @@ */ static DEFINE_RAW_SPINLOCK(seamldr_lock); =20 -static __maybe_unused int seamldr_call(u64 fn, struct tdx_module_args *arg= s) +static int seamldr_call(u64 fn, struct tdx_module_args *args) { guard(raw_spinlock)(&seamldr_lock); return seamcall_prerr(fn, args); } + +int seamldr_get_info(struct seamldr_info *seamldr_info) +{ + struct tdx_module_args args =3D {}; + + /* + * Use slow_virt_to_phys() since @seamldr_info may be allocated on + * the stack. + */ + args.rcx =3D slow_virt_to_phys(seamldr_info); + return seamldr_call(P_SEAMLDR_INFO, &args); +} +EXPORT_SYMBOL_FOR_MODULES(seamldr_get_info, "tdx-host"); --=20 2.47.1 From nobody Wed Jun 17 06:18:36 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6882C345CC0; Mon, 27 Apr 2026 15:30:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777303804; cv=none; b=gOu/EzQQL9drOn7GLe4Hjp8/uTVk6nYhX+PpHy1ZPCfbH3vMFAf0Bm+5WK5E9Ciyc5YkT+ADkxWU30/+McDwUNY6pf+VHZzF6BDknNawBwpPrKXCOv316z54f/wVMuLwxQg/u8Uv7y8LW1kysEaus/V5vHgQyz2KvhfB30pq82s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777303804; c=relaxed/simple; bh=Gwa1uyokNnXKuFhBVIEC2hgq4rbiGARvt36W+dszJRw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=MW7dgH7fy5h+lCDbtEQbr0qKvPmnGqb7pZLOprB6GN9jtmrBpqFFRgCoKqhpxuKbWCtd6CxnqPyo1TVEJTTm8q0MyaKLz5WVFyvpsh9m6QschuDIH2U7sfa2Wxl7FGGS4PqT5UQwBfrO3VoqPsNf560MQgrfdLuRi8bpOuO2ko8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=abQg33+a; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="abQg33+a" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777303802; x=1808839802; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Gwa1uyokNnXKuFhBVIEC2hgq4rbiGARvt36W+dszJRw=; b=abQg33+aNZfmRkEEdScsGO81BcHRdCdduxf8nTR3j/KnzcdYcjr1ML7u lPTw63J77n4c3ugh4ZB6iBb5CTHFf/dA1kpMcmFSVEyzgacgvN/hLfk50 DVyxz/sVfEZKZNji9IqiY4goZyiqPDVek2/ZoY0U7pMHAPat1ysCrxmeS IzAoaLh17U8F8MwLEaSKGzKd+AgrXnz0VzLqe2wS1HQ3fPVwvcAQXgNV1 jyly7U6cPd6XzkT6s8u+R8VXt3/kXvq/cozKwYAKc7rElelmPVaVJJK9q n/t5ZmT4OgAc9HGKvJwNpRAg125SW22AW+00+uoGhZU3hlfCGN8AB3ZtJ Q==; X-CSE-ConnectionGUID: bCMyy5j+QayWatdOKx5IJg== X-CSE-MsgGUID: BjcyRbHCTWuInmkyzFSZEg== X-IronPort-AV: E=McAfee;i="6800,10657,11769"; a="77900687" X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="77900687" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:29:58 -0700 X-CSE-ConnectionGUID: DEGylgPtRbGMI5SZoB5Yaw== X-CSE-MsgGUID: SMGQ9gHNTm+QUC66+DErrQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673231" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:29:58 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH v8 06/21] coco/tdx-host: Expose P-SEAMLDR information via sysfs Date: Mon, 27 Apr 2026 08:28:00 -0700 Message-ID: <20260427152854.101171-7-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable TDX module updates require userspace to select the appropriate module to load. Expose necessary information to facilitate this decision. Two values are needed: - P-SEAMLDR version: for compatibility checks between TDX module and P-SEAMLDR - num_remaining_updates: indicates how many updates can be performed Expose them as tdx-host device attributes. Make seamldr attributes visible only when the update feature is supported, as that's their sole purpose. Note that the underlying P-SEAMLDR attributes are available regardless of update support; this only restricts their visibility in Linux. Signed-off-by: Chao Gao Reviewed-by: Kiryl Shutsemau (Meta) --- v8: - explain when the two attributes are available and how they relate to TDX module update support [Rick] - drop erratum stuff [Rick, Dave] - drop the separate directory for p-seamldr attributes [Dave] - s/SEAM loader/P-SEAMLDR - don't use DEFINE_SIMPLE_SYSFS_GROUP_VISIBLE() as it doesn't work on an unnamed group. --- .../ABI/testing/sysfs-devices-faux-tdx-host | 22 +++++++ arch/x86/include/asm/tdx.h | 6 ++ drivers/virt/coco/tdx-host/tdx-host.c | 65 ++++++++++++++++++- 3 files changed, 92 insertions(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-devices-faux-tdx-host b/Docume= ntation/ABI/testing/sysfs-devices-faux-tdx-host index 2cf682b65acf..65897fe6abc0 100644 --- a/Documentation/ABI/testing/sysfs-devices-faux-tdx-host +++ b/Documentation/ABI/testing/sysfs-devices-faux-tdx-host @@ -4,3 +4,25 @@ Description: (RO) Report the version of the loaded TDX mod= ule. The TDX module version is formatted as x.y.z, where "x" is the major version, "y" is the minor version and "z" is the update version. Versions are used for bug reporting, TDX module updates etc. + +What: /sys/devices/faux/tdx_host/seamldr_version +Contact: linux-coco@lists.linux.dev +Description: (RO) Report the version of the loaded P-SEAMLDR. The P-SEAMLDR + version is formatted as x.y.z, where "x" is the major version, + "y" is the minor version and "z" is the update version. Versions + are used for bug reporting and compatibility checks. + +What: /sys/devices/faux/tdx_host/num_remaining_updates +Contact: linux-coco@lists.linux.dev +Description: (RO) Report the number of remaining updates. TDX maintains a + log about each TDX module that has been loaded. This log has + a finite size, which limits the number of TDX module updates + that can be performed. + + After each successful update, the number reduces by one. Once it + reaches zero, further updates will fail until next reboot. The + number is always zero if the P-SEAMLDR doesn't support updates. + + See Intel=C2=AE Trust Domain Extensions - SEAM Loader (SEAMLDR) + Interface Specification, Chapter "SEAMLDR_INFO" and Chapter + "SEAMLDR.INSTALL" for more information. diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index 2afa8dde72e0..1c5981453ff8 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -107,6 +107,12 @@ void tdx_init(void); const char *tdx_dump_mce_info(struct mce *m); const struct tdx_sys_info *tdx_get_sysinfo(void); =20 +static inline bool tdx_supports_runtime_update(const struct tdx_sys_info *= sysinfo) +{ + /* To be enabled when kernel is ready. */ + return false; +} + int tdx_guest_keyid_alloc(void); u32 tdx_get_nr_guest_keyids(void); void tdx_guest_keyid_free(unsigned int keyid); diff --git a/drivers/virt/coco/tdx-host/tdx-host.c b/drivers/virt/coco/tdx-= host/tdx-host.c index ef117a836b3a..079913dcc888 100644 --- a/drivers/virt/coco/tdx-host/tdx-host.c +++ b/drivers/virt/coco/tdx-host/tdx-host.c @@ -11,6 +11,7 @@ #include =20 #include +#include #include =20 static const struct x86_cpu_id tdx_host_ids[] =3D { @@ -40,7 +41,69 @@ static struct attribute *tdx_host_attrs[] =3D { &dev_attr_version.attr, NULL, }; -ATTRIBUTE_GROUPS(tdx_host); + +static const struct attribute_group tdx_host_group =3D { + .attrs =3D tdx_host_attrs, +}; + +static ssize_t seamldr_version_show(struct device *dev, struct device_attr= ibute *attr, + char *buf) +{ + struct seamldr_info info; + int ret; + + ret =3D seamldr_get_info(&info); + if (ret) + return ret; + + return sysfs_emit(buf, TDX_VERSION_FMT "\n", info.major_version, + info.minor_version, + info.update_version); +} + +static ssize_t num_remaining_updates_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct seamldr_info info; + int ret; + + ret =3D seamldr_get_info(&info); + if (ret) + return ret; + + return sysfs_emit(buf, "%u\n", info.num_remaining_updates); +} + +static DEVICE_ATTR_ADMIN_RO(seamldr_version); +static DEVICE_ATTR_ADMIN_RO(num_remaining_updates); + +static struct attribute *seamldr_attrs[] =3D { + &dev_attr_seamldr_version.attr, + &dev_attr_num_remaining_updates.attr, + NULL, +}; + +static umode_t seamldr_group_visible(struct kobject *kobj, struct attribut= e *attr, int idx) +{ + const struct tdx_sys_info *sysinfo =3D tdx_get_sysinfo(); + + if (!sysinfo) + return 0; + + return tdx_supports_runtime_update(sysinfo) ? attr->mode : 0; +} + +static const struct attribute_group seamldr_group =3D { + .attrs =3D seamldr_attrs, + .is_visible =3D seamldr_group_visible, +}; + +static const struct attribute_group *tdx_host_groups[] =3D { + &tdx_host_group, + &seamldr_group, + NULL, +}; =20 static struct faux_device *fdev; =20 --=20 2.47.1 From nobody Wed Jun 17 06:18:36 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA2E23469E7; Mon, 27 Apr 2026 15:30:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777303803; cv=none; b=Yju93AE23oZzfOu7yQEidEovEs/4Z2GlGVc2qAi/tPCrWZ4vC5W95gI1CVDmvk83CHTkApIUAJFRO5VTt1VTMe3c2ispp1sD5rseK+8UfwAw7k7N2PBYid9R4sQiQDzHe334X37gD22bdlPy9NfT9tc8VkGmpL1zLRyKKCrCldE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777303803; c=relaxed/simple; bh=9cpPVIbzbxLNuvVdcP0yIXzTtF37m4eskrQ4CNQkg8k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SYgYIh1uZMAimHTAk12ZnSWHPOBuR/JbrkM/jJOHNBCGMJnadVlw3GvT1O/80eQNjwNA0YiK1aHXKLe3GHceFi//gTljlw5GHGX+XygUdisOkxWBYEXlWNBZ6wYu3FIPoc1m7GTE7yAN+2PzkpAOFrmboYkjpXvoRZW3Wj9PlxA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=a8ligaDR; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="a8ligaDR" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777303802; x=1808839802; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9cpPVIbzbxLNuvVdcP0yIXzTtF37m4eskrQ4CNQkg8k=; b=a8ligaDRVD9bc9wD8fHkhi4esBg94plaaGBihXxoElV9Li6GBPyh2RbC 93vCXV5t93Ez5TclVN6O5QzvyE1hfzK3HQLeWHnuzlHx6CMagOJplBGft WNf4KGFjK3gPj6OLEeceueUsVP/Ot+O6sb+v70kQuMgjoZPTdylpCv/63 cN+AJarBw2GHeLiYJ8Fy8mc/U0hE+m6NvZDfkZijcyKiUPWmDOvnYnGMF VVJwx8PE+fa/21S/86SJ3Qfvo+3btRQ25so8hYy29qBEmpleabkGZXCLk 1VdJ9oI9gQzN7o0gxkgdcUIhTHg4YD6Gl2T798zqxP22K7bbJvYQcyoqR w==; X-CSE-ConnectionGUID: NYQOyIX6SqizETrw32cIZA== X-CSE-MsgGUID: FpLhcQ9PSPKG4M83Z2jKNg== X-IronPort-AV: E=McAfee;i="6800,10657,11769"; a="77900698" X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="77900698" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:29:59 -0700 X-CSE-ConnectionGUID: 0v+ln5ErTf2VanJKgYUB6w== X-CSE-MsgGUID: Gp8xSLwxSpqvt4EkcoKfcQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673236" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:29:59 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH v8 07/21] coco/tdx-host: Implement firmware upload sysfs ABI for TDX module updates Date: Mon, 27 Apr 2026 08:28:01 -0700 Message-ID: <20260427152854.101171-8-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Linux kernel supports two primary firmware update mechanisms: - request_firmware() - firmware upload (or fw_upload) The former is used by microcode updates, SEV firmware updates, etc. The latter is used by CXL and FPGA firmware updates. One key difference between them is: request_firmware() loads a named file from the filesystem where the filename is kernel-controlled, while fw_upload accepts firmware data directly from userspace. Use fw_upload for TDX module updates as loading a named file isn't suitable for TDX (see below for more reasons). Specifically, register TDX faux device with fw_upload framework to expose sysfs interfaces and implement operations to process data blobs supplied by userspace. Why fw_upload instead of request_firmware()? =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D The explicit file selection capabilities of fw_upload is preferred over the implicit file selection of request_firmware() for the following reasons: a. Intel distributes all versions of the TDX module, allowing admins to load any version rather than always defaulting to the latest. This flexibility is necessary because future extensions may require reverting to a previous version to clear fatal errors. b. Some module version series are platform-specific. For example, the 1.5.x series is for certain platform generations, while the 2.0.x series is intended for others. c. The update policy for TDX module updates is non-linear at times. The latest TDX module may not be compatible. For example, TDX module 1.5.x may be updated to 1.5.y but not to 1.5.y+1. This policy is documented separately in a file released along with each TDX module release. So, the default policy of "request_firmware()" of "always load latest", is not suitable for TDX. Userspace needs to deploy a more sophisticated policy check (e.g., latest may not be compatible), and there is potential operator choice to consider. Just have userspace pick rather than add kernel mechanism to change the default policy of request_firmware(). Signed-off-by: Chao Gao Reviewed-by: Tony Lindgren Reviewed-by: Kai Huang Reviewed-by: Kiryl Shutsemau (Meta) Link: https://lore.kernel.org/kvm/01fc8946-eb84-46fa-9458-f345dd3f6033@inte= l.com/ --- Dave also suggested making .poll_complete() optional in fw_upload_ops. That will be handled in a separate series. v8: - don't preemptively handle bugs that never occurs, i.e., drop the WARN_ON_ONCE(offset). [Dave] - tighten up the comment in .poll_complete() [Dave] - make the error-code mapping reviewable [Rick] --- arch/x86/include/asm/seamldr.h | 1 + arch/x86/virt/vmx/tdx/seamldr.c | 15 +++++ drivers/virt/coco/tdx-host/Kconfig | 2 + drivers/virt/coco/tdx-host/tdx-host.c | 87 ++++++++++++++++++++++++++- 4 files changed, 102 insertions(+), 3 deletions(-) diff --git a/arch/x86/include/asm/seamldr.h b/arch/x86/include/asm/seamldr.h index c67e5bc910a9..ac6f80f7208b 100644 --- a/arch/x86/include/asm/seamldr.h +++ b/arch/x86/include/asm/seamldr.h @@ -32,5 +32,6 @@ struct seamldr_info { static_assert(sizeof(struct seamldr_info) =3D=3D 256); =20 int seamldr_get_info(struct seamldr_info *seamldr_info); +int seamldr_install_module(const u8 *data, u32 size); =20 #endif /* _ASM_X86_SEAMLDR_H */ diff --git a/arch/x86/virt/vmx/tdx/seamldr.c b/arch/x86/virt/vmx/tdx/seamld= r.c index 7269a239bc22..650c0f097aac 100644 --- a/arch/x86/virt/vmx/tdx/seamldr.c +++ b/arch/x86/virt/vmx/tdx/seamldr.c @@ -6,6 +6,7 @@ */ #define pr_fmt(fmt) "seamldr: " fmt =20 +#include #include =20 #include @@ -41,3 +42,17 @@ int seamldr_get_info(struct seamldr_info *seamldr_info) return seamldr_call(P_SEAMLDR_INFO, &args); } EXPORT_SYMBOL_FOR_MODULES(seamldr_get_info, "tdx-host"); + +/** + * seamldr_install_module - Install a new TDX module. + * @data: Pointer to the TDX module update blob. + * @size: Size of the TDX module update blob. + * + * Returns 0 on success, negative error code on failure. + */ +int seamldr_install_module(const u8 *data, u32 size) +{ + /* TODO: Update TDX module here */ + return 0; +} +EXPORT_SYMBOL_FOR_MODULES(seamldr_install_module, "tdx-host"); diff --git a/drivers/virt/coco/tdx-host/Kconfig b/drivers/virt/coco/tdx-hos= t/Kconfig index d35d85ef91c0..ca600a39d97b 100644 --- a/drivers/virt/coco/tdx-host/Kconfig +++ b/drivers/virt/coco/tdx-host/Kconfig @@ -1,6 +1,8 @@ config TDX_HOST_SERVICES tristate "TDX Host Services Driver" depends on INTEL_TDX_HOST + select FW_LOADER + select FW_UPLOAD default m help Enable access to TDX host services like module update and diff --git a/drivers/virt/coco/tdx-host/tdx-host.c b/drivers/virt/coco/tdx-= host/tdx-host.c index 079913dcc888..d9bb1e7ef795 100644 --- a/drivers/virt/coco/tdx-host/tdx-host.c +++ b/drivers/virt/coco/tdx-host/tdx-host.c @@ -6,6 +6,7 @@ */ =20 #include +#include #include #include #include @@ -84,14 +85,19 @@ static struct attribute *seamldr_attrs[] =3D { NULL, }; =20 -static umode_t seamldr_group_visible(struct kobject *kobj, struct attribut= e *attr, int idx) +static bool can_expose_seamldr(void) { const struct tdx_sys_info *sysinfo =3D tdx_get_sysinfo(); =20 if (!sysinfo) return 0; =20 - return tdx_supports_runtime_update(sysinfo) ? attr->mode : 0; + return tdx_supports_runtime_update(sysinfo); +} + +static umode_t seamldr_group_visible(struct kobject *kobj, struct attribut= e *attr, int idx) +{ + return can_expose_seamldr() ? attr->mode : 0; } =20 static const struct attribute_group seamldr_group =3D { @@ -105,6 +111,81 @@ static const struct attribute_group *tdx_host_groups[]= =3D { NULL, }; =20 +static enum fw_upload_err tdx_fw_prepare(struct fw_upload *fwl, + const u8 *data, u32 size) +{ + return FW_UPLOAD_ERR_NONE; +} + +static enum fw_upload_err tdx_fw_write(struct fw_upload *fwl, const u8 *da= ta, + u32 offset, u32 size, u32 *written) +{ + int ret; + + ret =3D seamldr_install_module(data, size); + switch (ret) { + case 0: + *written =3D size; + return FW_UPLOAD_ERR_NONE; + default: + return FW_UPLOAD_ERR_FW_INVALID; + } +} + +static enum fw_upload_err tdx_fw_poll_complete(struct fw_upload *fwl) +{ + /* + * The upload completed during tdx_fw_write(). + * Never poll for completion. + */ + return FW_UPLOAD_ERR_NONE; +} + + +static void tdx_fw_cancel(struct fw_upload *fwl) +{ + /* + * TDX module updates are not cancellable. + * Provide a no-op callback to satisfy fw_upload_ops. + */ +} + +static const struct fw_upload_ops tdx_fw_ops =3D { + .prepare =3D tdx_fw_prepare, + .write =3D tdx_fw_write, + .poll_complete =3D tdx_fw_poll_complete, + .cancel =3D tdx_fw_cancel, +}; + +static void seamldr_deinit(void *tdx_fwl) +{ + firmware_upload_unregister(tdx_fwl); +} + +static int seamldr_init(struct device *dev) +{ + struct fw_upload *tdx_fwl; + + if (!can_expose_seamldr()) + return 0; + + tdx_fwl =3D firmware_upload_register(THIS_MODULE, dev, "tdx_module", + &tdx_fw_ops, NULL); + if (IS_ERR(tdx_fwl)) + return PTR_ERR(tdx_fwl); + + return devm_add_action_or_reset(dev, seamldr_deinit, tdx_fwl); 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27 Apr 2026 08:29:59 -0700 X-CSE-ConnectionGUID: 4LQMalnkSRuA32tY42rbnw== X-CSE-MsgGUID: cvgX8Q3YRgaa1Zf3Gt8EfQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673243" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:29:59 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH v8 08/21] x86/virt/seamldr: Allocate and populate a module update request Date: Mon, 27 Apr 2026 08:28:02 -0700 Message-ID: <20260427152854.101171-9-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" P-SEAMLDR uses the SEAMLDR_PARAMS structure to describe TDX module update requests. This structure contains physical addresses pointing to the module binary and its signature file (or sigstruct), along with an update scenario field. TDX modules are distributed in the tdx_blob format defined in blob_structure.txt from the "Intel TDX module Binaries Repository". A tdx_blob contains a header, sigstruct, and module binary. This is also the format supplied by the userspace to the kernel. Parse the tdx_blob format and populate a SEAMLDR_PARAMS structure. The header is consumed solely by the kernel to extract the sigstruct and module, so validate it before processing to protect the kernel ABI. The sigstruct and module are passed to and validated by P-SEAMLDR, so don't duplicate any validation in the kernel. Note: the sigstruct_pa field in SEAMLDR_PARAMS has been extended to a 4-element array. The updated "SEAM Loader (SEAMLDR) Interface Specification" will be published separately. Signed-off-by: Chao Gao --- v8: - Consolidate all tdx_blob validation into a dedicated helper instead of scattering checks across two functions. [Rick] - Clarify which validations are performed by the kernel and which are intentionally left to P-SEAMLDR/userspace. [Rick] - Drop free_seamldr_params() helper [Rick] - Change params->version assignment to a single sig_size > 4K expression [Rick] - Don't preemptively handle "PAGE_SIZE !=3D 4KB" [Dave] --- arch/x86/virt/vmx/tdx/seamldr.c | 155 ++++++++++++++++++++++++++++++++ 1 file changed, 155 insertions(+) diff --git a/arch/x86/virt/vmx/tdx/seamldr.c b/arch/x86/virt/vmx/tdx/seamld= r.c index 650c0f097aac..f70be8e2a07b 100644 --- a/arch/x86/virt/vmx/tdx/seamldr.c +++ b/arch/x86/virt/vmx/tdx/seamldr.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) "seamldr: " fmt =20 #include +#include #include =20 #include @@ -16,6 +17,33 @@ /* P-SEAMLDR SEAMCALL leaf function */ #define P_SEAMLDR_INFO 0x8000000000000000 =20 +#define SEAMLDR_MAX_NR_MODULE_PAGES 496 +#define SEAMLDR_MAX_NR_SIG_PAGES 4 + +/* + * The seamldr_params "scenario" field specifies the operation mode: + * 0: Install TDX module from scratch (not used by kernel) + * 1: Update existing TDX module to a compatible version + */ +#define SEAMLDR_SCENARIO_UPDATE 1 + +/* + * This is called the "SEAMLDR_PARAMS" data structure and is defined + * in "SEAM Loader (SEAMLDR) Interface Specification". + * + * It describes the TDX module that will be installed. + */ +struct seamldr_params { + u32 version; + u32 scenario; + u64 sigstruct_pa[SEAMLDR_MAX_NR_SIG_PAGES]; + u8 reserved[80]; + u64 num_module_pages; + u64 mod_pages_pa_list[SEAMLDR_MAX_NR_MODULE_PAGES]; +} __packed; + +static_assert(sizeof(struct seamldr_params) =3D=3D 4096); + /* * Serialize P-SEAMLDR calls since the hardware only allows a single CPU to * interact with P-SEAMLDR simultaneously. Use raw version as the calls can @@ -43,6 +71,128 @@ int seamldr_get_info(struct seamldr_info *seamldr_info) } EXPORT_SYMBOL_FOR_MODULES(seamldr_get_info, "tdx-host"); =20 +/* + * Intel TDX module blob. Its format is defined at: + * https://github.com/intel/tdx-module-binaries/blob/main/blob_structure.t= xt + * + * Note this structure differs from the reference above: the two variable-= length + * fields "@sigstruct" and "@module" are represented as a single "@data" f= ield + * here and split programmatically using the offset_of_module value. + * + * Note @offset_of_module is relative to the start of struct tdx_blob, not + * @data, and @length is the total length of the blob, not the length of + * @data. + */ +struct tdx_blob { + u16 version; + u16 checksum; + u32 offset_of_module; + u8 signature[8]; + u32 length; + u32 reserved0; + u64 reserved1[509]; + u8 data[]; +} __packed; + +/* Supported versions of the tdx_blob */ +#define TDX_BLOB_VERSION_1 0x100 + +/* + * Blob fields are processed by the kernel and the payloads + * are passed to the TDX module. Do normal user input type + * check for any fields that don't get passed to the TDX module. + */ +static const struct tdx_blob *get_and_check_blob(const u8 *data, u32 size) +{ + const struct tdx_blob *blob =3D (const void *)data; + + /* + * Ensure the size is valid otherwise reading any field from the + * blob may overflow. + */ + if (size <=3D sizeof(struct tdx_blob)) + return ERR_PTR(-EINVAL); + + /* + * Don't care about user passing the wrong file, but protect + * kernel ABI by preventing accepting garbage. + */ + if (memcmp(blob->signature, "TDX-BLOB", 8)) + return ERR_PTR(-EINVAL); + + /* + * Ensure the offset of the module is within valid bounds and + * page-aligned. + */ + if (blob->offset_of_module >=3D size || blob->offset_of_module <=3D sizeo= f(struct tdx_blob)) + return ERR_PTR(-EINVAL); + if (!IS_ALIGNED(blob->offset_of_module, PAGE_SIZE)) + return ERR_PTR(-EINVAL); + + if (blob->version !=3D TDX_BLOB_VERSION_1) + return ERR_PTR(-EINVAL); + + if (blob->reserved0 || memchr_inv(blob->reserved1, 0, sizeof(blob->reserv= ed1))) + return ERR_PTR(-EINVAL); + + return blob; +} + +static struct seamldr_params *alloc_seamldr_params(const struct tdx_blob *= blob, unsigned int blob_size) +{ + struct seamldr_params *params; + int module_pg_cnt, sig_pg_cnt; + const u8 *sig, *module; + int i; + + params =3D (struct seamldr_params *)get_zeroed_page(GFP_KERNEL); + if (!params) + return ERR_PTR(-ENOMEM); + + /* + * Split the blob into a sigstruct and a module. Assume all + * size/offsets are within bounds of blob_size due to prior checks. + */ + sig =3D blob->data; + sig_pg_cnt =3D (blob->offset_of_module - sizeof(struct tdx_blob)) >> PAGE= _SHIFT; + module =3D (const u8 *)blob + blob->offset_of_module; + module_pg_cnt =3D (blob_size - blob->offset_of_module) >> PAGE_SHIFT; + + /* + * Only use version 1 when required (sigstruct > 4KB) for backward + * compatibility with P-SEAMLDR that lacks version 1 support. + */ + params->version =3D sig_pg_cnt > 1; + params->scenario =3D SEAMLDR_SCENARIO_UPDATE; + + for (i =3D 0; i < MIN(sig_pg_cnt, SEAMLDR_MAX_NR_SIG_PAGES); i++) { + params->sigstruct_pa[i] =3D vmalloc_to_pfn(sig) << PAGE_SHIFT; + sig +=3D PAGE_SIZE; + } + + params->num_module_pages =3D MIN(module_pg_cnt, SEAMLDR_MAX_NR_MODULE_PAG= ES); + for (i =3D 0; i < params->num_module_pages; i++) { + params->mod_pages_pa_list[i] =3D vmalloc_to_pfn(module) << PAGE_SHIFT; + module +=3D PAGE_SIZE; + } + + return params; +} + +static struct seamldr_params *init_seamldr_params(const u8 *data, u32 size) +{ + const struct tdx_blob *blob; + + blob =3D get_and_check_blob(data, size); + if (IS_ERR(blob)) + return ERR_CAST(blob); + + return alloc_seamldr_params(blob, size); +} + +DEFINE_FREE(free_seamldr_params, struct seamldr_params *, + if (!IS_ERR_OR_NULL(_T)) free_page((unsigned long)_T)) + /** * seamldr_install_module - Install a new TDX module. * @data: Pointer to the TDX module update blob. @@ -52,6 +202,11 @@ EXPORT_SYMBOL_FOR_MODULES(seamldr_get_info, "tdx-host"); */ int seamldr_install_module(const u8 *data, u32 size) { + struct seamldr_params *params __free(free_seamldr_params) =3D + init_seamldr_params(data, size); + if (IS_ERR(params)) + return PTR_ERR(params); + /* TODO: Update TDX module here */ return 0; } --=20 2.47.1 From nobody Wed Jun 17 06:18:36 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0746834B1B0; Mon, 27 Apr 2026 15:30:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a="77900715" X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="77900715" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:00 -0700 X-CSE-ConnectionGUID: LRBEnch9QjyCYa4WFGi3sQ== X-CSE-MsgGUID: Tb7XvmEkRuGY2vYoJ0Jn5w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673248" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:00 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH v8 09/21] x86/virt/seamldr: Introduce skeleton for TDX module updates Date: Mon, 27 Apr 2026 08:28:03 -0700 Message-ID: <20260427152854.101171-10-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable TDX module updates require careful synchronization with other TDX operations. The requirements are (#1/#2 reflect current behavior that must be preserved): 1. SEAMCALLs need to be callable from both process and IRQ contexts. 2. SEAMCALLs need to be able to run concurrently across CPUs 3. During updates, only update-related SEAMCALLs are permitted; all other SEAMCALLs shouldn't be called. 4. During updates, all online CPUs must participate in the update work. No single lock primitive satisfies all requirements. For instance, rwlock_t handles #1/#2 but fails #4: CPUs spinning with IRQs disabled cannot be directed to perform update work. Use stop_machine() as it is the only well-understood mechanism that can meet all requirements. And TDX module updates consist of several steps (See Intel=C2=AE Trust Doma= in Extensions (Intel=C2=AE TDX) Module Base Architecture Specification, Chapter "TD-Preserving TDX module Update"). Ordering requirements between steps mandate lockstep synchronization across all CPUs. multi_cpu_stop() is a good example of performing a multi-step task in lockstep. But it doesn't synchronize steps within the callback function it takes. So, implement one based on its pattern to establish the skeleton for TDX module updates. Specifically, add a global state machine where each state represents a step in the update flow. The state advances only after all CPUs acknowledge completing their work in the current state. This acknowledgment mechanism is what ensures lockstep execution. Potential alternative to stop_machine() =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D An alternative approach is to lock all KVM entry points and kick all vCPUs. Here, KVM entry points refer to KVM VM/vCPU ioctl entry points, implemented in KVM common code (virt/kvm). Adding a locking mechanism there would affect all architectures KVM supports. And to lock only TDX vCPUs, new logic would be needed to identify TDX vCPUs, which the KVM common code currently lacks. This would add significant complexity and maintenance overhead to KVM for this TDX-specific use case, so don't take this approach. Signed-off-by: Chao Gao Reviewed-by: Xu Yilun Reviewed-by: Tony Lindgren Reviewed-by: Kai Huang Reviewed-by: Kiryl Shutsemau (Meta) Reviewed-by: Rick Edgecombe --- v8: - Add a "so don't take this approach" after alternative solution discussion in the changelog [Rick] - Use imperative mood for a comment [Dave] --- arch/x86/virt/vmx/tdx/seamldr.c | 79 ++++++++++++++++++++++++++++++++- 1 file changed, 77 insertions(+), 2 deletions(-) diff --git a/arch/x86/virt/vmx/tdx/seamldr.c b/arch/x86/virt/vmx/tdx/seamld= r.c index f70be8e2a07b..aa839aaeb79d 100644 --- a/arch/x86/virt/vmx/tdx/seamldr.c +++ b/arch/x86/virt/vmx/tdx/seamldr.c @@ -7,8 +7,10 @@ #define pr_fmt(fmt) "seamldr: " fmt =20 #include +#include #include #include +#include =20 #include =20 @@ -190,6 +192,77 @@ static struct seamldr_params *init_seamldr_params(cons= t u8 *data, u32 size) return alloc_seamldr_params(blob, size); } =20 +/* + * During a TDX module update, all CPUs start from MODULE_UPDATE_START and + * progress to MODULE_UPDATE_DONE. Each state is associated with certain + * work. For some states, just one CPU needs to perform the work, while + * other CPUs just wait during those states. + */ +enum module_update_state { + MODULE_UPDATE_START, + MODULE_UPDATE_DONE, +}; + +static struct { + enum module_update_state state; + int thread_ack; + /* + * Protect update_data. Raw spinlock as it will be acquired from + * interrupt-disabled contexts. + */ + raw_spinlock_t lock; +} update_data =3D { + .lock =3D __RAW_SPIN_LOCK_UNLOCKED(update_data.lock) +}; + +static void set_target_state(enum module_update_state state) +{ + /* Reset ack counter. */ + update_data.thread_ack =3D num_online_cpus(); + update_data.state =3D state; +} + +/* Last one to ack a state moves to the next state. */ +static void ack_state(void) +{ + guard(raw_spinlock)(&update_data.lock); + update_data.thread_ack--; + if (!update_data.thread_ack) + set_target_state(update_data.state + 1); +} + +/* + * See multi_cpu_stop() from where this multi-cpu state-machine was + * adopted, and the rationale for touch_nmi_watchdog(). + */ +static int do_seamldr_install_module(void *seamldr_params) +{ + enum module_update_state newstate, curstate =3D MODULE_UPDATE_START; + int ret =3D 0; + + do { + /* Chill out and re-read update_data. */ + cpu_relax(); + newstate =3D READ_ONCE(update_data.state); + + if (newstate !=3D curstate) { + curstate =3D newstate; + switch (curstate) { + /* TODO: add the update steps. */ + default: + break; + } + + ack_state(); + } else { + touch_nmi_watchdog(); + rcu_momentary_eqs(); + } + } while (curstate !=3D MODULE_UPDATE_DONE); + + return ret; +} + DEFINE_FREE(free_seamldr_params, struct seamldr_params *, if (!IS_ERR_OR_NULL(_T)) free_page((unsigned long)_T)) =20 @@ -207,7 +280,9 @@ int seamldr_install_module(const u8 *data, u32 size) if (IS_ERR(params)) return PTR_ERR(params); =20 - /* TODO: Update TDX module here */ - return 0; + /* Ensure a stable set of online CPUs for the update process. */ + guard(cpus_read_lock)(); + set_target_state(MODULE_UPDATE_START + 1); + return stop_machine_cpuslocked(do_seamldr_install_module, params, cpu_onl= ine_mask); } EXPORT_SYMBOL_FOR_MODULES(seamldr_install_module, "tdx-host"); --=20 2.47.1 From nobody Wed Jun 17 06:18:36 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 60E8834D384; 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a="77900725" X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="77900725" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:01 -0700 X-CSE-ConnectionGUID: zrfaTJLeQNm8gzF0oripOw== X-CSE-MsgGUID: WD2kDBxITyW24dNw7bBCOQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673265" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:01 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH v8 10/21] x86/virt/seamldr: Shut down the current TDX module Date: Mon, 27 Apr 2026 08:28:04 -0700 Message-ID: <20260427152854.101171-11-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The first step of TDX module updates is shutting down the current TDX Module. This step also packs state information that needs to be preserved across updates as handoff data, which will be consumed by the updated module. The handoff data is stored internally in the SEAM range and is hidden from the kernel. To ensure a successful update, the new module must be able to consume the handoff data generated by the old module. Since handoff data layout may change between modules, the handoff data is versioned. Each module has a native handoff version and provides backward support for several older versions. The complete handoff versioning protocol is complex as it supports both module upgrades and downgrades. See details in Intel=C2=AE Trust Domain Extensions (Intel=C2=AE TDX) Module Base Architecture Specification, Chapter "Handoff Versioning". Ideally, the kernel needs to retrieve the handoff versions supported by the current module and the new module and select a version supported by both. But, since this implementation chooses to only support module upgrades, simply request the current module to generate handoff data using its highest supported version, expecting that the new module will likely support it. Retrieve the module's handoff version from TDX global metadata and add an update step to shut down the module. Module shutdown has global effect, so it only needs to run on one CPU. Note that the handoff information isn't cached in tdx_sysinfo. It is used only for module shutdown, and is present only when the TDX module supports updates. Caching it in get_tdx_sys_info() would require extra update-support guards and refreshing the cached value across module updates. Signed-off-by: Chao Gao Reviewed-by: Tony Lindgren Reviewed-by: Xu Yilun Reviewed-by: Kai Huang Reviewed-by: Kiryl Shutsemau (Meta) --- v8: - Enhance the changelog to also talk about what the patch does instead of just "why". [Rick] - For simplicity, don't cache handoff version in tdx_sysinfo --- arch/x86/include/asm/tdx_global_metadata.h | 4 ++++ arch/x86/virt/vmx/tdx/seamldr.c | 11 ++++++++++- arch/x86/virt/vmx/tdx/tdx.c | 19 ++++++++++++++++++- arch/x86/virt/vmx/tdx/tdx.h | 3 +++ arch/x86/virt/vmx/tdx/tdx_global_metadata.c | 13 +++++++++++++ 5 files changed, 48 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/tdx_global_metadata.h b/arch/x86/include/= asm/tdx_global_metadata.h index 40689c8dc67e..41150d546589 100644 --- a/arch/x86/include/asm/tdx_global_metadata.h +++ b/arch/x86/include/asm/tdx_global_metadata.h @@ -40,6 +40,10 @@ struct tdx_sys_info_td_conf { u64 cpuid_config_values[128][2]; }; =20 +struct tdx_sys_info_handoff { + u16 module_hv; +}; + struct tdx_sys_info { struct tdx_sys_info_version version; struct tdx_sys_info_features features; diff --git a/arch/x86/virt/vmx/tdx/seamldr.c b/arch/x86/virt/vmx/tdx/seamld= r.c index aa839aaeb79d..f995153f24b9 100644 --- a/arch/x86/virt/vmx/tdx/seamldr.c +++ b/arch/x86/virt/vmx/tdx/seamldr.c @@ -15,6 +15,7 @@ #include =20 #include "seamcall_internal.h" +#include "tdx.h" =20 /* P-SEAMLDR SEAMCALL leaf function */ #define P_SEAMLDR_INFO 0x8000000000000000 @@ -200,6 +201,7 @@ static struct seamldr_params *init_seamldr_params(const= u8 *data, u32 size) */ enum module_update_state { MODULE_UPDATE_START, + MODULE_UPDATE_SHUTDOWN, MODULE_UPDATE_DONE, }; =20 @@ -238,8 +240,12 @@ static void ack_state(void) static int do_seamldr_install_module(void *seamldr_params) { enum module_update_state newstate, curstate =3D MODULE_UPDATE_START; + int cpu =3D smp_processor_id(); + bool primary; int ret =3D 0; =20 + primary =3D cpumask_first(cpu_online_mask) =3D=3D cpu; + do { /* Chill out and re-read update_data. */ cpu_relax(); @@ -248,7 +254,10 @@ static int do_seamldr_install_module(void *seamldr_par= ams) if (newstate !=3D curstate) { curstate =3D newstate; switch (curstate) { - /* TODO: add the update steps. */ + case MODULE_UPDATE_SHUTDOWN: + if (primary) + ret =3D tdx_module_shutdown(); + break; default: break; } diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 05d241626e48..d28421ac4180 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -287,7 +287,7 @@ static __init int build_tdx_memlist(struct list_head *t= mb_list) return ret; } =20 -static __init int read_sys_metadata_field(u64 field_id, u64 *data) +static int read_sys_metadata_field(u64 field_id, u64 *data) { struct tdx_module_args args =3D {}; int ret; @@ -1233,6 +1233,23 @@ static __init int tdx_enable(void) } subsys_initcall(tdx_enable); =20 +int tdx_module_shutdown(void) +{ + struct tdx_sys_info_handoff handoff =3D {}; + struct tdx_module_args args =3D {}; + int ret; + + ret =3D get_tdx_sys_info_handoff(&handoff); + WARN_ON_ONCE(ret); + + /* + * Use the module's handoff version as it is the highest the + * module can produce and most likely supported by newer modules. + */ + args.rcx =3D handoff.module_hv; + return seamcall_prerr(TDH_SYS_SHUTDOWN, &args); +} + static bool is_pamt_page(unsigned long phys) { struct tdmr_info_list *tdmr_list =3D &tdx_tdmr_list; diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h index dde219c823b4..36afebf0e04b 100644 --- a/arch/x86/virt/vmx/tdx/tdx.h +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -46,6 +46,7 @@ #define TDH_PHYMEM_PAGE_WBINVD 41 #define TDH_VP_WR 43 #define TDH_SYS_CONFIG 45 +#define TDH_SYS_SHUTDOWN 52 =20 /* * SEAMCALL leaf: @@ -110,4 +111,6 @@ struct tdmr_info_list { int max_tdmrs; /* How many 'tdmr_info's are allocated */ }; =20 +int tdx_module_shutdown(void); + #endif diff --git a/arch/x86/virt/vmx/tdx/tdx_global_metadata.c b/arch/x86/virt/vm= x/tdx/tdx_global_metadata.c index d54d4227990c..e793dec688ab 100644 --- a/arch/x86/virt/vmx/tdx/tdx_global_metadata.c +++ b/arch/x86/virt/vmx/tdx/tdx_global_metadata.c @@ -100,6 +100,19 @@ static __init int get_tdx_sys_info_td_conf(struct tdx_= sys_info_td_conf *sysinfo_ return ret; } =20 +static int get_tdx_sys_info_handoff(struct tdx_sys_info_handoff *sysinfo_h= andoff) +{ + int ret; + u64 val; + + ret =3D read_sys_metadata_field(0x8900000100000000, &val); + if (ret) + return ret; + + sysinfo_handoff->module_hv =3D val; + return 0; +} + static __init int get_tdx_sys_info(struct tdx_sys_info *sysinfo) { int ret =3D 0; --=20 2.47.1 From nobody Wed Jun 17 06:18:36 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1620E34CFD0; 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a="77900734" X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="77900734" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:01 -0700 X-CSE-ConnectionGUID: XKB/eandQ+SnX38venfP5g== X-CSE-MsgGUID: eEpcX28PTiaz9HacQj9DPA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673272" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:01 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH v8 11/21] x86/virt/tdx: Reset software states during TDX module shutdown Date: Mon, 27 Apr 2026 08:28:05 -0700 Message-ID: <20260427152854.101171-12-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The TDX module requires a one-time global initialization (TDH.SYS.INIT) and per-CPU initialization (TDH.SYS.LP.INIT) before use. These initializations are guarded by software flags to prevent repetition. After TDX module updates, the new TDX module requires the same global and per-CPU initializations, but the existing software flags prevent re-initialization. Reset all software flags guarding the initialization flows to allow the global and per-CPU initializations to be triggered again after updates. As tdx_module_initialized is changed at runtime, drop its "__ro_after_init" tag. Signed-off-by: Chao Gao Reviewed-by: Tony Lindgren Reviewed-by: Kai Huang Reviewed-by: Rick Edgecombe --- v8: - drop "__ro_after_init" from tdx_module_initialized. --- arch/x86/virt/vmx/tdx/tdx.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index d28421ac4180..ff5644f5daa4 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -55,11 +55,14 @@ static DEFINE_PER_CPU(bool, tdx_lp_initialized); =20 static struct tdmr_info_list tdx_tdmr_list; =20 +static bool sysinit_done; +static int sysinit_ret; + /* All TDX-usable memory regions. Protected by mem_hotplug_lock. */ static LIST_HEAD(tdx_memlist); =20 static struct tdx_sys_info tdx_sysinfo __ro_after_init; -static bool tdx_module_initialized __ro_after_init; +static bool tdx_module_initialized; =20 /* * Do the module global initialization once and return its result. @@ -69,8 +72,6 @@ static int try_init_module_global(void) { struct tdx_module_args args =3D {}; static DEFINE_RAW_SPINLOCK(sysinit_lock); - static bool sysinit_done; - static int sysinit_ret; =20 raw_spin_lock(&sysinit_lock); =20 @@ -1237,7 +1238,7 @@ int tdx_module_shutdown(void) { struct tdx_sys_info_handoff handoff =3D {}; struct tdx_module_args args =3D {}; - int ret; + int ret, cpu; =20 ret =3D get_tdx_sys_info_handoff(&handoff); WARN_ON_ONCE(ret); @@ -1247,7 +1248,22 @@ int tdx_module_shutdown(void) * module can produce and most likely supported by newer modules. */ args.rcx =3D handoff.module_hv; - return seamcall_prerr(TDH_SYS_SHUTDOWN, &args); + ret =3D seamcall_prerr(TDH_SYS_SHUTDOWN, &args); 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Peter Anvin" Subject: [PATCH v8 12/21] x86/virt/seamldr: Install a new TDX module Date: Mon, 27 Apr 2026 08:28:06 -0700 Message-ID: <20260427152854.101171-13-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Following the shutdown of the existing TDX module, the update process continues with installing the new module. P-SEAMLDR provides the SEAMLDR.INSTALL SEAMCALL to perform this installation, which must be executed on all CPUs. Implement SEAMLDR.INSTALL and execute it on every CPU. Signed-off-by: Chao Gao Reviewed-by: Tony Lindgren Reviewed-by: Kai Huang Reviewed-by: Xu Yilun Reviewed-by: Kiryl Shutsemau (Meta) Reviewed-by: Rick Edgecombe --- v8: - Standardize tdx_module_args initialization. For consistency, initialize each field on separate lines after declaration, instead of initializing them in the declaration. --- arch/x86/virt/vmx/tdx/seamldr.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/x86/virt/vmx/tdx/seamldr.c b/arch/x86/virt/vmx/tdx/seamld= r.c index f995153f24b9..317b38c4aa19 100644 --- a/arch/x86/virt/vmx/tdx/seamldr.c +++ b/arch/x86/virt/vmx/tdx/seamldr.c @@ -19,6 +19,7 @@ =20 /* P-SEAMLDR SEAMCALL leaf function */ #define P_SEAMLDR_INFO 0x8000000000000000 +#define P_SEAMLDR_INSTALL 0x8000000000000001 =20 #define SEAMLDR_MAX_NR_MODULE_PAGES 496 #define SEAMLDR_MAX_NR_SIG_PAGES 4 @@ -74,6 +75,14 @@ int seamldr_get_info(struct seamldr_info *seamldr_info) } EXPORT_SYMBOL_FOR_MODULES(seamldr_get_info, "tdx-host"); =20 +static int seamldr_install(const struct seamldr_params *params) +{ + struct tdx_module_args args =3D {}; + + args.rcx =3D __pa(params); + return seamldr_call(P_SEAMLDR_INSTALL, &args); +} + /* * Intel TDX module blob. Its format is defined at: * https://github.com/intel/tdx-module-binaries/blob/main/blob_structure.t= xt @@ -202,6 +211,7 @@ static struct seamldr_params *init_seamldr_params(const= u8 *data, u32 size) enum module_update_state { MODULE_UPDATE_START, MODULE_UPDATE_SHUTDOWN, + MODULE_UPDATE_CPU_INSTALL, MODULE_UPDATE_DONE, }; =20 @@ -258,6 +268,9 @@ static int do_seamldr_install_module(void *seamldr_para= ms) if (primary) ret =3D tdx_module_shutdown(); break; + case MODULE_UPDATE_CPU_INSTALL: + ret =3D seamldr_install(seamldr_params); + break; default: break; } --=20 2.47.1 From nobody Wed Jun 17 06:18:36 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CEE8C34D90C; Mon, 27 Apr 2026 15:30:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777303809; cv=none; b=uMPwKsFnxl6fDBXHdmCw2mz8+fygvrC6WgkiCofmVznIeTCrzr4O68dONqmahbCj6BIToz7JFoRPB7Ab4aG7LazEY7BQWMCYNM48G7H8R7DlxZjnSAUgl+F+enJHqgcJFwPXHnmPAYd8+0zPt7gbzOwgb7/f/Ij06hArNWbECcU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777303809; c=relaxed/simple; bh=awQLLVxSD7rc3F1aejYYETIC3I3QjxeXun497n3ZsXw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=L6KYcUIa4x/BbPLsVaKV2jWOFj7eLz3g6ak/HpVp6HuKYDrG81T0Le+bAsKRPEusKGf0dhE39O2FXHu6boTcy7xB98HHTk44SpJ1Dc4xSHbmAzh93ByOq2uSv+9eY/2z6NTLk6gao0rGPAHhrh/GNY8a9E//MYTHTo7celp3N6k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FyVOMoPH; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FyVOMoPH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777303807; x=1808839807; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=awQLLVxSD7rc3F1aejYYETIC3I3QjxeXun497n3ZsXw=; b=FyVOMoPH1Iae0iB+SVaH0IeiekjUedTTJ8iqmZRMUrEEaSi4vYuhQiKf jwiQmIMjE2HR8FqOGJAuOoudRZ1kk7waz4ekYTuAZ5/0oEYckRFHOlWr4 yHwZHxsR0CYH4fgX2wDKV9FWiQUMc69yjB/bNLtYpTQz+46S2oxW4bldr D1Fjf/PPnEoMNejBQV7P88d0vhkcnrmy55ubzwoRY+6IK8KkLncFKT3ro 4u2H/ErfTjUJBw5F7dZvHLlYTBvaxKG5mPFNrHD68qE2714N5DDKuwZe9 kCuTTge0gzDCkC1KjPemxnVU2qwIRyW1tFUKuNswfxEdKS0LMUJcHNd8g Q==; X-CSE-ConnectionGUID: AKVctQ9VSQm31wz9zXm78Q== X-CSE-MsgGUID: KkvTnSiBQ2SiE/7zPUaLvg== X-IronPort-AV: E=McAfee;i="6800,10657,11769"; a="77900751" X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="77900751" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:02 -0700 X-CSE-ConnectionGUID: +1JjX1oVRASxTQq2sMninw== X-CSE-MsgGUID: YcezkSyaRHycFt+3JCK/Fg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673288" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:02 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH v8 13/21] x86/virt/seamldr: Do TDX per-CPU initialization after module installation Date: Mon, 27 Apr 2026 08:28:07 -0700 Message-ID: <20260427152854.101171-14-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" After installing the new TDX module, each CPU needs to be initialized again to make the CPU ready to run any other SEAMCALLs. So, export and call tdx_cpu_enable() on all CPUs. Signed-off-by: Chao Gao Reviewed-by: Xu Yilun Reviewed-by: Tony Lindgren Reviewed-by: Kai Huang Reviewed-by: Kiryl Shutsemau (Meta) Reviewed-by: Rick Edgecombe --- v8: - export tdx_cpu_enable(). it is unexported by VMXON series. --- arch/x86/include/asm/tdx.h | 1 + arch/x86/virt/vmx/tdx/seamldr.c | 4 ++++ arch/x86/virt/vmx/tdx/tdx.c | 2 +- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index 1c5981453ff8..de822ed9ef0b 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -104,6 +104,7 @@ static inline long tdx_kvm_hypercall(unsigned int nr, u= nsigned long p1, =20 #ifdef CONFIG_INTEL_TDX_HOST void tdx_init(void); +int tdx_cpu_enable(void); const char *tdx_dump_mce_info(struct mce *m); const struct tdx_sys_info *tdx_get_sysinfo(void); =20 diff --git a/arch/x86/virt/vmx/tdx/seamldr.c b/arch/x86/virt/vmx/tdx/seamld= r.c index 317b38c4aa19..04c7a87ac7df 100644 --- a/arch/x86/virt/vmx/tdx/seamldr.c +++ b/arch/x86/virt/vmx/tdx/seamldr.c @@ -212,6 +212,7 @@ enum module_update_state { MODULE_UPDATE_START, MODULE_UPDATE_SHUTDOWN, MODULE_UPDATE_CPU_INSTALL, + MODULE_UPDATE_CPU_INIT, MODULE_UPDATE_DONE, }; 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a="77900760" X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="77900760" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:03 -0700 X-CSE-ConnectionGUID: FDyS1Dm+QkCWCi264f1Ydw== X-CSE-MsgGUID: UNXKPTXWS5eW0H/gkBR3mg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673300" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:03 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH v8 14/21] x86/virt/tdx: Restore TDX module state Date: Mon, 27 Apr 2026 08:28:08 -0700 Message-ID: <20260427152854.101171-15-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable TDX module state was packed as handoff data during module shutdown. After per-CPU initialization, the new module can restore TDX module state from handoff data to preserve running TDs. Once the restoration is done, the TDX module update is complete, which means the new module is ready to handle requests from the host and guests. Implement the new TDH.SYS.UPDATE SEAMCALL to restore TDX module state and invoke it on one CPU since it only needs to be called once. For error handling, Intel=C2=AE Trust Domain Extensions (Intel=C2=AE TDX) Module Base Architecture Specification, Chapter "Restore TDX Module State after a TD-Preserving Update" states If TDH.SYS.UPDATE returns an error, then the host VMM can continue with the non-update sequence (TDH.SYS.CONFIG, TDH.SYS.KEY.CONFIG etc.). In this case all existing TDs are lost. Alternatively, the host VMM can request the P-SEAMLDR to update to another TDX module. If that update is successful, existing TDs are preserved. Given the complexity and uncertain value of above recovery paths, simply propagate errors. Also note that the location and the format of handoff data is defined by the TDX module. The new module knows where to get handoff data and how to parse it. The kernel doesn't need to provide its location, format etc. Signed-off-by: Chao Gao Reviewed-by: Tony Lindgren Reviewed-by: Kai Huang Reviewed-by: Kiryl Shutsemau (Meta) Reviewed-by: Rick Edgecombe --- v8: - don't add a duplicate error code as seamcal_prerr() will do that - don't reset tdx module status to ERORR on error --- arch/x86/virt/vmx/tdx/seamldr.c | 5 +++++ arch/x86/virt/vmx/tdx/tdx.c | 13 +++++++++++++ arch/x86/virt/vmx/tdx/tdx.h | 2 ++ 3 files changed, 20 insertions(+) diff --git a/arch/x86/virt/vmx/tdx/seamldr.c b/arch/x86/virt/vmx/tdx/seamld= r.c index 04c7a87ac7df..98a8d9d3ae25 100644 --- a/arch/x86/virt/vmx/tdx/seamldr.c +++ b/arch/x86/virt/vmx/tdx/seamldr.c @@ -213,6 +213,7 @@ enum module_update_state { MODULE_UPDATE_SHUTDOWN, MODULE_UPDATE_CPU_INSTALL, MODULE_UPDATE_CPU_INIT, + MODULE_UPDATE_RUN_UPDATE, MODULE_UPDATE_DONE, }; =20 @@ -275,6 +276,10 @@ static int do_seamldr_install_module(void *seamldr_par= ams) case MODULE_UPDATE_CPU_INIT: ret =3D tdx_cpu_enable(); break; + case MODULE_UPDATE_RUN_UPDATE: + if (primary) + ret =3D tdx_module_run_update(); + break; default: break; } diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 3bbb12aefb4b..9e4085a1e683 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -1266,6 +1266,19 @@ int tdx_module_shutdown(void) return 0; } =20 +int tdx_module_run_update(void) +{ + struct tdx_module_args args =3D {}; + int ret; + + ret =3D seamcall_prerr(TDH_SYS_UPDATE, &args); + if (ret) + return ret; + + tdx_module_initialized =3D true; + return 0; +} + static bool is_pamt_page(unsigned long phys) { struct tdmr_info_list *tdmr_list =3D &tdx_tdmr_list; diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h index 36afebf0e04b..5fef813002c2 100644 --- a/arch/x86/virt/vmx/tdx/tdx.h +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -47,6 +47,7 @@ #define TDH_VP_WR 43 #define TDH_SYS_CONFIG 45 #define TDH_SYS_SHUTDOWN 52 +#define TDH_SYS_UPDATE 53 =20 /* * SEAMCALL leaf: @@ -112,5 +113,6 @@ struct tdmr_info_list { }; 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Peter Anvin" Subject: [PATCH v8 15/21] x86/virt/tdx: Refresh TDX module version after update Date: Mon, 27 Apr 2026 08:28:09 -0700 Message-ID: <20260427152854.101171-16-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The kernel exposes the TDX module version through sysfs so userspace can check update compatibility. That information needs to remain accurate across runtime updates. A runtime update may change the module's update_version, so refresh the cached version after a successful update and emit a log message to show the version change. Drop __ro_after_init from tdx_sysinfo because it is now updated at runtime. Perform the refresh outside of stop_machine() since printk() within stop_machine() would add significant latency. Do not refresh the rest of tdx_sysinfo. Refreshing them at runtime could disrupt running software that relies on the previously reported values. Note that major and minor versions are not refreshed because runtime updates are supported only between releases with identical major and minor versions. Signed-off-by: Chao Gao --- Sashiko flagged a potential torn-read concern: update_version is read via sysfs while it is refreshed post-update. But, update_version is a naturally-aligned u16, and on x86, the compiler won't split aligned u16 accesses. So READ_ONCE/WRITE_ONCE() aren't needed for update_version. v8: - drop the unnecessary old/new metadata comparison - do not refresh the handoff version, since it is no longer cached - rename the helper to reflect its purpose instead of using the generic tdx_module_post_update() --- arch/x86/virt/vmx/tdx/seamldr.c | 8 +++++++- arch/x86/virt/vmx/tdx/tdx.c | 21 ++++++++++++++++++++- arch/x86/virt/vmx/tdx/tdx.h | 1 + arch/x86/virt/vmx/tdx/tdx_global_metadata.c | 2 +- 4 files changed, 29 insertions(+), 3 deletions(-) diff --git a/arch/x86/virt/vmx/tdx/seamldr.c b/arch/x86/virt/vmx/tdx/seamld= r.c index 98a8d9d3ae25..c81b26c4bac1 100644 --- a/arch/x86/virt/vmx/tdx/seamldr.c +++ b/arch/x86/virt/vmx/tdx/seamldr.c @@ -306,6 +306,8 @@ DEFINE_FREE(free_seamldr_params, struct seamldr_params = *, */ int seamldr_install_module(const u8 *data, u32 size) { + int ret; + struct seamldr_params *params __free(free_seamldr_params) =3D init_seamldr_params(data, size); if (IS_ERR(params)) @@ -314,6 +316,10 @@ int seamldr_install_module(const u8 *data, u32 size) /* Ensure a stable set of online CPUs for the update process. */ guard(cpus_read_lock)(); set_target_state(MODULE_UPDATE_START + 1); - return stop_machine_cpuslocked(do_seamldr_install_module, params, cpu_onl= ine_mask); + ret =3D stop_machine_cpuslocked(do_seamldr_install_module, params, cpu_on= line_mask); + if (ret) + return ret; + + return tdx_module_refresh_version(); } EXPORT_SYMBOL_FOR_MODULES(seamldr_install_module, "tdx-host"); diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 9e4085a1e683..a7dfa4ee8813 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -61,7 +61,7 @@ static int sysinit_ret; /* All TDX-usable memory regions. Protected by mem_hotplug_lock. */ static LIST_HEAD(tdx_memlist); =20 -static struct tdx_sys_info tdx_sysinfo __ro_after_init; +static struct tdx_sys_info tdx_sysinfo; static bool tdx_module_initialized; =20 /* @@ -1279,6 +1279,25 @@ int tdx_module_run_update(void) return 0; } =20 +int tdx_module_refresh_version(void) +{ + struct tdx_sys_info_version *old, new; + int ret; + + /* Shouldn't fail as the update has succeeded. */ + ret =3D get_tdx_sys_info_version(&new); + WARN_ON_ONCE(ret); + + old =3D &tdx_sysinfo.version; + pr_info("version " TDX_VERSION_FMT " -> " TDX_VERSION_FMT "\n", + old->major_version, old->minor_version, old->update_version, + new.major_version, new.minor_version, new.update_version); + + /* Major/minor versions should not change across updates. */ + tdx_sysinfo.version.update_version =3D new.update_version; + return 0; +} + static bool is_pamt_page(unsigned long phys) { struct tdmr_info_list *tdmr_list =3D &tdx_tdmr_list; diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h index 5fef813002c2..d0e8cac9c1d5 100644 --- a/arch/x86/virt/vmx/tdx/tdx.h +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -114,5 +114,6 @@ struct tdmr_info_list { =20 int tdx_module_shutdown(void); int tdx_module_run_update(void); +int tdx_module_refresh_version(void); =20 #endif diff --git a/arch/x86/virt/vmx/tdx/tdx_global_metadata.c b/arch/x86/virt/vm= x/tdx/tdx_global_metadata.c index e793dec688ab..e49c300f23d4 100644 --- a/arch/x86/virt/vmx/tdx/tdx_global_metadata.c +++ b/arch/x86/virt/vmx/tdx/tdx_global_metadata.c @@ -7,7 +7,7 @@ * Include this file to other C file instead. */ =20 -static __init int get_tdx_sys_info_version(struct tdx_sys_info_version *sy= sinfo_version) +static int get_tdx_sys_info_version(struct tdx_sys_info_version *sysinfo_v= ersion) { int ret =3D 0; u64 val; --=20 2.47.1 From nobody Wed Jun 17 06:18:36 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 988BE3B4EA4; Mon, 27 Apr 2026 15:30:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; 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27 Apr 2026 08:30:05 -0700 X-CSE-ConnectionGUID: OML46hBoTWm2L6OHLNxcdQ== X-CSE-MsgGUID: nzLRMxpaRdWzm/o69g8kSw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673335" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:05 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH v8 16/21] x86/virt/tdx: Reject updates during concurrent TD build Date: Mon, 27 Apr 2026 08:28:10 -0700 Message-ID: <20260427152854.101171-17-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" tl;dr: A TDX module erratum can silently corrupt TD measurement state if a module update races with TD build. Handle that by rejecting the update, instead of introducing new TD-build ioctl failure paths. Long Version: Updates must not break unrelated operations. For TDX module updates, this means an update must not interfere with other TDX flows. A TDX module erratum violates that expectation: if an update races with TD build, TD build output can be corrupted, e.g. the measurement hash, which later causes attestation failure. The TDX module provides two independent, opt-in mitigations for this erratum: 1. Reject updates while TD build is in progress. This mitigation can be requested via TDH.SYS.SHUTDOWN. 2. Do not reject the update for this race, but instead fail later SEAMCALLs in the overlapping TD build flow. This mitigation can be requested via TDH.SYS.UPDATE. The kernel can choose option 1, option 2, or neither. Choose option 1 to confine failures to the update path and preserve existing TD build and KVM ioctl behavior. Userspace already controls update timing, and retrying a rejected update is straightforward. Option 2 would make TD build failures explicit, but it would also introduce new error paths in existing KVM ioctls. That complicates KVM error handling and risks ABI instability. Sean previously rejected that approach [1]. Choosing neither option was also considered and rejected. Leaving this erratum unhandled would allow an update racing with TD build to silently corrupt TD build output. That violates the requirement that TDX module updates must not interfere with unrelated TDX flows. Request race detection during TDH.SYS.SHUTDOWN and map a detected race to -EBUSY, and report it to userspace as FW_UPLOAD_ERR_BUSY. This lets userspace distinguish the race from other failures and retry the update. Do not pre-check support for this race-detection capability. If it is unsupported, rely on the TDX module to reject module shutdown. This implementation is based on a reference patch by Vishal [2]. Note: moving NO_RBP_MOD definition is to centralize the bit definitions. Signed-off-by: Chao Gao Acked-by: Sean Christopherson Link: https://lore.kernel.org/linux-coco/aQIbM5m09G0FYTzE@google.com/ # [1] Link: https://lore.kernel.org/linux-coco/CAGtprH_oR44Vx9Z0cfxvq5-QbyLmy_+Gn= 3tWm3wzHPmC1nC0eg@mail.gmail.com/ # [2] --- v8: - rewrite the changelog [Rick] - alway pass the compat flag to the TDX module [Rick] --- arch/x86/include/asm/tdx.h | 11 +++++++++-- arch/x86/kvm/vmx/tdx_errno.h | 2 -- arch/x86/virt/vmx/tdx/tdx.c | 26 +++++++++++++++++++++++--- arch/x86/virt/vmx/tdx/tdx.h | 3 --- drivers/virt/coco/tdx-host/tdx-host.c | 2 ++ 5 files changed, 34 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index de822ed9ef0b..b063aabe2554 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -26,11 +26,18 @@ #define TDX_SEAMCALL_GP (TDX_SW_ERROR | X86_TRAP_GP) #define TDX_SEAMCALL_UD (TDX_SW_ERROR | X86_TRAP_UD) =20 +#define TDX_SEAMCALL_STATUS_MASK 0xFFFFFFFF00000000ULL + /* * TDX module SEAMCALL leaf function error codes */ -#define TDX_SUCCESS 0ULL -#define TDX_RND_NO_ENTROPY 0x8000020300000000ULL +#define TDX_SUCCESS 0ULL +#define TDX_RND_NO_ENTROPY 0x8000020300000000ULL +#define TDX_UPDATE_COMPAT_SENSITIVE 0x8000051200000000ULL + +/* Bit definitions of TDX_FEATURES0 metadata field */ +#define TDX_FEATURES0_NO_RBP_MOD BIT_ULL(18) +#define TDX_FEATURES0_UPDATE_COMPAT BIT_ULL(47) =20 #ifndef __ASSEMBLER__ =20 diff --git a/arch/x86/kvm/vmx/tdx_errno.h b/arch/x86/kvm/vmx/tdx_errno.h index 6ff4672c4181..215c00d76a94 100644 --- a/arch/x86/kvm/vmx/tdx_errno.h +++ b/arch/x86/kvm/vmx/tdx_errno.h @@ -4,8 +4,6 @@ #ifndef __KVM_X86_TDX_ERRNO_H #define __KVM_X86_TDX_ERRNO_H =20 -#define TDX_SEAMCALL_STATUS_MASK 0xFFFFFFFF00000000ULL - /* * TDX SEAMCALL Status Codes (returned in RAX) */ diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index a7dfa4ee8813..7864ab68f4e3 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -1234,10 +1234,13 @@ static __init int tdx_enable(void) } subsys_initcall(tdx_enable); =20 +#define TDX_SYS_SHUTDOWN_AVOID_COMPAT_SENSITIVE BIT(16) + int tdx_module_shutdown(void) { struct tdx_sys_info_handoff handoff =3D {}; struct tdx_module_args args =3D {}; + u64 err; int ret, cpu; =20 ret =3D get_tdx_sys_info_handoff(&handoff); @@ -1248,9 +1251,26 @@ int tdx_module_shutdown(void) * module can produce and most likely supported by newer modules. */ args.rcx =3D handoff.module_hv; - ret =3D seamcall_prerr(TDH_SYS_SHUTDOWN, &args); - if (ret) - return ret; + + /* + * Mitigate the erratum where updates can break concurrent TD + * build. Do not pre-check support for this flag. If unsupported, + * rely on the TDX module to reject shutdown requests. + */ + args.rcx |=3D TDX_SYS_SHUTDOWN_AVOID_COMPAT_SENSITIVE; + + err =3D seamcall(TDH_SYS_SHUTDOWN, &args); + + /* + * Return -EBUSY to signal that some ongoing flows are incompatible + * with updates so that userspace can retry. + */ + if ((err & TDX_SEAMCALL_STATUS_MASK) =3D=3D TDX_UPDATE_COMPAT_SENSITIVE) + return -EBUSY; + if (err) { + seamcall_err(TDH_SYS_SHUTDOWN, err, &args); + return -EIO; + } =20 /* * Clear global and per-CPU initialization flags so the new module diff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h index d0e8cac9c1d5..2c8b64eeea8e 100644 --- a/arch/x86/virt/vmx/tdx/tdx.h +++ b/arch/x86/virt/vmx/tdx/tdx.h @@ -86,9 +86,6 @@ struct tdmr_info { DECLARE_FLEX_ARRAY(struct tdmr_reserved_area, reserved_areas); } __packed __aligned(TDMR_INFO_ALIGNMENT); =20 -/* Bit definitions of TDX_FEATURES0 metadata field */ -#define TDX_FEATURES0_NO_RBP_MOD BIT(18) - /* * Do not put any hardware-defined TDX structure representations below * this comment! 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Peter Anvin" Subject: [PATCH v8 17/21] x86/virt/seamldr: Abort updates on failure Date: Mon, 27 Apr 2026 08:28:11 -0700 Message-ID: <20260427152854.101171-18-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TDX module update is a multi-step process, and each step can fail. The current update flow continues to later steps after an error. Continuing after failure leaves the TDX module in an unrecoverable state. One failure case must remain recoverable: update contention with an ongoing TD build. The agreed kernel behavior for this case is to fail the update with -EBUSY so userspace can retry later. Abort the update on any failure. For the contention case, this provides a recoverable failure mode because the failure occurs before any TDX module state is changed. Use the same rule for all errors to avoid special-casing -EBUSY. Introduce a shared "failed" flag. When a CPU fails, set the flag and force all CPUs to exit the update loop. A failing CPU does not acknowledge the current step, so other CPUs remain at that step until they observe the "failed" flag and exit. Use READ_ONCE()/WRITE_ONCE() for the flag because it is used for lockless communication between stop_machine workers. Also use WRITE_ONCE() for the initial clear to keep accesses to the flag uniform and explicit. Signed-off-by: Chao Gao Reviewed-by: Xu Yilun Reviewed-by: Tony Lindgren Reviewed-by: Kai Huang Reviewed-by: Kiryl Shutsemau (Meta) --- v8: - Explain why aborting updates is necessary. [Rick] - always use READ_ONCE()/WRITE_ONCE() for the "failed" flag. --- arch/x86/virt/vmx/tdx/seamldr.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/x86/virt/vmx/tdx/seamldr.c b/arch/x86/virt/vmx/tdx/seamld= r.c index c81b26c4bac1..9b8f571eb03f 100644 --- a/arch/x86/virt/vmx/tdx/seamldr.c +++ b/arch/x86/virt/vmx/tdx/seamldr.c @@ -220,6 +220,7 @@ enum module_update_state { static struct { enum module_update_state state; int thread_ack; + bool failed; /* * Protect update_data. Raw spinlock as it will be acquired from * interrupt-disabled contexts. @@ -284,12 +285,15 @@ static int do_seamldr_install_module(void *seamldr_pa= rams) break; } =20 - ack_state(); + if (ret) + WRITE_ONCE(update_data.failed, true); + else + ack_state(); } else { touch_nmi_watchdog(); rcu_momentary_eqs(); } - } while (curstate !=3D MODULE_UPDATE_DONE); + } while (curstate !=3D MODULE_UPDATE_DONE && !READ_ONCE(update_data.faile= d)); =20 return ret; } @@ -315,6 +319,7 @@ int seamldr_install_module(const u8 *data, u32 size) =20 /* Ensure a stable set of online CPUs for the update process. */ guard(cpus_read_lock)(); + WRITE_ONCE(update_data.failed, false); set_target_state(MODULE_UPDATE_START + 1); ret =3D stop_machine_cpuslocked(do_seamldr_install_module, params, cpu_on= line_mask); if (ret) --=20 2.47.1 From nobody Wed Jun 17 06:18:36 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36F9A3D668E; Mon, 27 Apr 2026 15:30:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.20 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777303814; cv=none; b=GD8rgzcA4ukvkR1eCi+1MKLuFoz/9JiSgTcQ54FwGJqTaj+m3shCatKGpqstkNSx513wEcjcTQ4Du2HkCvkAisvKh3RyhkuLLIiH/iM3e77NnITrrHOp+Ar0ITLPR86Or3u5HprgolRjNtcrF+M/cwu5moOXOBb5cQClnuCKZWQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777303814; c=relaxed/simple; bh=oYaq4qw2SYfbSbF2xIIi8sE7DNKVVHZLZwNFEm/z1io=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uBD4OFadXj39MXCxneO5TDG5D5pjg/3IvqgJAqDJ+d0Oxp3VF5GFgjL9l/3Vtoie2O8Ofl/xB8r1hH07vkM7OS3W88OFOss5Liu/VyezgH+IKzlcYOR+IESULNviv7h/M7rbqI8JYy3hMCsbEENUvaH4Oe1MoaFsKnlmS7QuSf0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Yht/Px/p; arc=none smtp.client-ip=198.175.65.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Yht/Px/p" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777303811; x=1808839811; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oYaq4qw2SYfbSbF2xIIi8sE7DNKVVHZLZwNFEm/z1io=; b=Yht/Px/p0RHVVBga2jjMkhxFKS3VZ5rwd+rr3A0uSzmXkQjqECYmfAHa jDCH+ZFDA06VbsNalxrXFXjLmm9vw8LVU/Q6f8TPgPTL5X5Kc+FULxGX1 bqt1cwcdWCILg665ZDLjVHGoiTS/yZvkVzfnHTNW8E48gLqsbal5ZJJ9T 3OSejtmC2ZnSHyMZ6QAVjtROtRooc4LbJrmNrTbyz5oV6HayrHZSjiq52 1AqyTqJ5pK6B8EnkW5y7ceWw2ZpDD9r6+SmB4SHHku6/Zjmsd2qQ84ZO+ LP9QPLrTsp4ctSecauSjOIUco4q2bTVPjetuKGs4shggJBfiZlJ6d1PpY Q==; X-CSE-ConnectionGUID: i+JMdd+XQo22Y+IqvS6UTg== X-CSE-MsgGUID: Y7Tsppj9TXiXroQVQ/76TA== X-IronPort-AV: E=McAfee;i="6800,10657,11769"; a="77900806" X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="77900806" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:06 -0700 X-CSE-ConnectionGUID: y0Q8WY7iStmMX4uaqqiRYA== X-CSE-MsgGUID: c42cfKEBQiKZfreh4IQnkA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673350" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:06 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" Subject: [PATCH v8 18/21] coco/tdx-host: Don't expose P-SEAMLDR features on CPUs with erratum Date: Mon, 27 Apr 2026 08:28:12 -0700 Message-ID: <20260427152854.101171-19-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Some TDX-capable CPUs have an erratum, as documented in Intel=C2=AE Trust Domain CPU Architectural Extensions (May 2021 edition) Chapter 2.3: SEAMRET from the P-SEAMLDR clears the current VMCS structure pointed to by the current-VMCS pointer. A VMM that invokes the P-SEAMLDR using SEAMCALL must reload the current-VMCS, if required, using the VMPTRLD instruction. Clearing the current VMCS behind KVM's back will break KVM. This erratum is not present when IA32_VMX_BASIC[60] is set. Add a CPU bug bit for this erratum and refuse to expose P-SEAMLDR features (e.g., TDX module updates) on affected CPUs. =3D=3D Alternatives =3D=3D Two workarounds were considered but both were rejected: 1. Save/restore the current VMCS around P-SEAMLDR calls. This produces ugly assembly code [1] and doesn't play well with #MCE or #NMI if they need to use the current VMCS. 2. Move KVM's VMCS tracking logic to the TDX core code, which would break the boundary between KVM and the TDX core code [2]. Signed-off-by: Chao Gao Reviewed-by: Kai Huang Reviewed-by: Kiryl Shutsemau (Meta) Reviewed-by: Rick Edgecombe Link: https://lore.kernel.org/kvm/fedb3192-e68c-423c-93b2-a4dc2f964148@inte= l.com/ # [1] Link: https://lore.kernel.org/kvm/aYIXFmT-676oN6j0@google.com/ # [2] --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/vmx.h | 1 + arch/x86/virt/vmx/tdx/tdx.c | 11 +++++++++++ drivers/virt/coco/tdx-host/tdx-host.c | 8 ++++++++ 4 files changed, 21 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpuf= eatures.h index 1d506e5d6f46..7b572bc24265 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -573,4 +573,5 @@ #define X86_BUG_ITS_NATIVE_ONLY X86_BUG( 1*32+ 8) /* "its_native_only" CP= U is affected by ITS, VMX is not affected */ #define X86_BUG_TSA X86_BUG( 1*32+ 9) /* "tsa" CPU is affected by Transi= ent Scheduler Attacks */ #define X86_BUG_VMSCAPE X86_BUG( 1*32+10) /* "vmscape" CPU is affected b= y VMSCAPE attacks from guests */ +#define X86_BUG_SEAMRET_INVD_VMCS X86_BUG( 1*32+11) /* "seamret_invd_vmcs"= SEAMRET from P-SEAMLDR clears the current VMCS */ #endif /* _ASM_X86_CPUFEATURES_H */ diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h index 37080382df54..49d8551d285d 100644 --- a/arch/x86/include/asm/vmx.h +++ b/arch/x86/include/asm/vmx.h @@ -147,6 +147,7 @@ struct vmcs { #define VMX_BASIC_INOUT BIT_ULL(54) #define VMX_BASIC_TRUE_CTLS BIT_ULL(55) #define VMX_BASIC_NO_HW_ERROR_CODE_CC BIT_ULL(56) +#define VMX_BASIC_NO_SEAMRET_INVD_VMCS BIT_ULL(60) =20 static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic) { diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c index 7864ab68f4e3..23c5403b3691 100644 --- a/arch/x86/virt/vmx/tdx/tdx.c +++ b/arch/x86/virt/vmx/tdx/tdx.c @@ -41,6 +41,7 @@ #include #include #include +#include =20 #include "seamcall_internal.h" #include "tdx.h" @@ -1495,6 +1496,8 @@ static struct notifier_block tdx_memory_nb =3D { =20 static void __init check_tdx_erratum(void) { + u64 basic_msr; + /* * These CPUs have an erratum. A partial write from non-TD * software (e.g. via MOVNTI variants or UC/WC mapping) to TDX @@ -1506,6 +1509,14 @@ static void __init check_tdx_erratum(void) case INTEL_EMERALDRAPIDS_X: setup_force_cpu_bug(X86_BUG_TDX_PW_MCE); } + + /* + * Some TDX-capable CPUs have an erratum where the current VMCS is + * cleared after calling into P-SEAMLDR. + */ + rdmsrq(MSR_IA32_VMX_BASIC, basic_msr); + if (!(basic_msr & VMX_BASIC_NO_SEAMRET_INVD_VMCS)) + setup_force_cpu_bug(X86_BUG_SEAMRET_INVD_VMCS); } =20 void __init tdx_init(void) diff --git a/drivers/virt/coco/tdx-host/tdx-host.c b/drivers/virt/coco/tdx-= host/tdx-host.c index 14f861c03be4..24bd660ca2cd 100644 --- a/drivers/virt/coco/tdx-host/tdx-host.c +++ b/drivers/virt/coco/tdx-host/tdx-host.c @@ -92,6 +92,14 @@ static bool can_expose_seamldr(void) if (!sysinfo) return 0; =20 + /* + * Calling P-SEAMLDR on CPUs with the seamret_invd_vmcs bug clears + * the current VMCS, which breaks KVM. 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Peter Anvin" Subject: [PATCH v8 19/21] x86/virt/tdx: Enable TDX module runtime updates Date: Mon, 27 Apr 2026 08:28:13 -0700 Message-ID: <20260427152854.101171-20-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All pieces of TDX module runtime updates are in place. Enable it if it is supported. Signed-off-by: Chao Gao Reviewed-by: Xu Yilun Reviewed-by: Tony Lindgren Reviewed-by: Kiryl Shutsemau (Meta) Reviewed-by: Rick Edgecombe --- arch/x86/include/asm/tdx.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h index b063aabe2554..b9eb1da4f36c 100644 --- a/arch/x86/include/asm/tdx.h +++ b/arch/x86/include/asm/tdx.h @@ -36,6 +36,7 @@ #define TDX_UPDATE_COMPAT_SENSITIVE 0x8000051200000000ULL =20 /* Bit definitions of TDX_FEATURES0 metadata field */ +#define TDX_FEATURES0_TD_PRESERVING BIT_ULL(1) #define TDX_FEATURES0_NO_RBP_MOD BIT_ULL(18) #define TDX_FEATURES0_UPDATE_COMPAT BIT_ULL(47) =20 @@ -117,8 +118,7 @@ const struct tdx_sys_info *tdx_get_sysinfo(void); =20 static inline bool tdx_supports_runtime_update(const struct tdx_sys_info *= sysinfo) { - /* To be enabled when kernel is ready. */ - return false; + return sysinfo->features.tdx_features0 & TDX_FEATURES0_TD_PRESERVING; } =20 int tdx_guest_keyid_alloc(void); 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X-CSE-ConnectionGUID: dekbBNXvSPik/ktWqYAJHg== X-CSE-MsgGUID: ZLnTK606TOyjzm+tpt8Gug== X-IronPort-AV: E=McAfee;i="6800,10657,11769"; a="77900825" X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="77900825" Received: from orviesa006.jf.intel.com ([10.64.159.146]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:07 -0700 X-CSE-ConnectionGUID: MvDe03MAR3qRswU3bOMrnQ== X-CSE-MsgGUID: hpuV16JLTS2IP2iUAaMO8g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,202,1770624000"; d="scan'208";a="232673363" Received: from 984fee019967.jf.intel.com ([10.23.153.244]) by orviesa006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 08:30:07 -0700 From: Chao Gao To: kvm@vger.kernel.org, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, x86@kernel.org Cc: binbin.wu@linux.intel.com, dave.hansen@linux.intel.com, djbw@kernel.org, ira.weiny@intel.com, kai.huang@intel.com, kas@kernel.org, nik.borisov@suse.com, paulmck@kernel.org, pbonzini@redhat.com, reinette.chatre@intel.com, rick.p.edgecombe@intel.com, sagis@google.com, seanjc@google.com, tony.lindgren@linux.intel.com, vannapurve@google.com, vishal.l.verma@intel.com, yilun.xu@linux.intel.com, xiaoyao.li@intel.com, yan.y.zhao@intel.com, Chao Gao , Dan Williams Subject: [PATCH v8 20/21] coco/tdx-host: Document TDX module update compatibility criteria Date: Mon, 27 Apr 2026 08:28:14 -0700 Message-ID: <20260427152854.101171-21-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable The TDX module update protocol facilitates compatible runtime updates. Document the compatibility criteria and indicators of update failures. Note that runtime TDX module updates are an "update at your own risk" operation; userspace is responsible for ensureing that the update meets the compatibility criteria. Signed-off-by: Chao Gao Reviewed-by: Dan Williams Reviewed-by: Kiryl Shutsemau (Meta) --- v8: - Do not map -EIO and -ENOMEM to separate fw_upload errors. There is no current need to distinguish them in the userspace ABI, and fw_upload has no matching error code for -ENOMEM. - some wording changes. --- .../ABI/testing/sysfs-devices-faux-tdx-host | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-devices-faux-tdx-host b/Docume= ntation/ABI/testing/sysfs-devices-faux-tdx-host index 65897fe6abc0..ff585c79aa6e 100644 --- a/Documentation/ABI/testing/sysfs-devices-faux-tdx-host +++ b/Documentation/ABI/testing/sysfs-devices-faux-tdx-host @@ -26,3 +26,42 @@ Description: (RO) Report the number of remaining updates= . TDX maintains a See Intel=C2=AE Trust Domain Extensions - SEAM Loader (SEAMLDR) Interface Specification, Chapter "SEAMLDR_INFO" and Chapter "SEAMLDR.INSTALL" for more information. + +What: /sys/devices/faux/tdx_host/firmware/tdx_module +Contact: linux-coco@lists.linux.dev +Description: (Directory) The tdx_module directory implements the fw_upload + sysfs ABI, see Documentation/ABI/testing/sysfs-class-firmware + for the general description of the attributes @data, @cancel, + @error, @loading, @remaining_size, and @status. This ABI + facilitates "Compatible TDX module Updates". A compatible update + is one that meets the following criteria: + + Does not interrupt or interfere with any current TDX + operation or TD VM. + + Does not invalidate any previously consumed module metadata + values outside of the TEE_TCB_SVN_2 field (updated Security + Version Number) in TD Quotes. + + Does not require validation of new module metadata fields. By + implication, new module features and capabilities are only + available by installing the module at reboot (BIOS or EFI + helper loaded). + + See tdx_host/firmware/tdx_module/error for information on + update failure indicators. + +What: /sys/devices/faux/tdx_host/firmware/tdx_module/error +Contact: linux-coco@lists.linux.dev +Description: (RO) See Documentation/ABI/testing/sysfs-class-firmware for + baseline expectations for this file. The part in the + : format can be: + + "device-busy": The update conflicts with an in-progress TDX + operation. + + "firmware-invalid": The update failed for any other reason. + + A "firmware-invalid" result may be fatal. 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Peter Anvin" , Jonathan Corbet , Shuah Khan Subject: [PATCH v8 21/21] x86/virt/tdx: Document TDX module update Date: Mon, 27 Apr 2026 08:28:15 -0700 Message-ID: <20260427152854.101171-22-chao.gao@intel.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20260427152854.101171-1-chao.gao@intel.com> References: <20260427152854.101171-1-chao.gao@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document TDX module update as a subsection of "TDX Host Kernel Support" to provide background information and cover key points that developers and users may need to know, for example: - update is done in stop_machine() context - update instructions and results - update policy and tooling Signed-off-by: Chao Gao Reviewed-by: Kai Huang Reviewed-by: Kiryl Shutsemau (Meta) Reviewed-by: Rick Edgecombe --- Documentation/arch/x86/tdx.rst | 36 ++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/Documentation/arch/x86/tdx.rst b/Documentation/arch/x86/tdx.rst index ff6b110291bc..de6b99d9afa7 100644 --- a/Documentation/arch/x86/tdx.rst +++ b/Documentation/arch/x86/tdx.rst @@ -73,6 +73,42 @@ initialize:: =20 [..] virt/tdx: TDX-Module initialization failed ... =20 +TDX module Runtime Update +------------------------- + +The TDX architecture includes a persistent SEAM loader (P-SEAMLDR) that +runs in SEAM mode separately from the TDX module. The kernel can +communicate with P-SEAMLDR to perform runtime updates of the TDX module. + +During update, the TDX module becomes unresponsive to other TDX operations. +To prevent components using TDX (such as KVM) from experiencing unexpected +errors during updates, updates are performed in stop_machine() context. + +TDX module update has complex compatibility requirements; the new module +must be compatible with the current CPU, P-SEAMLDR, and running TDX module. +Rather than implementing complex module selection and policy enforcement +logic in the kernel, userspace is responsible for auditing and selecting +appropriate updates. + +Updates use the standard firmware upload interface. See +Documentation/driver-api/firmware/fw_upload.rst for detailed instructions. + +Successful updates are logged in dmesg: + [..] virt/tdx: version 1.5.20 -> 1.5.24 + +If updates failed, running TDs may be killed and further TDX operations may +not be possible until reboot. For detailed error information, see +Documentation/ABI/testing/sysfs-devices-faux-tdx-host. + +Given the risk of losing existing TDs, userspace should verify that the +update is compatible with the current system and properly validated before +applying it. + +A reference userspace tool that implements necessary checks is available +at: + + https://github.com/intel/tdx-module-binaries + TDX Interaction to Other Kernel Components ------------------------------------------ =20 --=20 2.47.1