From nobody Wed Jun 17 06:29:42 2026 Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D54A43B8BCC for ; Mon, 27 Apr 2026 11:28:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777289326; cv=none; b=TNBgjrC1Q8EUO+sUHOy2wChR0XzzXeElcuqk/o1+zCJj/iBsgs3KS6Thz29uYMujNpnTCig5dekwMsTJdrmVKb7wGX5aVNUZpG6Xss/cdZC+DeoaCDTBUcQYVlIvImSo3gVVd5BXyZiJktMV5YyCjnNn0sSZ2ihFq1yXMVRIR/Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777289326; c=relaxed/simple; bh=604GKGZ2LMBnNnG2sD7aHeVbMINZqCZkzgKWWG7wcBQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=MPIiCBVyvyhf9fAXdSzYmFsRqLuH0c5hk9EbYPZ1mv8B3LBWyWAGh2uN8UXOGT1/NhtAcj/Y5ndhUizUiomGB+6VJSg8WLF1go89N9rOQ83cFgsFrOKjYTAZY67fJQnITdO1lN3NQXyVTCWdI4oGWHqoDac7SOTd+Hy6k/zS424= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=j22EKtWh; arc=none smtp.client-ip=209.85.221.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="j22EKtWh" Received: by mail-wr1-f53.google.com with SMTP id ffacd0b85a97d-445795cf6f1so289931f8f.1 for ; Mon, 27 Apr 2026 04:28:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777289322; x=1777894122; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=03jq2FOnuh9qmdwhdZ2J0ZBVYWSyNXvDV4qpUXfZIHI=; b=j22EKtWh/OugspcOI2gbsnLWX7iyQnImVF5OgG1uuVvtR5FlsPNaUlv7xpZmMTwNRs uXOjWYR0LblsbWjhhM4i9sQYAeGAhjeuMlGoXbtMRdU42TMCexb5XrWXF2GWt65821jN HfZf3v6rsnnpsy8zOMlLoBpOwZILG6HwNy9F/XHD9TZfCJ+rZ/d4mKxeSN/CXnf+bJof xa3sA/WV4U4Ed9KA/Cw33VE0Ae0Nkuc/wqYqoKWZIZrzWJjSrxX1GClRr4rTh5sW5zLS ALgGAZX+IYjl1fT8+Aga/lxmdYpYtnYZ7CGjotk/9LbxHjh7SQoAvxkndzpmeY7XAq86 2oIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777289322; x=1777894122; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=03jq2FOnuh9qmdwhdZ2J0ZBVYWSyNXvDV4qpUXfZIHI=; b=jnaIE53GRhMM4kjo5VDJ4W5boV6itdCOefqZXMwqXtiQ9TFYZBe/4M8xCltMcPvtku sns/n/IQquscndqE0jOhVMIxHPxLaaJ/aVXZudqxMOtH3WS7exxGcr6On+wNGP4kWK1H O5eVIe6idXiF+ibPAuWB8p9NwhooxWiW/F6v7qWK41JQQxLJSDdBik2QbFQkpycc7BhO S6ttlxf5H7PUwqHklXqtpVKzEX6SOHJ1uNYGryz1pUa2tos1NeOgcB8E90GSh3h8o6Zm chxKPDfM9zB8gyBveGvUnPIgrJtwq1gaefOyfUqfTJ8KzDQuKAWbN/UlTuUUnpTAt8a9 UsRA== X-Gm-Message-State: AOJu0YylmQszdo9KnE8u4wAdjshpPHud7g6YRaOsG1HJl+BiRJ69qtv/ maDnBOgTn17sen5vkyO2E5Wk0W9UgcYn4Np/pd4YkEEVyI77FlZP/Dsa X-Gm-Gg: AeBDieuYwmzVdZviItB4/FJF+DaNvC+LSOR5wZEROkYDzErthc9fNKT0QEDJrNjaVzp ek1iK6Vr3lABAaPxg/d+5MJZjBxmugyOMYhhq2YF+V65LVpmKcQ8s2WrNnJzisErbbjQhgwh9ta FW9G/cR1B3KiDz9Io7dJ50NuimDtZ5XRhOGA5W5M0Zs4aFUzu2dhU2CSW7EKH0VBtxHnT+EDDZX W533rX+ja6Olz8gqwCn4+AjCqfOZOeYZudBotTG0HQgfh3jRokgLThmYTBd1A6HqyKXyDlBSZFi FHwmbLpzds4Irqd2e9uHg9+bXTB4jjySbZlQM7X9YBergfGgIlNU3JROS0nWYCCFRohTpYsGUW0 lII6wRVe5RiQ0PD0QYThnhorN3x9GQBsALdxzXBFK5ifiw+fumDRbRWpidoB+5jlJCW6tpvhI8v iLnzp6pnRP/TKyLvQwCVL2Ljrz6RK4lmIGyE8yuu3O4/KBjmalTa43RCA4d2+uXTghf3c3gAyHc UgFxjBCL81c9uYxQv9gH6OUdLgoVxvrDDmKgqT3y5B2vbNpUOVC0O2Tyw== X-Received: by 2002:a05:6000:2307:b0:43b:3e40:2223 with SMTP id ffacd0b85a97d-43fe3dcc52cmr67755277f8f.19.1777289322002; Mon, 27 Apr 2026 04:28:42 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:3f97:a47d:8f30:c055]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43fe4cb135asm85759519f8f.6.2026.04.27.04.28.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 04:28:41 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Michael Turquette , Stephen Boyd , Brian Masney , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 1/2] clk: divider: Add KUnit tests for clk_divider_bestdiv() ULONG_MAX handling Date: Mon, 27 Apr 2026 12:28:23 +0100 Message-ID: <20260427112824.231150-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260427112824.231150-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260427112824.231150-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add KUnit tests to verify the behaviour of clk_divider_bestdiv() when clk_round_rate() is called with ULONG_MAX, which is the canonical way to probe the maximum rate a clock can produce. Two test cases are introduced: - clk_divider_bestdiv_ulong_max_returns_max_rate: registers a 1 GHz fixed-rate parent driving a table-based divider whose smallest entry is div=3D2 (entries: 2, 4, 8). Calls clk_hw_round_rate(div_hw, ULONG_MAX) and checks the result. - clk_divider_bestdiv_mux_ulong_max_returns_max_rate: places a two-input mux (4 GHz and 2 GHz fixed-rate parents, CLK_SET_RATE_PARENT) ahead of the same table-based divider to verify correct parent selection under ULONG_MAX. Both tests use an explicit clk_div_table with a minimum divider of 2 so that the pre-loop maxdiv clamping in clk_divider_bestdiv(): maxdiv =3D min(ULONG_MAX / rate, maxdiv); clamps maxdiv to 1, causing _next_div() to return 2 on the first iteration and skip the loop body entirely. This makes bestdiv fall back to the maximum divider, returning the minimum rate rather than the maximum. The expected values intentionally reflect the buggy output: - test 1: PARENT_RATE_1GHZ / 8 (minimum rate, not maximum) - test 2: 0 (invalid, loop never populated bestdiv) These will be corrected to PARENT_RATE_1GHZ / 2 and PARENT_RATE_4GHZ / 2 respectively once the fix to clk_divider_bestdiv() is applied. Signed-off-by: Lad Prabhakar Reviewed-by: Brian Masney --- v3->v4: - Dropped unregister_fixed_rate/unregister_divider/unregister_mux wrapper - Added entry in .kunitconfig file - Fixed reverse christmas tree order in clk_divider_bestdiv_ulong_max_returns_max_rate - Updated MODULE_DESCRIPTION() to be more specific v2->v3: - Added false positive expected values - Updated the commit message - Added dependency on !S390 in Kconfig --- drivers/clk/.kunitconfig | 1 + drivers/clk/Kconfig | 8 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-divider_test.c | 152 +++++++++++++++++++++++++++++++++ 4 files changed, 162 insertions(+) create mode 100644 drivers/clk/clk-divider_test.c diff --git a/drivers/clk/.kunitconfig b/drivers/clk/.kunitconfig index 8a0ea41934a2..ea05b9a28c80 100644 --- a/drivers/clk/.kunitconfig +++ b/drivers/clk/.kunitconfig @@ -4,6 +4,7 @@ CONFIG_OF=3Dy CONFIG_OF_OVERLAY=3Dy CONFIG_COMMON_CLK=3Dy CONFIG_CLK_KUNIT_TEST=3Dy +CONFIG_CLK_DIVIDER_KUNIT_TEST=3Dy CONFIG_CLK_FIXED_RATE_KUNIT_TEST=3Dy CONFIG_CLK_GATE_KUNIT_TEST=3Dy CONFIG_CLK_FD_KUNIT_TEST=3Dy diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index b2efbe9f6acb..fdeb87ff8fd9 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -573,4 +573,12 @@ config CLK_FD_KUNIT_TEST help Kunit test for the clk-fractional-divider type. =20 +config CLK_DIVIDER_KUNIT_TEST + tristate "KUnit tests for clk divider bestdiv" if !KUNIT_ALL_TESTS + depends on KUNIT + depends on !S390 + default KUNIT_ALL_TESTS + help + Kunit test for the clk-divider type. + endif diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index a3e2862ebd7e..dc653b458f56 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -21,6 +21,7 @@ clk-test-y :=3D clk_test.o \ kunit_clk_hw_get_dev_of_node.dtbo.o \ kunit_clk_parent_data_test.dtbo.o obj-$(CONFIG_COMMON_CLK) +=3D clk-divider.o +obj-$(CONFIG_CLK_DIVIDER_KUNIT_TEST) +=3D clk-divider_test.o obj-$(CONFIG_COMMON_CLK) +=3D clk-fixed-factor.o obj-$(CONFIG_COMMON_CLK) +=3D clk-fixed-rate.o obj-$(CONFIG_CLK_FIXED_RATE_KUNIT_TEST) +=3D clk-fixed-rate-test.o diff --git a/drivers/clk/clk-divider_test.c b/drivers/clk/clk-divider_test.c new file mode 100644 index 000000000000..b1bc802f38e4 --- /dev/null +++ b/drivers/clk/clk-divider_test.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * KUnit tests for clk_divider_bestdiv() + */ +#include +#include +#include +#include +#include + +#define PARENT_RATE_1GHZ GIGA +#define PARENT_RATE_2GHZ (2 * GIGA) +#define PARENT_RATE_4GHZ (4 * GIGA) + +static const struct clk_div_table bestdiv_table[] =3D { + { .val =3D 0, .div =3D 2 }, + { .val =3D 1, .div =3D 4 }, + { .val =3D 2, .div =3D 8 }, + { /* sentinel */ } +}; + +/* + * Test that clk_round_rate(clk, ULONG_MAX) returns the maximum achievable + * rate for a divider clock. + */ +static void clk_divider_bestdiv_ulong_max_returns_max_rate(struct kunit *t= est) +{ + struct clk_hw *parent_hw, *div_hw; + unsigned long rate; + u32 *fake_reg; + + fake_reg =3D kunit_kzalloc(test, sizeof(*fake_reg), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, fake_reg); + + parent_hw =3D clk_hw_register_fixed_rate(NULL, "bestdiv-parent", + NULL, 0, PARENT_RATE_1GHZ); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent_hw); + KUNIT_ASSERT_EQ(test, 0, + kunit_add_action_or_reset(test, + (kunit_action_t *)clk_hw_unregister_fixed_rate, + parent_hw)); + + div_hw =3D clk_hw_register_divider_table(NULL, "bestdiv-div", + "bestdiv-parent", + CLK_SET_RATE_PARENT, + (void __iomem __force *)fake_reg, + 0, 2, 0, bestdiv_table, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, div_hw); + KUNIT_ASSERT_EQ(test, 0, + kunit_add_action_or_reset(test, + (kunit_action_t *)clk_hw_unregister_divider, + div_hw)); + + /* + * ULONG_MAX is the canonical way to probe the maximum rate a clock + * can produce. + */ + rate =3D clk_hw_round_rate(div_hw, ULONG_MAX); + KUNIT_EXPECT_EQ(test, rate, PARENT_RATE_1GHZ / 8); +} + +/* + * Test that clk_round_rate(clk, ULONG_MAX) returns the correct maximum ra= te + * when a mux clock sits between a divider and its parent candidates. + * + * Topology: + * + * [fixed 4 GHz] --\ + * +--> [mux CLK_SET_RATE_PARENT] --> [div {2,4,8} CLK_= SET_RATE_PARENT] + * [fixed 2 GHz] --/ + * + */ +static void clk_divider_bestdiv_mux_ulong_max_returns_max_rate(struct kuni= t *test) +{ + static const char * const mux_parents[] =3D { + "bestdiv-mux-parent-a", + "bestdiv-mux-parent-b", + }; + struct clk_hw *parent_a_hw, *parent_b_hw, *mux_hw, *div_hw; + u32 *fake_reg_mux, *fake_reg_div; + unsigned long rate; + + fake_reg_mux =3D kunit_kzalloc(test, sizeof(*fake_reg_mux), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, fake_reg_mux); + + fake_reg_div =3D kunit_kzalloc(test, sizeof(*fake_reg_div), GFP_KERNEL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, fake_reg_div); + + /* Higher-rate parent: the mux should select this for ULONG_MAX. */ + parent_a_hw =3D clk_hw_register_fixed_rate(NULL, "bestdiv-mux-parent-a", + NULL, 0, PARENT_RATE_4GHZ); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent_a_hw); + KUNIT_ASSERT_EQ(test, 0, + kunit_add_action_or_reset(test, + (kunit_action_t *)clk_hw_unregister_fixed_rate, + parent_a_hw)); + + /* Lower-rate parent: should not be selected. */ + parent_b_hw =3D clk_hw_register_fixed_rate(NULL, "bestdiv-mux-parent-b", + NULL, 0, PARENT_RATE_2GHZ); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, parent_b_hw); + KUNIT_ASSERT_EQ(test, 0, + kunit_add_action_or_reset(test, + (kunit_action_t *)clk_hw_unregister_fixed_rate, + parent_b_hw)); + + /* + * 1-bit mux register selects between the two parents. + * CLK_SET_RATE_PARENT allows the divider's rate request to + * propagate into clk_mux_determine_rate(). + */ + mux_hw =3D clk_hw_register_mux(NULL, "bestdiv-mux", + mux_parents, ARRAY_SIZE(mux_parents), + CLK_SET_RATE_PARENT, + (void __iomem __force *)fake_reg_mux, + 0, 1, 0, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, mux_hw); + KUNIT_ASSERT_EQ(test, 0, + kunit_add_action_or_reset(test, + (kunit_action_t *)clk_hw_unregister_mux, + mux_hw)); + + div_hw =3D clk_hw_register_divider_table(NULL, "bestdiv-mux-div", + "bestdiv-mux", + CLK_SET_RATE_PARENT, + (void __iomem __force *)fake_reg_div, + 0, 2, 0, bestdiv_table, NULL); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, div_hw); + KUNIT_ASSERT_EQ(test, 0, + kunit_add_action_or_reset(test, + (kunit_action_t *)clk_hw_unregister_divider, + div_hw)); + + rate =3D clk_hw_round_rate(div_hw, ULONG_MAX); + KUNIT_EXPECT_EQ(test, rate, 0); +} + +static struct kunit_case clk_divider_bestdiv_test_cases[] =3D { + KUNIT_CASE(clk_divider_bestdiv_ulong_max_returns_max_rate), + KUNIT_CASE(clk_divider_bestdiv_mux_ulong_max_returns_max_rate), + {} +}; + +static struct kunit_suite clk_divider_bestdiv_test_suite =3D { + .name =3D "clk_divider_bestdiv", + .test_cases =3D clk_divider_bestdiv_test_cases, +}; + +kunit_test_suite(clk_divider_bestdiv_test_suite); + +MODULE_DESCRIPTION("KUnit tests for clk divider"); +MODULE_LICENSE("GPL"); --=20 2.54.0 From nobody Wed Jun 17 06:29:42 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 851973B7B9D for ; Mon, 27 Apr 2026 11:28:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777289326; cv=none; b=lXqNLziY2r3grOcXxJq/3FIDmrpLQmwwTFLccJOcV4JlIGmPaGVSY22XmCuJ1U21APT/LMbgeQiJBVPDXhrTo6Mlvt2hG/Vt1XmYXnVnCgeBluDhmHvnWGrBzFWBFsfZtuL3KB/5wp7+HjLHzrXYdnY8GYB9d+hEKZhMyjynEYU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777289326; c=relaxed/simple; bh=h7uIE0mqqq4mHL5t/tYzDztinxFslRwHMvJ3tdF+6q0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UZ94v8/JdUFedVX0yJlO+7aahJr2AVgdBK8a/9jFw8p354Zn1tgTFwD4qhlo/Py7IHnNBlFBVj6nfocqoTrwKkpGDFjHWXmUP1W7FPozzfhB6c7lpH4A0soM1cNoLJUix+52GSrixPvOjYRzhCrob8r2BDOVJIjWEVxkuB2dIO0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NH6KkKX6; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NH6KkKX6" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-4891e86fabeso110088255e9.1 for ; Mon, 27 Apr 2026 04:28:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1777289323; x=1777894123; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wCeqg+kQQc+bo4zJQuFR7vpp5utJVCWYM9xfYQe2WTM=; b=NH6KkKX6BTIxhRBg87mLl7vZkvyYVrP0ahuVj98Zu8/Q36G6sgjoBGVqA32qEskxdR x9e8MecXYft6GeGtWLMJikwkZSVC0zxO/pqKwu8AL+zeuInbRrnVDN/v0pLpF9AjfUC4 w7kDHnxsVx7fQPG4z0o34R2eBSYaTgzqaAjOTPhU6JOXoMdkcVdCmpRs97iFlpjkfuc9 3Hd+Y5P8JcKJ1J5XezUMmSdRbqIdaNQ74ZX+ZYWmh7G47iEK5yyHe/pkHv8sJHbZLP1k VspAS/1v7EOzVPrHDjjA99jbis9P616bp4Ue60VlFT9ezFYwyWOJ3gGgQpvnQpTbQBZn ga+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777289323; x=1777894123; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=wCeqg+kQQc+bo4zJQuFR7vpp5utJVCWYM9xfYQe2WTM=; b=tKbpV/gIfTq7wkeYMjDt3ewTMG+6sOueNW4EGYbmua4GCNSOTKzo0o6MQ9xmLMR45m 7frNlOgbaBFS2yKzMBaER/DhO8ZVyes3N/LMzLR+bjiVIRZ+/U2kw0ubWM+1uGxgTULE QnVb6d0lY1is4CzkaFlSKAXVhlrvo6lhEl2CFFRS0Zdq+8JtQ4y/f9GPefNRtSWg2gWs WMHjFbY6E7ykLE7wqlek/h8BHmHX+OWr5ptJI/UHwkODWkyzHawuwiEZ/G5nSxyQsavu feORKFqd3imh4OUs22x6SeF0d+DcWoxpbulEL559fPkmeqqEkwlfq0H5U/jNHeT4AN8K Lcvw== X-Gm-Message-State: AOJu0YzPoYY9FCJYBJszHMF3o5WYuVu1ES/1Rj6Ymm3W/h6xYJjczj5V GTp+sAWN1yoU79TO5twhXLfrP45fsrExwKCiCyMqEJsyTVlnrmffNn5Q X-Gm-Gg: AeBDieu5XPBX+Xf9ig36536DfH02CCFvGFs8o/wJe31hCo17IwGDPFrJFRuzMCtfYUK ZiyqE3PP36Qhr/G0/c3wBRogwarCoeW5HCYOX29yODNKEqlC6QRGv8XmobpMdJGFOV+3uXZnVO9 MuJsillMArMU9aOO43NoelNUUjg6gx5pP+muH3HUnM138IGTktDH54VnyVGFPxGSdatdLtP6h89 XNneh7TjqrHP72Ya3YIfyZ0zx4VvFmfmmTcnHo422MOpHjKbf/dTYJ2vZyGWQCSIhJvUqc6wR6U JVCxcwo1mc+P084XEuE2WqWM3L/nioOYjBKbnuvTjJCGpTouvv4W7fIjCXoYykWxXLqZXycrR/f w5DEmVEe9VXXzrfTy8OVFDTQdfm5Pv02IyQKvL8lifp6+cX90Ie+0H86BeJ0HhNCYCjuI7EOoHC d94z7BRrpLQmdbDrYzxeWSN2WIZNq/nTseFIEBtX0E78vra+OBfKod9lK7pB2Yw6oJ1HbyKhM6e NKEzfs/GU78rhpVpiPvXfa5yB0QVJNs79MyI2C4qmpJE1czj7wBC4VCPfEozNWyTMB2 X-Received: by 2002:a05:6000:2886:b0:43d:500a:1e5c with SMTP id ffacd0b85a97d-43fe3e0dc92mr65324143f8f.26.1777289322784; Mon, 27 Apr 2026 04:28:42 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:3f97:a47d:8f30:c055]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43fe4cb135asm85759519f8f.6.2026.04.27.04.28.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 04:28:42 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Michael Turquette , Stephen Boyd , Brian Masney , Geert Uytterhoeven Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 2/2] clk: divider: Fix clk_divider_bestdiv() returning min rate for large rate requests Date: Mon, 27 Apr 2026 12:28:24 +0100 Message-ID: <20260427112824.231150-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260427112824.231150-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20260427112824.231150-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar clk_divider_bestdiv() clamps maxdiv using: maxdiv =3D min(ULONG_MAX / rate, maxdiv); to avoid overflow in rate * i. However, requests like clk_round_rate(clk, ULONG_MAX), which are used to determine the maximum supported rate of a clock, result in maxdiv being clamped to 1. If no valid divider of 1 exists in the table the loop is never entered and bestdiv falls back to the maximum divider with the minimum parent rate, causing clk_round_rate(clk, ULONG_MAX) to incorrectly return the minimum supported rate instead of the maximum. Fix this by removing the pre-loop maxdiv clamping and replacing the unprotected rate * i multiplication with check_mul_overflow(). Guard the exact-match short-circuit with !overflow to prevent a clamped target_parent_rate of ULONG_MAX from falsely matching parent_rate_saved and causing premature loop exit. Break out of the loop after evaluating the first overflowing divider since clk_hw_round_rate(parent, ULONG_MAX) returns a constant for all subsequent iterations, meaning no better candidate can be found, and continuing would cause exponential recursive calls in chained divider clocks. Update the KUnit test expected values to reflect the corrected behaviour: - clk_divider_bestdiv_ulong_max_returns_max_rate: PARENT_RATE_1GHZ / 8 (minimum rate, pre-fix) -> PARENT_RATE_1GHZ / 2 (maximum rate) - clk_divider_bestdiv_mux_ulong_max_returns_max_rate: 0 (invalid, pre-fix) -> PARENT_RATE_4GHZ / 2 (maximum rate with mux selecting the 4 GHz parent and applying the smallest table divider of 2) Signed-off-by: Lad Prabhakar Reviewed-by: Brian Masney --- v3->v4: - No change v2->v3: - Added Rb tag - Added the expected value for the tests - updated the commit message --- drivers/clk/clk-divider.c | 25 +++++++++++++++++-------- drivers/clk/clk-divider_test.c | 4 ++-- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index c3804bbc06f9..36bfaf7200e2 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 /* * DOC: basic adjustable divider clock that cannot gate @@ -301,6 +302,7 @@ static int clk_divider_bestdiv(struct clk_hw *hw, struc= t clk_hw *parent, int i, bestdiv =3D 0; unsigned long parent_rate, best =3D 0, now, maxdiv; unsigned long parent_rate_saved =3D *best_parent_rate; + unsigned long target_parent_rate; =20 if (!rate) rate =3D 1; @@ -315,15 +317,11 @@ static int clk_divider_bestdiv(struct clk_hw *hw, str= uct clk_hw *parent, return bestdiv; } =20 - /* - * The maximum divider we can use without overflowing - * unsigned long in rate * i below - */ - maxdiv =3D min(ULONG_MAX / rate, maxdiv); - for (i =3D _next_div(table, 0, flags); i <=3D maxdiv; i =3D _next_div(table, i, flags)) { - if (rate * i =3D=3D parent_rate_saved) { + bool overflow =3D check_mul_overflow(rate, (unsigned long)i, &target_par= ent_rate); + + if (!overflow && target_parent_rate =3D=3D parent_rate_saved) { /* * It's the most ideal case if the requested rate can be * divided from parent clock without needing to change @@ -332,13 +330,24 @@ static int clk_divider_bestdiv(struct clk_hw *hw, str= uct clk_hw *parent, *best_parent_rate =3D parent_rate_saved; return i; } - parent_rate =3D clk_hw_round_rate(parent, rate * i); + /* + * Clamp target_parent_rate to ULONG_MAX on overflow. The true + * required parent rate exceeds what can be represented, so ask + * the parent for the highest rate it can produce. There is no + * point continuing the loop past this since larger dividers + * only move further from the requested rate. + */ + if (overflow) + target_parent_rate =3D ULONG_MAX; + parent_rate =3D clk_hw_round_rate(parent, target_parent_rate); now =3D DIV_ROUND_UP_ULL((u64)parent_rate, i); if (_is_best_div(rate, now, best, flags)) { bestdiv =3D i; best =3D now; *best_parent_rate =3D parent_rate; } + if (overflow) + break; } =20 if (!bestdiv) { diff --git a/drivers/clk/clk-divider_test.c b/drivers/clk/clk-divider_test.c index b1bc802f38e4..093399c06467 100644 --- a/drivers/clk/clk-divider_test.c +++ b/drivers/clk/clk-divider_test.c @@ -56,7 +56,7 @@ static void clk_divider_bestdiv_ulong_max_returns_max_rat= e(struct kunit *test) * can produce. */ rate =3D clk_hw_round_rate(div_hw, ULONG_MAX); - KUNIT_EXPECT_EQ(test, rate, PARENT_RATE_1GHZ / 8); + KUNIT_EXPECT_EQ(test, rate, PARENT_RATE_1GHZ / 2); } =20 /* @@ -132,7 +132,7 @@ static void clk_divider_bestdiv_mux_ulong_max_returns_m= ax_rate(struct kunit *tes div_hw)); =20 rate =3D clk_hw_round_rate(div_hw, ULONG_MAX); - KUNIT_EXPECT_EQ(test, rate, 0); + KUNIT_EXPECT_EQ(test, rate, PARENT_RATE_4GHZ / 2); } =20 static struct kunit_case clk_divider_bestdiv_test_cases[] =3D { --=20 2.54.0