From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DCEAE3B3BF1; Mon, 27 Apr 2026 09:56:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283800; cv=none; b=G0aWOAguBEx4IAJHvfpfaPhO7KaTqWdtHMy1kkk5A3SRvAB9WDzMQbNDRk6QALOj7qriDQhZ7KKQ2SZgngJh5xX6uDI+rO+gR867s5K0XMOzycRt0eaDkXJGQvYZsWahZhaDz4vk1t+qzNbBI1Wun1K3v0XN8TeJ291BGk8wgQQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283800; c=relaxed/simple; bh=Vjf/+W6X2o66/p4JzdVpEIdyl1g7SDuTTeHJJ8c4c3c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bh89LjsS0fyEoNdzMrl6YeN+Z1JcBunAMbQcmtuKaIWPJUI7/RyiKJpnDseSDShN4afW+6aWQHWNUmOYCt7FwwQo8F6IdUww+6s9F2F151Wr25GAVqqM1q+lo/BvTN8+Jfp4ziEWafMx7+hZdGOAtDxahvVBe9ZBNIEv31CB+Is= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cIvBmmoW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cIvBmmoW" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 10397C19425; Mon, 27 Apr 2026 09:56:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777283800; bh=Vjf/+W6X2o66/p4JzdVpEIdyl1g7SDuTTeHJJ8c4c3c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cIvBmmoWC4ilkf4onLtk1RY6WIe+m6DAizvAuPwSB0lEO8+ZPvYQInQCDIAS79N7X JyrYREaURcugcD0kLj1b5DNLMq/vnTYHtxEk5WqR46jndRF48LRK/Wgx54xAAg1bmt awVYnSWneL2LiVm+BfhWs4C9PLPyaZlFK7GHDMZo1B8aRy9yeXALulLykdOgZ0VkkW QyyRfd3i6sZwx8M25NZ/p2UbKS2TWyebfUukIipYnekeFsOF/bzCIcrW+D9wSob12b wB+au19OqxM3fyBTbEinuskD/HXsSk4KbHZeca+5YvT+AjF72D1PTSOS1hU6qIDyrb fCCCaHW9o/EKw== From: Sumit Garg To: andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v4 01/15] arm64: dts: qcom: kodiak: Add EL2 overlay Date: Mon, 27 Apr 2026 15:25:49 +0530 Message-ID: <20260427095603.1157963-2-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260427095603.1157963-1-sumit.garg@kernel.org> References: <20260427095603.1157963-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Mukesh Ojha All the existing variants Kodiak boards are using Gunyah hypervisor which means that, so far, Linux-based OS could only boot in EL1 on those devices. However, it is possible for us to boot Linux at EL2 on these devices [1]. When running under Gunyah, the remote processor firmware IOMMU streams are controlled by Gunyah. However, without Gunyah, the IOMMU is managed by the consumer of this DeviceTree. Therefore, describe the firmware streams for each remote processor. Add a EL2-specific DT overlay and apply it to Kodiak IOT variant devices to create -el2.dtb for each of them alongside "normal" dtb. [1] https://docs.qualcomm.com/bundle/publicresource/topics/80-70020-4/boot-deve= loper-touchpoints.html#uefi Signed-off-by: Mukesh Ojha [SG: watchdog fixup] Signed-off-by: Sumit Garg Tested-by: Mukesh Ojha # Lemans --- arch/arm64/boot/dts/qcom/Makefile | 2 ++ arch/arm64/boot/dts/qcom/kodiak-el2.dtso | 35 ++++++++++++++++++++++++ 2 files changed, 37 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/kodiak-el2.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/M= akefile index 4ba8e7306419..28123cdc9de2 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -170,6 +170,8 @@ qcs615-ride-el2-dtbs :=3D qcs615-ride.dtb talos-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) +=3D qcs615-ride-el2.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-radxa-dragon-q6a.dtb dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-rb3gen2.dtb +qcs6490-rb3gen2-el2-dtbs :=3D qcs6490-rb3gen2.dtb kodiak-el2.dtbo +dtb-$(CONFIG_ARCH_QCOM) +=3D qcs6490-rb3gen2-el2.dtb =20 qcs6490-rb3gen2-vision-mezzanine-dtbs :=3D qcs6490-rb3gen2.dtb qcs6490-rb3= gen2-vision-mezzanine.dtbo qcs6490-rb3gen2-industrial-mezzanine-dtbs :=3D qcs6490-rb3gen2.dtb qcs6490= -rb3gen2-industrial-mezzanine.dtbo diff --git a/arch/arm64/boot/dts/qcom/kodiak-el2.dtso b/arch/arm64/boot/dts= /qcom/kodiak-el2.dtso new file mode 100644 index 000000000000..0b3a69a0d765 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/kodiak-el2.dtso @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + * Kodiak specific modifications required to boot in EL2. + */ + + +/dts-v1/; +/plugin/; + +&gpu_zap_shader { + status =3D "disabled"; +}; + +&remoteproc_adsp { + iommus =3D <&apps_smmu 0x1800 0x0>; +}; + +&remoteproc_cdsp { + iommus =3D <&apps_smmu 0x11a0 0x0400>; +}; + +&remoteproc_wpss { + iommus =3D <&apps_smmu 0x1c03 0x1>, + <&apps_smmu 0x1c83 0x1>; +}; + +&venus { + status =3D "disabled"; +}; + +&watchdog { + status =3D "okay"; +}; --=20 2.51.0 From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 720F33B3BF2; Mon, 27 Apr 2026 09:56:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283815; cv=none; b=hFiHpKsNuw/ryc3dil5vqylpUdjV++vfrGeF+rF4+tyjl0rDfCJcBSzjC/mSaF+hmNh8J6Unsg0OTFsCK+l7WEQ2wNEmY/4fZ54EmARt8UQsIwEjjQOrwg3yJk+9qmxxovfAdjGaQFWhWnROCTlEPog3YJc2saYqtOVJmFpE2kw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283815; c=relaxed/simple; bh=6gVNfGmS2oSWVHiem7W6EixlqbPCAbMEFqVrdvxtapA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qLLc9a4BhKkvrJ/eGgHBekm6PDts5AsQoatuWMPKx6gVyCfyF4+m+iU5OnbGbVAAvCeHz5XLjeVxb12TBPpqza2LDgGVh/93OH2zNs9lfGME9W+W5TRknEy171/OiDxtWCmlw1s+PJ7b8z/38SUkShC4xEZ/SNvmYKHXYgkb8lE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DjGko5rL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DjGko5rL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52573C2BCC4; Mon, 27 Apr 2026 09:56:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777283815; bh=6gVNfGmS2oSWVHiem7W6EixlqbPCAbMEFqVrdvxtapA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DjGko5rLOzmZukai6NYZ5FzDeJqJvbZU9rm1acbFW4BytNClUkwiOYvTyHao4ivNS gqHfM1K/OQyB97unNiiD7n8gW8ibQg7etnO5nckdkS4Yj4nBqff+NkAnKRXsCJT5AW u3f3HkWVCqpUKNvHMP54mhdPastueqFmRibHYHkjw0KF5fADJA5hisV4tSltMj4SEL ATyMN2nV497DrzI4olr0yGQFgQ4cl7NzMPWB73i2mALkigFr2Bto70Ll/LUK0EeCRq F6jKNVDXJb8n08PQlL+uRH+tEEmI7YL9CyvL0XuIfZcp7qU0us+stlHhJvP26V6+CU ovva2CxbvTWrw== From: Sumit Garg To: andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v4 02/15] firmware: qcom: Add a generic PAS service Date: Mon, 27 Apr 2026 15:25:50 +0530 Message-ID: <20260427095603.1157963-3-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260427095603.1157963-1-sumit.garg@kernel.org> References: <20260427095603.1157963-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Qcom platforms has the legacy of using non-standard SCM calls splintered over the various kernel drivers. These SCM calls aren't compliant with the standard SMC calling conventions which is a prerequisite to enable migration to the FF-A specifications from Arm. OP-TEE as an alternative trusted OS to Qualcomm TEE (QTEE) can't support these non-standard SCM calls. And even for newer architectures using S-EL2 with Hafnium support, QTEE won't be able to support SCM calls either with FF-A requirements coming in. And with both OP-TEE and QTEE drivers well integrated in the TEE subsystem, it makes further sense to reuse the TEE bus client drivers infrastructure. The added benefit of TEE bus infrastructure is that there is support for discoverable/enumerable services. With that client drivers don't have to manually invoke a special SCM call to know the service status. So enable the generic Peripheral Authentication Service (PAS) provided by the firmware. It acts as the common layer with different TZ backends plugged in whether it's an SCM implementation or a proper TEE bus based PAS service implementation. Signed-off-by: Sumit Garg Reviewed-by: Harshal Dev Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans --- drivers/firmware/qcom/Kconfig | 8 + drivers/firmware/qcom/Makefile | 1 + drivers/firmware/qcom/qcom_pas.c | 288 +++++++++++++++++++++++++ drivers/firmware/qcom/qcom_pas.h | 50 +++++ include/linux/firmware/qcom/qcom_pas.h | 43 ++++ 5 files changed, 390 insertions(+) create mode 100644 drivers/firmware/qcom/qcom_pas.c create mode 100644 drivers/firmware/qcom/qcom_pas.h create mode 100644 include/linux/firmware/qcom/qcom_pas.h diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig index b477d54b495a..8653639d06db 100644 --- a/drivers/firmware/qcom/Kconfig +++ b/drivers/firmware/qcom/Kconfig @@ -6,6 +6,14 @@ =20 menu "Qualcomm firmware drivers" =20 +config QCOM_PAS + tristate + help + Enable the generic Peripheral Authentication Service (PAS) provided + by the firmware. It acts as the common layer with different TZ + backends plugged in whether it's an SCM implementation or a proper + TEE bus based PAS service implementation. + config QCOM_SCM select QCOM_TZMEM tristate diff --git a/drivers/firmware/qcom/Makefile b/drivers/firmware/qcom/Makefile index 0be40a1abc13..dc5ab45f906a 100644 --- a/drivers/firmware/qcom/Makefile +++ b/drivers/firmware/qcom/Makefile @@ -8,3 +8,4 @@ qcom-scm-objs +=3D qcom_scm.o qcom_scm-smc.o qcom_scm-legac= y.o obj-$(CONFIG_QCOM_TZMEM) +=3D qcom_tzmem.o obj-$(CONFIG_QCOM_QSEECOM) +=3D qcom_qseecom.o obj-$(CONFIG_QCOM_QSEECOM_UEFISECAPP) +=3D qcom_qseecom_uefisecapp.o +obj-$(CONFIG_QCOM_PAS) +=3D qcom_pas.o diff --git a/drivers/firmware/qcom/qcom_pas.c b/drivers/firmware/qcom/qcom_= pas.c new file mode 100644 index 000000000000..caf7fff33e5c --- /dev/null +++ b/drivers/firmware/qcom/qcom_pas.c @@ -0,0 +1,288 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include + +#include "qcom_pas.h" + +static struct qcom_pas_ops *ops_ptr; + +/** + * devm_qcom_pas_context_alloc() - Allocate peripheral authentication serv= ice + * context for a given peripheral + * + * PAS context is device-resource managed, so the caller does not need + * to worry about freeing the context memory. + * + * @dev: PAS firmware device + * @pas_id: peripheral authentication service id + * @mem_phys: Subsystem reserve memory start address + * @mem_size: Subsystem reserve memory size + * + * Return: The new PAS context, or ERR_PTR() on failure. + */ +struct qcom_pas_context *devm_qcom_pas_context_alloc(struct device *dev, + u32 pas_id, + phys_addr_t mem_phys, + size_t mem_size) +{ + struct qcom_pas_context *ctx; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); + + ctx->dev =3D dev; + ctx->pas_id =3D pas_id; + ctx->mem_phys =3D mem_phys; + ctx->mem_size =3D mem_size; + + return ctx; +} +EXPORT_SYMBOL_GPL(devm_qcom_pas_context_alloc); + +/** + * qcom_pas_init_image() - Initialize peripheral authentication service st= ate + * machine for a given peripheral, using the metadata + * @pas_id: peripheral authentication service id + * @metadata: pointer to memory containing ELF header, program header table + * and optional blob of data used for authenticating the metadata + * and the rest of the firmware + * @size: size of the metadata + * @ctx: optional pas context + * + * Return: 0 on success. + * + * Upon successful return, the PAS metadata context (@ctx) will be used to + * track the metadata allocation, this needs to be released by invoking + * qcom_pas_metadata_release() by the caller. + */ +int qcom_pas_init_image(u32 pas_id, const void *metadata, size_t size, + struct qcom_pas_context *ctx) +{ + if (!ops_ptr) + return -ENODEV; + + return ops_ptr->init_image(ops_ptr->dev, pas_id, metadata, size, ctx); +} +EXPORT_SYMBOL_GPL(qcom_pas_init_image); + +/** + * qcom_pas_metadata_release() - release metadata context + * @ctx: pas context + */ +void qcom_pas_metadata_release(struct qcom_pas_context *ctx) +{ + if (!ctx || !ctx->ptr || !ops_ptr) + return; + + ops_ptr->metadata_release(ops_ptr->dev, ctx); +} +EXPORT_SYMBOL_GPL(qcom_pas_metadata_release); + +/** + * qcom_pas_mem_setup() - Prepare the memory related to a given peripheral + * for firmware loading + * @pas_id: peripheral authentication service id + * @addr: start address of memory area to prepare + * @size: size of the memory area to prepare + * + * Return: 0 on success. + */ +int qcom_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size) +{ + if (!ops_ptr) + return -ENODEV; + + return ops_ptr->mem_setup(ops_ptr->dev, pas_id, addr, size); +} +EXPORT_SYMBOL_GPL(qcom_pas_mem_setup); + +/** + * qcom_pas_get_rsc_table() - Retrieve the resource table in passed output= buffer + * for a given peripheral. + * + * Qualcomm remote processor may rely on both static and dynamic resources= for + * its functionality. Static resources typically refer to memory-mapped + * addresses required by the subsystem and are often embedded within the + * firmware binary and dynamic resources, such as shared memory in DDR etc= ., + * are determined at runtime during the boot process. + * + * On Qualcomm Technologies devices, it's possible that static resources a= re + * not embedded in the firmware binary and instead are provided by TrustZo= ne. + * However, dynamic resources are always expected to come from TrustZone. = This + * indicates that for Qualcomm devices, all resources (static and dynamic)= will + * be provided by TrustZone PAS service. + * + * If the remote processor firmware binary does contain static resources, = they + * should be passed in input_rt. These will be forwarded to TrustZone for + * authentication. TrustZone will then append the dynamic resources and re= turn + * the complete resource table in output_rt_tzm. + * + * If the remote processor firmware binary does not include a resource tab= le, + * the caller of this function should set input_rt as NULL and input_rt_si= ze + * as zero respectively. + * + * More about documentation on resource table data structures can be found= in + * include/linux/remoteproc.h + * + * @ctx: PAS context + * @pas_id: peripheral authentication service id + * @input_rt: resource table buffer which is present in firmware bin= ary + * @input_rt_size: size of the resource table present in firmware binary + * @output_rt_size: TrustZone expects caller should pass worst case size f= or + * the output_rt_tzm. + * + * Return: + * On success, returns a pointer to the allocated buffer containing the f= inal + * resource table and output_rt_size will have actual resource table size= from + * TrustZone. The caller is responsible for freeing the buffer. On failur= e, + * returns ERR_PTR(-errno). + */ +struct resource_table *qcom_pas_get_rsc_table(struct qcom_pas_context *ctx, + void *input_rt, + size_t input_rt_size, + size_t *output_rt_size) +{ + if (!ctx) + return ERR_PTR(-EINVAL); + if (!ops_ptr) + return ERR_PTR(-ENODEV); + + return ops_ptr->get_rsc_table(ops_ptr->dev, ctx, input_rt, + input_rt_size, output_rt_size); +} +EXPORT_SYMBOL_GPL(qcom_pas_get_rsc_table); + +/** + * qcom_pas_auth_and_reset() - Authenticate the given peripheral firmware + * and reset the remote processor + * @pas_id: peripheral authentication service id + * + * Return: 0 on success. + */ +int qcom_pas_auth_and_reset(u32 pas_id) +{ + if (!ops_ptr) + return -ENODEV; + + return ops_ptr->auth_and_reset(ops_ptr->dev, pas_id); +} +EXPORT_SYMBOL_GPL(qcom_pas_auth_and_reset); + +/** + * qcom_pas_prepare_and_auth_reset() - Prepare, authenticate, and reset the + * remote processor + * + * @ctx: Context saved during call to qcom_scm_pas_context_init() + * + * This function performs the necessary steps to prepare a PAS subsystem, + * authenticate it using the provided metadata, and initiate a reset seque= nce. + * + * It should be used when Linux is in control setting up the IOMMU hardware + * for remote subsystem during secure firmware loading processes. The + * preparation step sets up a shmbridge over the firmware memory before + * TrustZone accesses the firmware memory region for authentication. The + * authentication step verifies the integrity and authenticity of the firm= ware + * or configuration using secure metadata. Finally, the reset step ensures= the + * subsystem starts in a clean and sane state. + * + * Return: 0 on success, negative errno on failure. + */ +int qcom_pas_prepare_and_auth_reset(struct qcom_pas_context *ctx) +{ + if (!ctx) + return -EINVAL; + if (!ops_ptr) + return -ENODEV; + + return ops_ptr->prepare_and_auth_reset(ops_ptr->dev, ctx); +} +EXPORT_SYMBOL_GPL(qcom_pas_prepare_and_auth_reset); + +/** + * qcom_pas_set_remote_state() - Set the remote processor state + * @state: peripheral state + * @pas_id: peripheral authentication service id + * + * Return: 0 on success. + */ +int qcom_pas_set_remote_state(u32 state, u32 pas_id) +{ + if (!ops_ptr) + return -ENODEV; + + return ops_ptr->set_remote_state(ops_ptr->dev, state, pas_id); +} +EXPORT_SYMBOL_GPL(qcom_pas_set_remote_state); + +/** + * qcom_pas_shutdown() - Shut down the remote processor + * @pas_id: peripheral authentication service id + * + * Return: 0 on success. + */ +int qcom_pas_shutdown(u32 pas_id) +{ + if (!ops_ptr) + return -ENODEV; + + return ops_ptr->shutdown(ops_ptr->dev, pas_id); +} +EXPORT_SYMBOL_GPL(qcom_pas_shutdown); + +/** + * qcom_pas_supported() - Check if the peripheral authentication service is + * available for the given peripheral + * @pas_id: peripheral authentication service id + * + * Return: true if PAS is supported for this peripheral, otherwise false. + */ +bool qcom_pas_supported(u32 pas_id) +{ + if (!ops_ptr) + return false; + + return ops_ptr->supported(ops_ptr->dev, pas_id); +} +EXPORT_SYMBOL_GPL(qcom_pas_supported); + +bool qcom_pas_is_available(void) +{ + /* + * The barrier for ops_ptr is intended to synchronize the data stores + * for the ops data structure when client drivers are in parallel + * checking for PAS service availability. + * + * Once the PAS backend becomes available, it is allowed for multiple + * threads to enter TZ for parallel bringup of co-processors during + * boot. + */ + return !!smp_load_acquire(&ops_ptr); +} +EXPORT_SYMBOL_GPL(qcom_pas_is_available); + +void qcom_pas_ops_register(struct qcom_pas_ops *ops) +{ + if (!qcom_pas_is_available()) + /* Paired with smp_load_acquire() in qcom_pas_is_available() */ + smp_store_release(&ops_ptr, ops); + else + pr_err("qcom_pas: ops already registered\n"); +} +EXPORT_SYMBOL_GPL(qcom_pas_ops_register); + +void qcom_pas_ops_unregister(void) +{ + /* Paired with smp_load_acquire() in qcom_pas_is_available() */ + smp_store_release(&ops_ptr, NULL); +} +EXPORT_SYMBOL_GPL(qcom_pas_ops_unregister); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Qualcomm common TZ PAS driver"); diff --git a/drivers/firmware/qcom/qcom_pas.h b/drivers/firmware/qcom/qcom_= pas.h new file mode 100644 index 000000000000..8643e2760602 --- /dev/null +++ b/drivers/firmware/qcom/qcom_pas.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __QCOM_PAS_INT_H +#define __QCOM_PAS_INT_H + +struct device; + +/** + * struct qcom_pas_ops - Qcom Peripheral Authentication Service (PAS) ops + * @drv_name: PAS driver name. + * @dev: PAS device pointer. + * @supported: Peripheral supported callback. + * @init_image: Peripheral image initialization callback. + * @mem_setup: Peripheral memory setup callback. + * @get_rsc_table: Peripheral get resource table callback. + * @prepare_and_auth_reset: Peripheral prepare firmware authentication and + * reset callback. + * @auth_and_reset: Peripheral firmware authentication and reset + * callback. + * @set_remote_state: Peripheral set remote state callback. + * @shutdown: Peripheral shutdown callback. + * @metadata_release: Image metadata release callback. + */ +struct qcom_pas_ops { + const char *drv_name; + struct device *dev; + bool (*supported)(struct device *dev, u32 pas_id); + int (*init_image)(struct device *dev, u32 pas_id, const void *metadata, + size_t size, struct qcom_pas_context *ctx); + int (*mem_setup)(struct device *dev, u32 pas_id, phys_addr_t addr, + phys_addr_t size); + void *(*get_rsc_table)(struct device *dev, struct qcom_pas_context *ctx, + void *input_rt, size_t input_rt_size, + size_t *output_rt_size); + int (*prepare_and_auth_reset)(struct device *dev, + struct qcom_pas_context *ctx); + int (*auth_and_reset)(struct device *dev, u32 pas_id); + int (*set_remote_state)(struct device *dev, u32 state, u32 pas_id); + int (*shutdown)(struct device *dev, u32 pas_id); + void (*metadata_release)(struct device *dev, + struct qcom_pas_context *ctx); +}; + +void qcom_pas_ops_register(struct qcom_pas_ops *ops); +void qcom_pas_ops_unregister(void); + +#endif /* __QCOM_PAS_INT_H */ diff --git a/include/linux/firmware/qcom/qcom_pas.h b/include/linux/firmwar= e/qcom/qcom_pas.h new file mode 100644 index 000000000000..65b1c9564458 --- /dev/null +++ b/include/linux/firmware/qcom/qcom_pas.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights res= erved. + * Copyright (C) 2015 Linaro Ltd. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __QCOM_PAS_H +#define __QCOM_PAS_H + +#include +#include + +struct qcom_pas_context { + struct device *dev; + u32 pas_id; + phys_addr_t mem_phys; + size_t mem_size; + void *ptr; + dma_addr_t phys; + ssize_t size; + bool use_tzmem; +}; + +bool qcom_pas_is_available(void); +struct qcom_pas_context *devm_qcom_pas_context_alloc(struct device *dev, + u32 pas_id, + phys_addr_t mem_phys, + size_t mem_size); +int qcom_pas_init_image(u32 pas_id, const void *metadata, size_t size, + struct qcom_pas_context *ctx); +struct resource_table *qcom_pas_get_rsc_table(struct qcom_pas_context *ctx, + void *input_rt, size_t input_rt_size, + size_t *output_rt_size); +int qcom_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size); +int qcom_pas_auth_and_reset(u32 pas_id); +int qcom_pas_prepare_and_auth_reset(struct qcom_pas_context *ctx); +int qcom_pas_set_remote_state(u32 state, u32 pas_id); +int qcom_pas_shutdown(u32 pas_id); +bool qcom_pas_supported(u32 pas_id); +void qcom_pas_metadata_release(struct qcom_pas_context *ctx); + +#endif /* __QCOM_PAS_H */ --=20 2.51.0 From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28EFA3B0ACA; Mon, 27 Apr 2026 09:57:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283830; cv=none; b=N5etst2GB5jfT3do2gzrw9B2dS0UoRALxKgT4YZcMzvfNu33PTzpSHgH2Fx6+UMKXmdZddVFhlyOj2b6QcD8ZLiGs7f5FKRhS+lnICNfV71bx3MbJNFr9YjZLi8Wwxhu0GLIyOs0gt7Da1sZYgk+Th9PEwxzR2RDDBZWjWKIYIs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283830; c=relaxed/simple; bh=xvoMSqLb6SfP83UjzVWIR7N1shkeibHvTD3IB0YGMW0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dWU5SZthmqZzmjs07E8x786iOS3HR73Xd8h+1IibzTX2qdh78MWLxvwU4YNNfsqelDvY4JZHZFtaxt2+TJ3ne5fxi+StQsNBc2mKKV3sr78EkkZlLswpAvE81movvaCHCqvKop9UAqCLwxlwMb7GjkAAe+RKZkN2v5qq1iD4bBs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tpl14dDs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tpl14dDs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B73B3C2BCB4; Mon, 27 Apr 2026 09:56:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777283829; bh=xvoMSqLb6SfP83UjzVWIR7N1shkeibHvTD3IB0YGMW0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tpl14dDsYIq6MoKnfbfToT3cXjHrr7pr7YZhsgOBdv6+kQE4R9h+WngfPo220yK4b Osczu9guAMcGFzjeqNce6LIm5d3ok9UL8jT6PcqzxxhliQj90yEj+vjmL34hmTpHIj lS1S5eP6d/6Bg42qVBln2YvESbxExiJjUDv8ELtr3zscQwWNELNtiHT5s7nzS+hnCY pDf/+eIxwF4Mzljo3pflUori6tBiRdVG5b1xHL6KfCUDBoqWEJxpQWDOLFy7smcbVv wapQRV9XqcQgaUVmhu2doSf854Q9/MjTxcqqVIcRI7vBIbVVnNxI66geYQ2BRHtgPU uD6FMLha/mZDg== From: Sumit Garg To: andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v4 03/15] firmware: qcom_scm: Migrate to generic PAS service Date: Mon, 27 Apr 2026 15:25:51 +0530 Message-ID: <20260427095603.1157963-4-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260427095603.1157963-1-sumit.garg@kernel.org> References: <20260427095603.1157963-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg With the availability of generic PAS service, let's add SCM calls as a backend to keep supporting legacy QTEE interfaces. The exported qcom_scm* wrappers will get dropped once all the client drivers get migrated as part of future patches. Signed-off-by: Sumit Garg Reviewed-by: Harshal Dev Reviewed-by: Mukesh Ojha =20 Tested-by: Mukesh Ojha # Lemans --- drivers/firmware/qcom/Kconfig | 1 + drivers/firmware/qcom/qcom_scm.c | 335 ++++++++++++++----------------- 2 files changed, 155 insertions(+), 181 deletions(-) diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig index 8653639d06db..9a12ae2b639d 100644 --- a/drivers/firmware/qcom/Kconfig +++ b/drivers/firmware/qcom/Kconfig @@ -15,6 +15,7 @@ config QCOM_PAS TEE bus based PAS service implementation. =20 config QCOM_SCM + select QCOM_PAS select QCOM_TZMEM tristate =20 diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 9b06a69d3a6d..d87a962e93da 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -33,6 +34,7 @@ =20 #include =20 +#include "qcom_pas.h" #include "qcom_scm.h" #include "qcom_tzmem.h" =20 @@ -479,25 +481,6 @@ void qcom_scm_cpu_power_down(u32 flags) } EXPORT_SYMBOL_GPL(qcom_scm_cpu_power_down); =20 -int qcom_scm_set_remote_state(u32 state, u32 id) -{ - struct qcom_scm_desc desc =3D { - .svc =3D QCOM_SCM_SVC_BOOT, - .cmd =3D QCOM_SCM_BOOT_SET_REMOTE_STATE, - .arginfo =3D QCOM_SCM_ARGS(2), - .args[0] =3D state, - .args[1] =3D id, - .owner =3D ARM_SMCCC_OWNER_SIP, - }; - struct qcom_scm_res res; - int ret; - - ret =3D qcom_scm_call(__scm->dev, &desc, &res); - - return ret ? : res.result[0]; -} -EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state); - static int qcom_scm_disable_sdi(void) { int ret; @@ -570,26 +553,12 @@ static void qcom_scm_set_download_mode(u32 dload_mode) dev_err(__scm->dev, "failed to set download mode: %d\n", ret); } =20 -/** - * devm_qcom_scm_pas_context_alloc() - Allocate peripheral authentication = service - * context for a given peripheral - * - * PAS context is device-resource managed, so the caller does not need - * to worry about freeing the context memory. - * - * @dev: PAS firmware device - * @pas_id: peripheral authentication service id - * @mem_phys: Subsystem reserve memory start address - * @mem_size: Subsystem reserve memory size - * - * Returns: The new PAS context, or ERR_PTR() on failure. - */ struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device= *dev, u32 pas_id, phys_addr_t mem_phys, size_t mem_size) { - struct qcom_scm_pas_context *ctx; + struct qcom_pas_context *ctx; =20 ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); if (!ctx) @@ -600,11 +569,12 @@ struct qcom_scm_pas_context *devm_qcom_scm_pas_contex= t_alloc(struct device *dev, ctx->mem_phys =3D mem_phys; ctx->mem_size =3D mem_size; =20 - return ctx; + return (struct qcom_scm_pas_context *)ctx; } EXPORT_SYMBOL_GPL(devm_qcom_scm_pas_context_alloc); =20 -static int __qcom_scm_pas_init_image(u32 pas_id, dma_addr_t mdata_phys, +static int __qcom_scm_pas_init_image(struct device *dev, u32 pas_id, + dma_addr_t mdata_phys, struct qcom_scm_res *res) { struct qcom_scm_desc desc =3D { @@ -626,7 +596,7 @@ static int __qcom_scm_pas_init_image(u32 pas_id, dma_ad= dr_t mdata_phys, =20 desc.args[1] =3D mdata_phys; =20 - ret =3D qcom_scm_call(__scm->dev, &desc, res); + ret =3D qcom_scm_call(dev, &desc, res); qcom_scm_bw_disable(); =20 disable_clk: @@ -635,7 +605,8 @@ static int __qcom_scm_pas_init_image(u32 pas_id, dma_ad= dr_t mdata_phys, return ret; } =20 -static int qcom_scm_pas_prep_and_init_image(struct qcom_scm_pas_context *c= tx, +static int qcom_scm_pas_prep_and_init_image(struct device *dev, + struct qcom_pas_context *ctx, const void *metadata, size_t size) { struct qcom_scm_res res; @@ -650,7 +621,7 @@ static int qcom_scm_pas_prep_and_init_image(struct qcom= _scm_pas_context *ctx, memcpy(mdata_buf, metadata, size); mdata_phys =3D qcom_tzmem_to_phys(mdata_buf); =20 - ret =3D __qcom_scm_pas_init_image(ctx->pas_id, mdata_phys, &res); + ret =3D __qcom_scm_pas_init_image(dev, ctx->pas_id, mdata_phys, &res); if (ret < 0) qcom_tzmem_free(mdata_buf); else @@ -659,25 +630,9 @@ static int qcom_scm_pas_prep_and_init_image(struct qco= m_scm_pas_context *ctx, return ret ? : res.result[0]; } =20 -/** - * qcom_scm_pas_init_image() - Initialize peripheral authentication service - * state machine for a given peripheral, using the - * metadata - * @pas_id: peripheral authentication service id - * @metadata: pointer to memory containing ELF header, program header table - * and optional blob of data used for authenticating the metadata - * and the rest of the firmware - * @size: size of the metadata - * @ctx: optional pas context - * - * Return: 0 on success. - * - * Upon successful return, the PAS metadata context (@ctx) will be used to - * track the metadata allocation, this needs to be released by invoking - * qcom_scm_pas_metadata_release() by the caller. - */ -int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size, - struct qcom_scm_pas_context *ctx) +static int __qcom_scm_pas_init_image2(struct device *dev, u32 pas_id, + const void *metadata, size_t size, + struct qcom_pas_context *ctx) { struct qcom_scm_res res; dma_addr_t mdata_phys; @@ -685,7 +640,7 @@ int qcom_scm_pas_init_image(u32 pas_id, const void *met= adata, size_t size, int ret; =20 if (ctx && ctx->use_tzmem) - return qcom_scm_pas_prep_and_init_image(ctx, metadata, size); + return qcom_scm_pas_prep_and_init_image(dev, ctx, metadata, size); =20 /* * During the scm call memory protection will be enabled for the meta @@ -699,16 +654,15 @@ int qcom_scm_pas_init_image(u32 pas_id, const void *m= etadata, size_t size, * If we pass a buffer that is already part of an SHM Bridge to this * call, it will fail. */ - mdata_buf =3D dma_alloc_coherent(__scm->dev, size, &mdata_phys, - GFP_KERNEL); + mdata_buf =3D dma_alloc_coherent(dev, size, &mdata_phys, GFP_KERNEL); if (!mdata_buf) return -ENOMEM; =20 memcpy(mdata_buf, metadata, size); =20 - ret =3D __qcom_scm_pas_init_image(pas_id, mdata_phys, &res); + ret =3D __qcom_scm_pas_init_image(dev, pas_id, mdata_phys, &res); if (ret < 0 || !ctx) { - dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys); + dma_free_coherent(dev, size, mdata_buf, mdata_phys); } else if (ctx) { ctx->ptr =3D mdata_buf; ctx->phys =3D mdata_phys; @@ -717,36 +671,35 @@ int qcom_scm_pas_init_image(u32 pas_id, const void *m= etadata, size_t size, =20 return ret ? : res.result[0]; } -EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image); =20 -/** - * qcom_scm_pas_metadata_release() - release metadata context - * @ctx: pas context - */ -void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx) +int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size, + struct qcom_scm_pas_context *ctx) { - if (!ctx->ptr) - return; + return __qcom_scm_pas_init_image2(__scm->dev, pas_id, metadata, size, + (struct qcom_pas_context *)ctx); +} +EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image); =20 +static void __qcom_scm_pas_metadata_release(struct device *dev, + struct qcom_pas_context *ctx) +{ if (ctx->use_tzmem) qcom_tzmem_free(ctx->ptr); else - dma_free_coherent(__scm->dev, ctx->size, ctx->ptr, ctx->phys); + dma_free_coherent(dev, ctx->size, ctx->ptr, ctx->phys); =20 ctx->ptr =3D NULL; } + +void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx) +{ + __qcom_scm_pas_metadata_release(__scm->dev, + (struct qcom_pas_context *)ctx); +} EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release); =20 -/** - * qcom_scm_pas_mem_setup() - Prepare the memory related to a given periph= eral - * for firmware loading - * @pas_id: peripheral authentication service id - * @addr: start address of memory area to prepare - * @size: size of the memory area to prepare - * - * Returns 0 on success. - */ -int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size) +static int __qcom_scm_pas_mem_setup(struct device *dev, u32 pas_id, + phys_addr_t addr, phys_addr_t size) { int ret; struct qcom_scm_desc desc =3D { @@ -768,7 +721,7 @@ int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr= , phys_addr_t size) if (ret) goto disable_clk; =20 - ret =3D qcom_scm_call(__scm->dev, &desc, &res); + ret =3D qcom_scm_call(dev, &desc, &res); qcom_scm_bw_disable(); =20 disable_clk: @@ -776,9 +729,15 @@ int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t add= r, phys_addr_t size) =20 return ret ? : res.result[0]; } + +int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size) +{ + return __qcom_scm_pas_mem_setup(__scm->dev, pas_id, addr, size); +} EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup); =20 -static void *__qcom_scm_pas_get_rsc_table(u32 pas_id, void *input_rt_tzm, +static void *__qcom_scm_pas_get_rsc_table(struct device *dev, u32 pas_id, + void *input_rt_tzm, size_t input_rt_size, size_t *output_rt_size) { @@ -813,7 +772,7 @@ static void *__qcom_scm_pas_get_rsc_table(u32 pas_id, v= oid *input_rt_tzm, * with output_rt_tzm buffer with res.result[2] size however, It should n= ot * be of unresonable size. */ - ret =3D qcom_scm_call(__scm->dev, &desc, &res); + ret =3D qcom_scm_call(dev, &desc, &res); if (!ret && res.result[2] > SZ_1G) { ret =3D -E2BIG; goto free_output_rt; @@ -830,51 +789,11 @@ static void *__qcom_scm_pas_get_rsc_table(u32 pas_id,= void *input_rt_tzm, return ret ? ERR_PTR(ret) : output_rt_tzm; } =20 -/** - * qcom_scm_pas_get_rsc_table() - Retrieve the resource table in passed ou= tput buffer - * for a given peripheral. - * - * Qualcomm remote processor may rely on both static and dynamic resources= for - * its functionality. Static resources typically refer to memory-mapped ad= dresses - * required by the subsystem and are often embedded within the firmware bi= nary - * and dynamic resources, such as shared memory in DDR etc., are determine= d at - * runtime during the boot process. - * - * On Qualcomm Technologies devices, it's possible that static resources a= re not - * embedded in the firmware binary and instead are provided by TrustZone H= owever, - * dynamic resources are always expected to come from TrustZone. This indi= cates - * that for Qualcomm devices, all resources (static and dynamic) will be p= rovided - * by TrustZone via the SMC call. - * - * If the remote processor firmware binary does contain static resources, = they - * should be passed in input_rt. These will be forwarded to TrustZone for - * authentication. TrustZone will then append the dynamic resources and re= turn - * the complete resource table in output_rt_tzm. - * - * If the remote processor firmware binary does not include a resource tab= le, - * the caller of this function should set input_rt as NULL and input_rt_si= ze - * as zero respectively. - * - * More about documentation on resource table data structures can be found= in - * include/linux/remoteproc.h - * - * @ctx: PAS context - * @pas_id: peripheral authentication service id - * @input_rt: resource table buffer which is present in firmware bin= ary - * @input_rt_size: size of the resource table present in firmware binary - * @output_rt_size: TrustZone expects caller should pass worst case size f= or - * the output_rt_tzm. - * - * Return: - * On success, returns a pointer to the allocated buffer containing the f= inal - * resource table and output_rt_size will have actual resource table size= from - * TrustZone. The caller is responsible for freeing the buffer. On failur= e, - * returns ERR_PTR(-errno). - */ -struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_cont= ext *ctx, - void *input_rt, - size_t input_rt_size, - size_t *output_rt_size) +static void *__qcom_scm_pas_get_rsc_table2(struct device *dev, + struct qcom_pas_context *ctx, + void *input_rt, + size_t input_rt_size, + size_t *output_rt_size) { struct resource_table empty_rsc =3D {}; size_t size =3D SZ_16K; @@ -909,11 +828,12 @@ struct resource_table *qcom_scm_pas_get_rsc_table(str= uct qcom_scm_pas_context *c =20 memcpy(input_rt_tzm, input_rt, input_rt_size); =20 - output_rt_tzm =3D __qcom_scm_pas_get_rsc_table(ctx->pas_id, input_rt_tzm, + output_rt_tzm =3D __qcom_scm_pas_get_rsc_table(dev, ctx->pas_id, + input_rt_tzm, input_rt_size, &size); if (PTR_ERR(output_rt_tzm) =3D=3D -EOVERFLOW) /* Try again with the size requested by the TZ */ - output_rt_tzm =3D __qcom_scm_pas_get_rsc_table(ctx->pas_id, + output_rt_tzm =3D __qcom_scm_pas_get_rsc_table(dev, ctx->pas_id, input_rt_tzm, input_rt_size, &size); @@ -943,16 +863,20 @@ struct resource_table *qcom_scm_pas_get_rsc_table(str= uct qcom_scm_pas_context *c =20 return ret ? ERR_PTR(ret) : tbl_ptr; } + +struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_cont= ext *ctx, + void *input_rt, + size_t input_rt_size, + size_t *output_rt_size) +{ + return __qcom_scm_pas_get_rsc_table2(__scm->dev, + (struct qcom_pas_context *)ctx, + input_rt, input_rt_size, + output_rt_size); +} EXPORT_SYMBOL_GPL(qcom_scm_pas_get_rsc_table); =20 -/** - * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmw= are - * and reset the remote processor - * @pas_id: peripheral authentication service id - * - * Return 0 on success. - */ -int qcom_scm_pas_auth_and_reset(u32 pas_id) +static int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { @@ -972,7 +896,7 @@ int qcom_scm_pas_auth_and_reset(u32 pas_id) if (ret) goto disable_clk; =20 - ret =3D qcom_scm_call(__scm->dev, &desc, &res); + ret =3D qcom_scm_call(dev, &desc, &res); qcom_scm_bw_disable(); =20 disable_clk: @@ -980,28 +904,15 @@ int qcom_scm_pas_auth_and_reset(u32 pas_id) =20 return ret ? : res.result[0]; } + +int qcom_scm_pas_auth_and_reset(u32 pas_id) +{ + return __qcom_scm_pas_auth_and_reset(__scm->dev, pas_id); +} EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset); =20 -/** - * qcom_scm_pas_prepare_and_auth_reset() - Prepare, authenticate, and rese= t the - * remote processor - * - * @ctx: Context saved during call to qcom_scm_pas_context_init() - * - * This function performs the necessary steps to prepare a PAS subsystem, - * authenticate it using the provided metadata, and initiate a reset seque= nce. - * - * It should be used when Linux is in control setting up the IOMMU hardware - * for remote subsystem during secure firmware loading processes. The prep= aration - * step sets up a shmbridge over the firmware memory before TrustZone acce= sses the - * firmware memory region for authentication. The authentication step veri= fies - * the integrity and authenticity of the firmware or configuration using s= ecure - * metadata. Finally, the reset step ensures the subsystem starts in a cle= an and - * sane state. - * - * Return: 0 on success, negative errno on failure. - */ -int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx) +static int __qcom_scm_pas_prepare_and_auth_reset(struct device *dev, + struct qcom_pas_context *ctx) { u64 handle; int ret; @@ -1012,7 +923,7 @@ int qcom_scm_pas_prepare_and_auth_reset(struct qcom_sc= m_pas_context *ctx) * memory region and then invokes a call to TrustZone to authenticate. */ if (!ctx->use_tzmem) - return qcom_scm_pas_auth_and_reset(ctx->pas_id); + return __qcom_scm_pas_auth_and_reset(dev, ctx->pas_id); =20 /* * When Linux runs @ EL2 Linux must create the shmbridge itself and then @@ -1022,20 +933,45 @@ int qcom_scm_pas_prepare_and_auth_reset(struct qcom_= scm_pas_context *ctx) if (ret) return ret; =20 - ret =3D qcom_scm_pas_auth_and_reset(ctx->pas_id); + ret =3D __qcom_scm_pas_auth_and_reset(dev, ctx->pas_id); qcom_tzmem_shm_bridge_delete(handle); =20 return ret; } + +int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx) +{ + return __qcom_scm_pas_prepare_and_auth_reset(__scm->dev, + (struct qcom_pas_context *)ctx); +} EXPORT_SYMBOL_GPL(qcom_scm_pas_prepare_and_auth_reset); =20 -/** - * qcom_scm_pas_shutdown() - Shut down the remote processor - * @pas_id: peripheral authentication service id - * - * Returns 0 on success. - */ -int qcom_scm_pas_shutdown(u32 pas_id) +static int __qcom_scm_pas_set_remote_state(struct device *dev, u32 state, + u32 pas_id) +{ + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_BOOT, + .cmd =3D QCOM_SCM_BOOT_SET_REMOTE_STATE, + .arginfo =3D QCOM_SCM_ARGS(2), + .args[0] =3D state, + .args[1] =3D pas_id, + .owner =3D ARM_SMCCC_OWNER_SIP, + }; + struct qcom_scm_res res; + int ret; + + ret =3D qcom_scm_call(dev, &desc, &res); + + return ret ? : res.result[0]; +} + +int qcom_scm_set_remote_state(u32 state, u32 id) +{ + return __qcom_scm_pas_set_remote_state(__scm->dev, state, id); +} +EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state); + +static int __qcom_scm_pas_shutdown(struct device *dev, u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { @@ -1055,7 +991,7 @@ int qcom_scm_pas_shutdown(u32 pas_id) if (ret) goto disable_clk; =20 - ret =3D qcom_scm_call(__scm->dev, &desc, &res); + ret =3D qcom_scm_call(dev, &desc, &res); qcom_scm_bw_disable(); =20 disable_clk: @@ -1063,16 +999,14 @@ int qcom_scm_pas_shutdown(u32 pas_id) =20 return ret ? : res.result[0]; } + +int qcom_scm_pas_shutdown(u32 pas_id) +{ + return __qcom_scm_pas_shutdown(__scm->dev, pas_id); +} EXPORT_SYMBOL_GPL(qcom_scm_pas_shutdown); =20 -/** - * qcom_scm_pas_supported() - Check if the peripheral authentication servi= ce is - * available for the given peripherial - * @pas_id: peripheral authentication service id - * - * Returns true if PAS is supported for this peripheral, otherwise false. - */ -bool qcom_scm_pas_supported(u32 pas_id) +static bool __qcom_scm_pas_supported(struct device *dev, u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { @@ -1084,16 +1018,49 @@ bool qcom_scm_pas_supported(u32 pas_id) }; struct qcom_scm_res res; =20 - if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, + if (!__qcom_scm_is_call_available(dev, QCOM_SCM_SVC_PIL, QCOM_SCM_PIL_PAS_IS_SUPPORTED)) return false; =20 - ret =3D qcom_scm_call(__scm->dev, &desc, &res); + ret =3D qcom_scm_call(dev, &desc, &res); =20 return ret ? false : !!res.result[0]; } + +bool qcom_scm_pas_supported(u32 pas_id) +{ + return __qcom_scm_pas_supported(__scm->dev, pas_id); +} EXPORT_SYMBOL_GPL(qcom_scm_pas_supported); =20 +static struct qcom_pas_ops qcom_pas_ops_scm =3D { + .drv_name =3D "qcom_scm", + .supported =3D __qcom_scm_pas_supported, + .init_image =3D __qcom_scm_pas_init_image2, + .mem_setup =3D __qcom_scm_pas_mem_setup, + .get_rsc_table =3D __qcom_scm_pas_get_rsc_table2, + .auth_and_reset =3D __qcom_scm_pas_auth_and_reset, + .prepare_and_auth_reset =3D __qcom_scm_pas_prepare_and_auth_reset, + .set_remote_state =3D __qcom_scm_pas_set_remote_state, + .shutdown =3D __qcom_scm_pas_shutdown, + .metadata_release =3D __qcom_scm_pas_metadata_release, +}; + +/** + * qcom_scm_is_pas_available() - Check if the peripheral authentication se= rvice + * is available via SCM or not + * + * Returns true if PAS is available, otherwise false. + */ +static bool qcom_scm_is_pas_available(void) +{ + if (!__qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_PIL, + QCOM_SCM_PIL_PAS_AUTH_AND_RESET)) + return false; + + return true; +} + static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) { struct qcom_scm_desc desc =3D { @@ -2836,6 +2803,11 @@ static int qcom_scm_probe(struct platform_device *pd= ev) =20 __get_convention(); =20 + if (qcom_scm_is_pas_available()) { + qcom_pas_ops_scm.dev =3D scm->dev; + qcom_pas_ops_register(&qcom_pas_ops_scm); + } + /* * If "download mode" is requested, from this point on warmboot * will cause the boot stages to enter download mode, unless @@ -2875,6 +2847,7 @@ static void qcom_scm_shutdown(struct platform_device = *pdev) { /* Clean shutdown, disable download mode to allow normal restart */ qcom_scm_set_download_mode(QCOM_DLOAD_NODUMP); + qcom_pas_ops_unregister(); } =20 static const struct of_device_id qcom_scm_dt_match[] =3D { --=20 2.51.0 From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36B123B3BF2; Mon, 27 Apr 2026 09:57:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283844; cv=none; b=tcXENhYq4OI6DQRaGlNWFdNAz+nuLmP016UPFtAZBxdbZKKhuz33cst11FF8fkP9g3ZKbd4n7iG696VIcuNuNjxeBgfz4HhzcSQc6sZBw6zAdfMpVfJUVOHyX1rdjgVFzsoO5wZA33g2/0gblR8E+Xccq2HESSgO/dVT7++yWNI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283844; c=relaxed/simple; bh=OOblnkYddkRyc8tYMxdqgWXaI8R7SAn2dlqOhSRdSBo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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charset="utf-8" From: Sumit Garg Add support for Peripheral Authentication Service (PAS) driver based on TEE bus with OP-TEE providing the backend PAS service implementation. The TEE PAS service ABI is designed to be extensible with additional API as PTA_QCOM_PAS_CAPABILITIES. This allows to accommodate any future extensions of the PAS service needed while still maintaining backwards compatibility. Signed-off-by: Sumit Garg Reviewed-by: Harshal Dev Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans --- drivers/firmware/qcom/Kconfig | 10 + drivers/firmware/qcom/Makefile | 1 + drivers/firmware/qcom/qcom_pas_tee.c | 479 +++++++++++++++++++++++++++ 3 files changed, 490 insertions(+) create mode 100644 drivers/firmware/qcom/qcom_pas_tee.c diff --git a/drivers/firmware/qcom/Kconfig b/drivers/firmware/qcom/Kconfig index 9a12ae2b639d..300b3a1bd178 100644 --- a/drivers/firmware/qcom/Kconfig +++ b/drivers/firmware/qcom/Kconfig @@ -14,6 +14,16 @@ config QCOM_PAS backends plugged in whether it's an SCM implementation or a proper TEE bus based PAS service implementation. =20 +config QCOM_PAS_TEE + tristate + select QCOM_PAS + depends on TEE + depends on !CPU_BIG_ENDIAN + default m if ARCH_QCOM + help + Enable the generic Peripheral Authentication Service (PAS) provided + by the firmware TEE implementation as the backend. + config QCOM_SCM select QCOM_PAS select QCOM_TZMEM diff --git a/drivers/firmware/qcom/Makefile b/drivers/firmware/qcom/Makefile index dc5ab45f906a..48801d18f37b 100644 --- a/drivers/firmware/qcom/Makefile +++ b/drivers/firmware/qcom/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_QCOM_TZMEM) +=3D qcom_tzmem.o obj-$(CONFIG_QCOM_QSEECOM) +=3D qcom_qseecom.o obj-$(CONFIG_QCOM_QSEECOM_UEFISECAPP) +=3D qcom_qseecom_uefisecapp.o obj-$(CONFIG_QCOM_PAS) +=3D qcom_pas.o +obj-$(CONFIG_QCOM_PAS_TEE) +=3D qcom_pas_tee.o diff --git a/drivers/firmware/qcom/qcom_pas_tee.c b/drivers/firmware/qcom/q= com_pas_tee.c new file mode 100644 index 000000000000..af73d0a68525 --- /dev/null +++ b/drivers/firmware/qcom/qcom_pas_tee.c @@ -0,0 +1,479 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "qcom_pas.h" + +/* + * Peripheral Authentication Service (PAS) supported. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + */ +#define TA_QCOM_PAS_IS_SUPPORTED 1 + +/* + * PAS capabilities. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + * [out] params[1].value.a: PAS capability flags + */ +#define TA_QCOM_PAS_CAPABILITIES 2 + +/* + * PAS image initialization. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + * [in] params[1].memref: Loadable firmware metadata + */ +#define TA_QCOM_PAS_INIT_IMAGE 3 + +/* + * PAS memory setup. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + * [in] params[0].value.b: Relocatable firmware size + * [in] params[1].value.a: 32bit LSB relocatable firmware memory address + * [in] params[1].value.b: 32bit MSB relocatable firmware memory address + */ +#define TA_QCOM_PAS_MEM_SETUP 4 + +/* + * PAS get resource table. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + * [inout] params[1].memref: Resource table config + */ +#define TA_QCOM_PAS_GET_RESOURCE_TABLE 5 + +/* + * PAS image authentication and co-processor reset. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + * [in] params[0].value.b: Firmware size + * [in] params[1].value.a: 32bit LSB firmware memory address + * [in] params[1].value.b: 32bit MSB firmware memory address + * [in] params[2].memref: Optional fw memory space shared/lent + */ +#define TA_QCOM_PAS_AUTH_AND_RESET 6 + +/* + * PAS co-processor set suspend/resume state. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + * [in] params[0].value.b: Co-processor state identifier + */ +#define TA_QCOM_PAS_SET_REMOTE_STATE 7 + +/* + * PAS co-processor shutdown. + * + * [in] params[0].value.a: Unique 32bit remote processor identifier + */ +#define TA_QCOM_PAS_SHUTDOWN 8 + +#define TEE_NUM_PARAMS 4 + +/** + * struct qcom_pas_tee_private - PAS service private data + * @dev: PAS service device. + * @ctx: TEE context handler. + * @session_id: PAS TA session identifier. + */ +struct qcom_pas_tee_private { + struct device *dev; + struct tee_context *ctx; + u32 session_id; +}; + +static bool qcom_pas_tee_supported(struct device *dev, u32 pas_id) +{ + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + struct tee_ioctl_invoke_arg inv_arg =3D { + .func =3D TA_QCOM_PAS_IS_SUPPORTED, + .session =3D data->session_id, + .num_params =3D TEE_NUM_PARAMS + }; + struct tee_param param[4] =3D { + [0] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D pas_id + } + }; + int ret; + + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS not supported, pas_id: %d, ret: %d, err: 0x%x\n", + pas_id, ret, inv_arg.ret); + return false; + } + + return true; +} + +static int qcom_pas_tee_init_image(struct device *dev, u32 pas_id, + const void *metadata, size_t size, + struct qcom_pas_context *ctx) +{ + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + struct tee_ioctl_invoke_arg inv_arg =3D { + .func =3D TA_QCOM_PAS_INIT_IMAGE, + .session =3D data->session_id, + .num_params =3D TEE_NUM_PARAMS + }; + struct tee_param param[4] =3D { + [0] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D pas_id + }, + [1] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT, + } + }; + struct tee_shm *mdata_shm; + u8 *mdata_buf =3D NULL; + int ret; + + mdata_shm =3D tee_shm_alloc_kernel_buf(data->ctx, size); + if (IS_ERR(mdata_shm)) { + dev_err(dev, "mdata_shm allocation failed\n"); + return PTR_ERR(mdata_shm); + } + + mdata_buf =3D tee_shm_get_va(mdata_shm, 0); + if (IS_ERR(mdata_buf)) { + dev_err(dev, "mdata_buf get VA failed\n"); + tee_shm_free(mdata_shm); + return PTR_ERR(mdata_buf); + } + memcpy(mdata_buf, metadata, size); + + param[1].u.memref.shm =3D mdata_shm; + param[1].u.memref.size =3D size; + + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS init image failed, pas_id: %d, ret: %d, err: 0x%x\n", + pas_id, ret, inv_arg.ret); + tee_shm_free(mdata_shm); + return ret ?: -EINVAL; + } + + if (ctx) + ctx->ptr =3D (void *)mdata_shm; + else + tee_shm_free(mdata_shm); + + return ret; +} + +static int qcom_pas_tee_mem_setup(struct device *dev, u32 pas_id, + phys_addr_t addr, phys_addr_t size) +{ + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + struct tee_ioctl_invoke_arg inv_arg =3D { + .func =3D TA_QCOM_PAS_MEM_SETUP, + .session =3D data->session_id, + .num_params =3D TEE_NUM_PARAMS + }; + struct tee_param param[4] =3D { + [0] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D pas_id, + .u.value.b =3D size, + }, + [1] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D lower_32_bits(addr), + .u.value.b =3D upper_32_bits(addr), + } + }; + int ret; + + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS mem setup failed, pas_id: %d, ret: %d, err: 0x%x\n", + pas_id, ret, inv_arg.ret); + return ret ?: -EINVAL; + } + + return ret; +} + +DEFINE_FREE(shm_free, struct tee_shm *, tee_shm_free(_T)) + +static void *qcom_pas_tee_get_rsc_table(struct device *dev, + struct qcom_pas_context *ctx, + void *input_rt, size_t input_rt_size, + size_t *output_rt_size) +{ + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + struct tee_ioctl_invoke_arg inv_arg =3D { + .func =3D TA_QCOM_PAS_GET_RESOURCE_TABLE, + .session =3D data->session_id, + .num_params =3D TEE_NUM_PARAMS + }; + struct tee_param param[4] =3D { + [0] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D ctx->pas_id, + }, + [1] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INOUT, + .u.memref.size =3D input_rt_size, + } + }; + void *rt_buf =3D NULL; + int ret; + + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS get RT failed, pas_id: %d, ret: %d, err: 0x%x\n", + ctx->pas_id, ret, inv_arg.ret); + return ret ? ERR_PTR(ret) : ERR_PTR(-EINVAL); + } + + if (param[1].u.memref.size) { + struct tee_shm *rt_shm __free(shm_free) =3D + tee_shm_alloc_kernel_buf(data->ctx, + param[1].u.memref.size); + void *rt_shm_va; + + if (IS_ERR(rt_shm)) { + dev_err(dev, "rt_shm allocation failed\n"); + return rt_shm; + } + + rt_shm_va =3D tee_shm_get_va(rt_shm, 0); + if (IS_ERR(rt_shm_va)) { + dev_err(dev, "rt_shm get VA failed\n"); + return ERR_CAST(rt_shm_va); + } + memcpy(rt_shm_va, input_rt, input_rt_size); + + param[1].u.memref.shm =3D rt_shm; + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS get RT failed, pas_id: %d, ret: %d, err: 0x%x\n", + ctx->pas_id, ret, inv_arg.ret); + return ret ? ERR_PTR(ret) : ERR_PTR(-EINVAL); + } + + if (param[1].u.memref.size) { + *output_rt_size =3D param[1].u.memref.size; + rt_buf =3D kmemdup(rt_shm_va, *output_rt_size, GFP_KERNEL); + if (!rt_buf) + return ERR_PTR(-ENOMEM); + } + } + + return rt_buf; +} + +static int __qcom_pas_tee_auth_and_reset(struct device *dev, u32 pas_id, + phys_addr_t mem_phys, size_t mem_size) +{ + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + struct tee_ioctl_invoke_arg inv_arg =3D { + .func =3D TA_QCOM_PAS_AUTH_AND_RESET, + .session =3D data->session_id, + .num_params =3D TEE_NUM_PARAMS + }; + struct tee_param param[4] =3D { + [0] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D pas_id, + .u.value.b =3D mem_size, + }, + [1] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D lower_32_bits(mem_phys), + .u.value.b =3D upper_32_bits(mem_phys), + }, + /* Reserved for fw memory space to be shared or lent */ + [2] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_MEMREF_INPUT, + } + }; + int ret; + + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS auth reset failed, pas_id: %d, ret: %d, err: 0x%x\n", + pas_id, ret, inv_arg.ret); + return ret ?: -EINVAL; + } + + return ret; +} + +static int qcom_pas_tee_auth_and_reset(struct device *dev, u32 pas_id) +{ + return __qcom_pas_tee_auth_and_reset(dev, pas_id, 0, 0); +} + +static int qcom_pas_tee_prepare_and_auth_reset(struct device *dev, + struct qcom_pas_context *ctx) +{ + return __qcom_pas_tee_auth_and_reset(dev, ctx->pas_id, ctx->mem_phys, + ctx->mem_size); +} + +static int qcom_pas_tee_set_remote_state(struct device *dev, u32 state, + u32 pas_id) +{ + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + struct tee_ioctl_invoke_arg inv_arg =3D { + .func =3D TA_QCOM_PAS_SET_REMOTE_STATE, + .session =3D data->session_id, + .num_params =3D TEE_NUM_PARAMS + }; + struct tee_param param[4] =3D { + [0] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D pas_id, + .u.value.b =3D state, + } + }; + int ret; + + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS shutdown failed, pas_id: %d, ret: %d, err: 0x%x\n", + pas_id, ret, inv_arg.ret); + return ret ?: -EINVAL; + } + + return ret; +} + +static int qcom_pas_tee_shutdown(struct device *dev, u32 pas_id) +{ + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + struct tee_ioctl_invoke_arg inv_arg =3D { + .func =3D TA_QCOM_PAS_SHUTDOWN, + .session =3D data->session_id, + .num_params =3D TEE_NUM_PARAMS + }; + struct tee_param param[4] =3D { + [0] =3D { + .attr =3D TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INPUT, + .u.value.a =3D pas_id + } + }; + int ret; + + ret =3D tee_client_invoke_func(data->ctx, &inv_arg, param); + if (ret < 0 || inv_arg.ret !=3D 0) { + dev_err(dev, "PAS shutdown failed, pas_id: %d, ret: %d, err: 0x%x\n", + pas_id, ret, inv_arg.ret); + return ret ?: -EINVAL; + } + + return ret; +} + +static void qcom_pas_tee_metadata_release(struct device *dev, + struct qcom_pas_context *ctx) +{ + struct tee_shm *mdata_shm =3D ctx->ptr; + + tee_shm_free(mdata_shm); +} + +static struct qcom_pas_ops qcom_pas_ops_tee =3D { + .drv_name =3D "qcom-pas-tee", + .supported =3D qcom_pas_tee_supported, + .init_image =3D qcom_pas_tee_init_image, + .mem_setup =3D qcom_pas_tee_mem_setup, + .get_rsc_table =3D qcom_pas_tee_get_rsc_table, + .auth_and_reset =3D qcom_pas_tee_auth_and_reset, + .prepare_and_auth_reset =3D qcom_pas_tee_prepare_and_auth_reset, + .set_remote_state =3D qcom_pas_tee_set_remote_state, + .shutdown =3D qcom_pas_tee_shutdown, + .metadata_release =3D qcom_pas_tee_metadata_release, +}; + +static int optee_ctx_match(struct tee_ioctl_version_data *ver, const void = *data) +{ + return ver->impl_id =3D=3D TEE_IMPL_ID_OPTEE; +} + +static int qcom_pas_tee_probe(struct tee_client_device *pas_dev) +{ + struct device *dev =3D &pas_dev->dev; + struct qcom_pas_tee_private *data; + struct tee_ioctl_open_session_arg sess_arg =3D { + .clnt_login =3D TEE_IOCTL_LOGIN_REE_KERNEL + }; + int ret, err =3D -ENODEV; + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->ctx =3D tee_client_open_context(NULL, optee_ctx_match, NULL, NULL); + if (IS_ERR(data->ctx)) + return -ENODEV; + + export_uuid(sess_arg.uuid, &pas_dev->id.uuid); + ret =3D tee_client_open_session(data->ctx, &sess_arg, NULL); + if (ret < 0 || sess_arg.ret !=3D 0) { + dev_err(dev, "tee_client_open_session failed, ret: %d, err: 0x%x\n", + ret, sess_arg.ret); + err =3D ret ?: -EINVAL; + goto out_ctx; + } + + data->session_id =3D sess_arg.session; + dev_set_drvdata(dev, data); + qcom_pas_ops_tee.dev =3D dev; + qcom_pas_ops_register(&qcom_pas_ops_tee); + + return ret; +out_ctx: + tee_client_close_context(data->ctx); + + return err; +} + +static void qcom_pas_tee_remove(struct tee_client_device *pas_dev) +{ + struct device *dev =3D &pas_dev->dev; + struct qcom_pas_tee_private *data =3D dev_get_drvdata(dev); + + qcom_pas_ops_unregister(); + tee_client_close_session(data->ctx, data->session_id); + tee_client_close_context(data->ctx); +} + +static const struct tee_client_device_id qcom_pas_tee_id_table[] =3D { + {UUID_INIT(0xcff7d191, 0x7ca0, 0x4784, + 0xaf, 0x13, 0x48, 0x22, 0x3b, 0x9a, 0x4f, 0xbe)}, + {} +}; +MODULE_DEVICE_TABLE(tee, qcom_pas_tee_id_table); + +static struct tee_client_driver optee_pas_tee_driver =3D { + .probe =3D qcom_pas_tee_probe, + .remove =3D qcom_pas_tee_remove, + .id_table =3D qcom_pas_tee_id_table, + .driver =3D { + .name =3D "qcom-pas-tee", + }, +}; + +module_tee_client_driver(optee_pas_tee_driver); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Qualcomm PAS TEE driver"); --=20 2.51.0 From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A124D3B3C11; Mon, 27 Apr 2026 09:57:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283858; cv=none; b=b8oYAfOeBj4JS9y20tWU+os+/Po7L+FPeWVbQVXtmueSBjQq6IOYNXD2UFHA22EwazRvhQZb1UGsnfCrD5RLDcvqFclG1xysXo2yIqWfOyPKzv/enqsfX4VKmNBJvPqbN5zNqtm7IjVtx5NGdPdvVytQ3RL1LKVL47D4WABx3ig= ARC-Message-Signature: i=1; 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b=tefwXEppoWncta9TOUT6uzrshJrU5jVgNxJfZROG6t47OVgcaPdOyoco/f2lU2T65 gUCYQu3xSVvnGw0s2zlgAl+fk01AJmXIoQWhQELhahqaOPIfLVDOqQ5+8qHVeCkyNG LpX+8x/p9c9Nyoy4ZvZBzhpL/lZaWaMmnl1QPFnIhHC7Rz9dBce5Oi9f71MdgX7K02 7CxVqI4XQU+u6iPfE6X/jZ8hj+7QHaCFSbvKKBiI1pU6QY4Xmr/ldb4MyeOnlHJd1x 4XsJHqe4y0E/iJq8LlvKb/lKQOeFMe7P8opyhWb6h6VZBBeBQBZOBjBmq9UyddAwKD PkVyw1yfXoRBw== From: Sumit Garg To: andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v4 05/15] remoteproc: qcom_q6v5_pas: Switch over to generic PAS TZ APIs Date: Mon, 27 Apr 2026 15:25:53 +0530 Message-ID: <20260427095603.1157963-6-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260427095603.1157963-1-sumit.garg@kernel.org> References: <20260427095603.1157963-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Switch qcom_q6v5_pas client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Signed-off-by: Sumit Garg Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans --- drivers/remoteproc/qcom_q6v5_pas.c | 51 +++++++++++++++--------------- 1 file changed, 26 insertions(+), 25 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q= 6v5_pas.c index da27d1d3c9da..847249c28c1b 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include #include @@ -118,8 +119,8 @@ struct qcom_pas { struct qcom_rproc_ssr ssr_subdev; struct qcom_sysmon *sysmon; =20 - struct qcom_scm_pas_context *pas_ctx; - struct qcom_scm_pas_context *dtb_pas_ctx; + struct qcom_pas_context *pas_ctx; + struct qcom_pas_context *dtb_pas_ctx; }; =20 static void qcom_pas_segment_dump(struct rproc *rproc, @@ -196,7 +197,7 @@ static int qcom_pas_shutdown_poll_decrypt(struct qcom_p= as *pas) =20 do { msleep(QCOM_PAS_DECRYPT_SHUTDOWN_DELAY_MS); - ret =3D qcom_scm_pas_shutdown(pas->pas_id); + ret =3D qcom_pas_shutdown(pas->pas_id); } while (ret =3D=3D -EINVAL && --retry_num); =20 return ret; @@ -212,9 +213,9 @@ static int qcom_pas_unprepare(struct rproc *rproc) * auth_and_reset() was successful, but in other cases clean it up * here. */ - qcom_scm_pas_metadata_release(pas->pas_ctx); + qcom_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); + qcom_pas_metadata_release(pas->dtb_pas_ctx); =20 return 0; } @@ -228,9 +229,9 @@ static int qcom_pas_load(struct rproc *rproc, const str= uct firmware *fw) pas->firmware =3D fw; =20 if (pas->lite_pas_id) - qcom_scm_pas_shutdown(pas->lite_pas_id); + qcom_pas_shutdown(pas->lite_pas_id); if (pas->lite_dtb_pas_id) - qcom_scm_pas_shutdown(pas->lite_dtb_pas_id); + qcom_pas_shutdown(pas->lite_dtb_pas_id); =20 if (pas->dtb_pas_id) { ret =3D request_firmware(&pas->dtb_firmware, pas->dtb_firmware_name, pas= ->dev); @@ -250,7 +251,7 @@ static int qcom_pas_load(struct rproc *rproc, const str= uct firmware *fw) return 0; =20 release_dtb_metadata: - qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); + qcom_pas_metadata_release(pas->dtb_pas_ctx); release_firmware(pas->dtb_firmware); =20 return ret; @@ -310,7 +311,7 @@ static int qcom_pas_start(struct rproc *rproc) if (ret) goto disable_px_supply; =20 - ret =3D qcom_scm_pas_prepare_and_auth_reset(pas->dtb_pas_ctx); + ret =3D qcom_pas_prepare_and_auth_reset(pas->dtb_pas_ctx); if (ret) { dev_err(pas->dev, "failed to authenticate dtb image and release reset\n"); @@ -329,7 +330,7 @@ static int qcom_pas_start(struct rproc *rproc) if (ret) goto release_pas_metadata; =20 - ret =3D qcom_scm_pas_prepare_and_auth_reset(pas->pas_ctx); + ret =3D qcom_pas_prepare_and_auth_reset(pas->pas_ctx); if (ret) { dev_err(pas->dev, "failed to authenticate image and release reset\n"); @@ -339,13 +340,13 @@ static int qcom_pas_start(struct rproc *rproc) ret =3D qcom_q6v5_wait_for_start(&pas->q6v5, msecs_to_jiffies(5000)); if (ret =3D=3D -ETIMEDOUT) { dev_err(pas->dev, "start timed out\n"); - qcom_scm_pas_shutdown(pas->pas_id); + qcom_pas_shutdown(pas->pas_id); goto unmap_carveout; } =20 - qcom_scm_pas_metadata_release(pas->pas_ctx); + qcom_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); + qcom_pas_metadata_release(pas->dtb_pas_ctx); =20 /* firmware is used to pass reference from qcom_pas_start(), drop it now = */ pas->firmware =3D NULL; @@ -355,9 +356,9 @@ static int qcom_pas_start(struct rproc *rproc) unmap_carveout: qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size); release_pas_metadata: - qcom_scm_pas_metadata_release(pas->pas_ctx); + qcom_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); + qcom_pas_metadata_release(pas->dtb_pas_ctx); =20 unmap_dtb_carveout: if (pas->dtb_pas_id) @@ -406,7 +407,7 @@ static int qcom_pas_stop(struct rproc *rproc) if (ret =3D=3D -ETIMEDOUT) dev_err(pas->dev, "timed out on wait\n"); =20 - ret =3D qcom_scm_pas_shutdown(pas->pas_id); + ret =3D qcom_pas_shutdown(pas->pas_id); if (ret && pas->decrypt_shutdown) ret =3D qcom_pas_shutdown_poll_decrypt(pas); =20 @@ -414,7 +415,7 @@ static int qcom_pas_stop(struct rproc *rproc) dev_err(pas->dev, "failed to shutdown: %d\n", ret); =20 if (pas->dtb_pas_id) { - ret =3D qcom_scm_pas_shutdown(pas->dtb_pas_id); + ret =3D qcom_pas_shutdown(pas->dtb_pas_id); if (ret) dev_err(pas->dev, "failed to shutdown dtb: %d\n", ret); =20 @@ -484,11 +485,11 @@ static int qcom_pas_parse_firmware(struct rproc *rpro= c, const struct firmware *f * * Here, we call rproc_elf_load_rsc_table() to check firmware binary has = resources * or not and if it is not having then we pass NULL and zero as input res= ource - * table pointer and size respectively to the argument of qcom_scm_pas_ge= t_rsc_table() + * table pointer and size respectively to the argument of qcom_pas_get_rs= c_table() * and this is even true for Qualcomm remote processor who does follow re= moteproc * framework. */ - output_rt =3D qcom_scm_pas_get_rsc_table(pas->pas_ctx, table, table_sz, &= output_rt_size); + output_rt =3D qcom_pas_get_rsc_table(pas->pas_ctx, table, table_sz, &outp= ut_rt_size); ret =3D IS_ERR(output_rt) ? PTR_ERR(output_rt) : 0; if (ret) { dev_err(pas->dev, "Error in getting resource table: %d\n", ret); @@ -746,7 +747,7 @@ static int qcom_pas_probe(struct platform_device *pdev) if (!desc) return -EINVAL; =20 - if (!qcom_scm_is_available()) + if (!qcom_pas_is_available()) return -EPROBE_DEFER; =20 fw_name =3D desc->firmware_name; @@ -838,16 +839,16 @@ static int qcom_pas_probe(struct platform_device *pde= v) =20 qcom_add_ssr_subdev(rproc, &pas->ssr_subdev, desc->ssr_name); =20 - pas->pas_ctx =3D devm_qcom_scm_pas_context_alloc(pas->dev, pas->pas_id, - pas->mem_phys, pas->mem_size); + pas->pas_ctx =3D devm_qcom_pas_context_alloc(pas->dev, pas->pas_id, + pas->mem_phys, pas->mem_size); if (IS_ERR(pas->pas_ctx)) { ret =3D PTR_ERR(pas->pas_ctx); goto remove_ssr_sysmon; } =20 - pas->dtb_pas_ctx =3D devm_qcom_scm_pas_context_alloc(pas->dev, pas->dtb_p= as_id, - pas->dtb_mem_phys, - pas->dtb_mem_size); + pas->dtb_pas_ctx =3D devm_qcom_pas_context_alloc(pas->dev, pas->dtb_pas_i= d, + pas->dtb_mem_phys, + pas->dtb_mem_size); if (IS_ERR(pas->dtb_pas_ctx)) { ret =3D PTR_ERR(pas->dtb_pas_ctx); goto remove_ssr_sysmon; --=20 2.51.0 From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B6C63B3BEF; Mon, 27 Apr 2026 09:57:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283873; cv=none; b=r/sxTrJ+UFhFsa05lnU6e4V0A0e/78HLkWkMA9AjuLls7kNRD7mKJB32T7f5BVu+urHAg5onJt9O2k2qequD6Hk725cE5OQJJVuuQIi6OxrH+pWm+mMpmAxZv7uMW8Nm7uRTskL/O2zKyzurXFkvGxqf6PTbW+Bn9CVeX2r1i4Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283873; c=relaxed/simple; bh=5si9p9X+QdKOUj/kEC+OxqljHo6dif086Up1Mo3twcA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; 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charset="utf-8" From: Sumit Garg Switch qcom_q6v5_mss client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Signed-off-by: Sumit Garg Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans --- drivers/remoteproc/qcom_q6v5_mss.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_mss.c b/drivers/remoteproc/qcom_q= 6v5_mss.c index ae78f5c7c1b6..96888007faa8 100644 --- a/drivers/remoteproc/qcom_q6v5_mss.c +++ b/drivers/remoteproc/qcom_q6v5_mss.c @@ -34,6 +34,7 @@ #include "qcom_pil_info.h" #include "qcom_q6v5.h" =20 +#include #include =20 #define MPSS_CRASH_REASON_SMEM 421 @@ -1480,7 +1481,7 @@ static int q6v5_mpss_load(struct q6v5 *qproc) } =20 if (qproc->need_pas_mem_setup) { - ret =3D qcom_scm_pas_mem_setup(MPSS_PAS_ID, qproc->mpss_phys, qproc->mps= s_size); + ret =3D qcom_pas_mem_setup(MPSS_PAS_ID, qproc->mpss_phys, qproc->mpss_si= ze); if (ret) { dev_err(qproc->dev, "setting up mpss memory failed: %d\n", ret); @@ -2077,7 +2078,7 @@ static int q6v5_probe(struct platform_device *pdev) if (!desc) return -EINVAL; =20 - if (desc->need_mem_protection && !qcom_scm_is_available()) + if (desc->need_mem_protection && !qcom_pas_is_available()) return -EPROBE_DEFER; =20 mba_image =3D desc->hexagon_mba_image; --=20 2.51.0 From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 874DA3B4EBF; Mon, 27 Apr 2026 09:58:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283887; cv=none; b=jtm6wM4zaALzajbWponM7CArbYQpui3DMZyRP2cwXei+Nk0BnRtEeL1s0/DZqbCZrVUmjrxjEXirogAbkdFcHu1JDSfosbVhVE/OepoUW51P85LsDecjsVf8AqX4FN54UGGrQytt5qmvSnyGY+nyv9RrVnyk0Qwf9FxrUoTrce0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283887; c=relaxed/simple; bh=VzhDqsiFiUXfxZd81NSur10DXXCFIN3cES5W3dbPI8k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=X7FU6R4ro/nAZvIpSXp3C+CkmyrllAcwuCGDVvmaCdDBd8ASDkBWhz2KI7cy9AwkQwanGIK2z/kPMbzmN34FTnF5bNDk0Lmf90MNkrlj4C1XnUmnO9v+cC6RvdC1ntIwTXkQpeAaT36GFE5wYeINo5HNadGjZR9bzRxGpQYgmXc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=g4+YyAUN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="g4+YyAUN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 673F1C2BCB6; Mon, 27 Apr 2026 09:57:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777283887; bh=VzhDqsiFiUXfxZd81NSur10DXXCFIN3cES5W3dbPI8k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g4+YyAUNRTFiwSXYHbcfYJw6QH6wTznLZljlE2nES+knEuGtg9/d241wLGrfQRSOa TV/lcFFANTiYjyDFbvLdGbWO+fZW1cTUQt7Y293jIuZUDYdnZGw8ajMJNsci92fSw7 5GGvYSqbLQWUq6IYYc4KYAdnjptVJMmAS5NukP4YqeeHafIKNedcgjTnwtaOxPZuzf 1ORfUYVJOk2z1fNStjJuVXrkbpij63TSEEZfWU1pvTfJj43LuxKVllpvoUxlfFjmEZ SBDWDV4sZqjp6skH3gLdg8CKUoL1kZNB4L6Q6Dg8K0VrLgOAKbMFLL1UaHxzmkF1GM Q2DWxmGtR1fWg== From: Sumit Garg To: andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v4 07/15] soc: qcom: mdtloader: Switch to generic PAS TZ APIs Date: Mon, 27 Apr 2026 15:25:55 +0530 Message-ID: <20260427095603.1157963-8-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260427095603.1157963-1-sumit.garg@kernel.org> References: <20260427095603.1157963-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Switch mdtloader client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Signed-off-by: Sumit Garg Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans --- drivers/soc/qcom/mdt_loader.c | 12 ++++++------ include/linux/soc/qcom/mdt_loader.h | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index c004d444d698..fdde7eda538a 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include @@ -229,7 +229,7 @@ EXPORT_SYMBOL_GPL(qcom_mdt_read_metadata); =20 static int __qcom_mdt_pas_init(struct device *dev, const struct firmware *= fw, const char *fw_name, int pas_id, phys_addr_t mem_phys, - struct qcom_scm_pas_context *ctx) + struct qcom_pas_context *ctx) { const struct elf32_phdr *phdrs; const struct elf32_phdr *phdr; @@ -271,7 +271,7 @@ static int __qcom_mdt_pas_init(struct device *dev, cons= t struct firmware *fw, goto out; } =20 - ret =3D qcom_scm_pas_init_image(pas_id, metadata, metadata_len, ctx); + ret =3D qcom_pas_init_image(pas_id, metadata, metadata_len, ctx); kfree(metadata); if (ret) { /* Invalid firmware metadata */ @@ -280,7 +280,7 @@ static int __qcom_mdt_pas_init(struct device *dev, cons= t struct firmware *fw, } =20 if (relocate) { - ret =3D qcom_scm_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr); + ret =3D qcom_pas_mem_setup(pas_id, mem_phys, max_addr - min_addr); if (ret) { /* Unable to set up relocation */ dev_err(dev, "error %d setting up firmware %s\n", ret, fw_name); @@ -472,7 +472,7 @@ EXPORT_SYMBOL_GPL(qcom_mdt_load); * firmware segments (e.g., .bXX files). Authentication of the segments do= ne * by a separate call. * - * The PAS context must be initialized using qcom_scm_pas_context_init() + * The PAS context must be initialized using qcom_pas_context_init() * prior to invoking this function. * * @ctx: Pointer to the PAS (Peripheral Authentication Service) con= text @@ -483,7 +483,7 @@ EXPORT_SYMBOL_GPL(qcom_mdt_load); * * Return: 0 on success or a negative error code on failure. */ -int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmw= are *fw, +int qcom_mdt_pas_load(struct qcom_pas_context *ctx, const struct firmware = *fw, const char *firmware, void *mem_region, phys_addr_t *reloc_base) { int ret; diff --git a/include/linux/soc/qcom/mdt_loader.h b/include/linux/soc/qcom/m= dt_loader.h index 82372e0db0a1..142409555425 100644 --- a/include/linux/soc/qcom/mdt_loader.h +++ b/include/linux/soc/qcom/mdt_loader.h @@ -10,7 +10,7 @@ =20 struct device; struct firmware; -struct qcom_scm_pas_context; +struct qcom_pas_context; =20 #if IS_ENABLED(CONFIG_QCOM_MDT_LOADER) =20 @@ -20,7 +20,7 @@ int qcom_mdt_load(struct device *dev, const struct firmwa= re *fw, phys_addr_t mem_phys, size_t mem_size, phys_addr_t *reloc_base); =20 -int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, const struct firmw= are *fw, +int qcom_mdt_pas_load(struct qcom_pas_context *ctx, const struct firmware = *fw, const char *firmware, void *mem_region, phys_addr_t *reloc_base); =20 int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw, @@ -45,7 +45,7 @@ static inline int qcom_mdt_load(struct device *dev, const= struct firmware *fw, return -ENODEV; } =20 -static inline int qcom_mdt_pas_load(struct qcom_scm_pas_context *ctx, +static inline int qcom_mdt_pas_load(struct qcom_pas_context *ctx, const struct firmware *fw, const char *firmware, void *mem_region, phys_addr_t *reloc_base) { --=20 2.51.0 From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C48293B3C0F; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QIJBnvj9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DB698C2BCB9; Mon, 27 Apr 2026 09:58:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777283901; bh=6sMeataN91v3DK2/OM6RN4V1kVMHnyLiK0yE4PVQrP8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QIJBnvj9TWNnO1BxOeV3F4HfjzJvi5lYnjzVZPbWoPEV8NmZMmomZdNKn1q//4NFF gY7/hsDB4Z9GSOqC5FjMb9L0B0v3qmHnSL+bbQ3z4YAl+iFf7jjJJXffeCjSvWCqUp QNi03y38ZZUSDAUK8Ff89rbX3XSSQOxTHOf1bB1LU2efUXEBECqcH/YRjWD9PcAuX9 CEoK6dMwiuZeBZp+z91AUCKY5d90Q+LDM+rSLAc8Rzm7MQzNYJnSdHfumLkmGuqpv7 Wz4NErgjv6RaI420T7gEivkkYea9uEcNz26h/wT5qmX8u1oPpns5/jst6Gp1XWaPV7 l2aH+YIze1ShA== From: Sumit Garg To: andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v4 08/15] remoteproc: qcom_wcnss: Switch to generic PAS TZ APIs Date: Mon, 27 Apr 2026 15:25:56 +0530 Message-ID: <20260427095603.1157963-9-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260427095603.1157963-1-sumit.garg@kernel.org> References: <20260427095603.1157963-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Switch qcom_wcnss client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Signed-off-by: Sumit Garg Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans --- drivers/remoteproc/qcom_wcnss.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/remoteproc/qcom_wcnss.c b/drivers/remoteproc/qcom_wcns= s.c index 4add9037dbd5..0dbdd18ab3dd 100644 --- a/drivers/remoteproc/qcom_wcnss.c +++ b/drivers/remoteproc/qcom_wcnss.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include #include @@ -257,7 +257,7 @@ static int wcnss_start(struct rproc *rproc) wcnss_indicate_nv_download(wcnss); wcnss_configure_iris(wcnss); =20 - ret =3D qcom_scm_pas_auth_and_reset(WCNSS_PAS_ID); + ret =3D qcom_pas_auth_and_reset(WCNSS_PAS_ID); if (ret) { dev_err(wcnss->dev, "failed to authenticate image and release reset\n"); @@ -269,7 +269,7 @@ static int wcnss_start(struct rproc *rproc) if (wcnss->ready_irq > 0 && ret =3D=3D 0) { /* We have a ready_irq, but it didn't fire in time. */ dev_err(wcnss->dev, "start timed out\n"); - qcom_scm_pas_shutdown(WCNSS_PAS_ID); + qcom_pas_shutdown(WCNSS_PAS_ID); ret =3D -ETIMEDOUT; goto disable_iris; } @@ -311,7 +311,7 @@ static int wcnss_stop(struct rproc *rproc) 0); } =20 - ret =3D qcom_scm_pas_shutdown(WCNSS_PAS_ID); + ret =3D qcom_pas_shutdown(WCNSS_PAS_ID); if (ret) dev_err(wcnss->dev, "failed to shutdown: %d\n", ret); =20 @@ -557,10 +557,10 @@ static int wcnss_probe(struct platform_device *pdev) =20 data =3D of_device_get_match_data(&pdev->dev); =20 - if (!qcom_scm_is_available()) + if (!qcom_pas_is_available()) return -EPROBE_DEFER; =20 - if (!qcom_scm_pas_supported(WCNSS_PAS_ID)) { + if (!qcom_pas_supported(WCNSS_PAS_ID)) { dev_err(&pdev->dev, "PAS is not available for WCNSS\n"); return -ENXIO; } --=20 2.51.0 From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2B5903B0ACA; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="poZiuXQa" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1CCB0C2BCB4; Mon, 27 Apr 2026 09:58:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777283915; bh=xYlvJO+JflPgYH7lV81mrAxzP35EX+W421jGEAyidpM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=poZiuXQaK+RMtf7K2aOlAUJi4kCbFFBuAtE8LsuQaL73aE65NbJ832nqq0RwR74jN BV4kY+BPz3ughnNyUdsvqIlQ5EMHiFhzjJBF9Aokuew+S+s2+U3Mp9+yhSs6CE8y6p FR0BPZxUU9d+pSSJ3alTf/lO7p1F6D2bOqfQe6zpZnQyRSfJgp4xGJ8T3zefDswcml GpOxyuLDmr5TzuICuLCUKBiBBBt2xI6w6peUGOVpEmrUKpSWzkw38p8rjZLC4naGoK zek/cp3u22URZRBVte6v2qcCju0lFb8E5b1ev4X/9Q6ehAg4NDRYZEaVnczI+RuWlK xPM7/7NBSWing== From: Sumit Garg To: andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v4 09/15] remoteproc: qcom: Select QCOM_PAS generic service Date: Mon, 27 Apr 2026 15:25:57 +0530 Message-ID: <20260427095603.1157963-10-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260427095603.1157963-1-sumit.garg@kernel.org> References: <20260427095603.1157963-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Select PAS generic service driver to enable support for multiple PAS backends like OP-TEE in addition to SCM. Signed-off-by: Sumit Garg Tested-by: Mukesh Ojha # Lemans --- drivers/remoteproc/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index ee54436fea5a..da3c5d9562ea 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -230,6 +230,7 @@ config QCOM_Q6V5_PAS select QCOM_Q6V5_COMMON select QCOM_RPROC_COMMON select QCOM_SCM + select QCOM_PAS help Say y here to support the TrustZone based Peripheral Image Loader for the Qualcomm remote processors. This is commonly used to control --=20 2.51.0 From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAFF73B0ACA; Mon, 27 Apr 2026 09:58:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283930; cv=none; b=O+n+vYACu1SAB9INXPObCHv3oEggWc2MQW3wyG+f+9j4Jv2766e3/5eFD1OrJw0hnAuy2OK06bjQLfWiUxVK8EHSf/3sguFCSESEmO7NiLmfTbYTbpMsYf0kO5I7EX0q87ql7i2VhwXd/Vjdzu1CFwy4hW+oVzVjnjU83DjrWCY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283930; c=relaxed/simple; bh=J4HLesdTxZiOmSnG4cnDWRHJXWd/P5xqcY0bR8WnNJ8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uGDC4w6/bTdT2/k0xbxnYk+Lf8PUYWXeVzAEkEeShVOXPc/67wYPShQJC65kadgJ6mwSkw6OLZprNE+rTrnoYN/LPBhK1f+JfiSHeVTGGsRZvwEgmaWbA4L9/lGz8S1me8adZGEYOfyj4RtTXP0Pfnu8Hloy80JdPKHK54QMBgU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oj2FsikU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oj2FsikU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F43CC2BCB6; Mon, 27 Apr 2026 09:58:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777283930; bh=J4HLesdTxZiOmSnG4cnDWRHJXWd/P5xqcY0bR8WnNJ8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oj2FsikUqt/Gx83Ruzgqb4I4oRuBnjiEWRzwEndq2ttmcFbIauNVNe9r8tvowWUAF OQ6VTL9C4FxpcZFsNy8RMMu2VvDrRh5OuGQF61IN5G3AxUzgQkmUxFuLFe8cP1vY4g GLE3bK5qRfwa5zernMpQyZYRtP9ytwYnjkhH0b7A3ewciP8gXAJY7lgI744XYJ2eJJ QRlcM5sHKUt93OBkQY02nRronUbny/gHF2Mvjif/cALltv9IMjlu/Q9/yutDgmzy3e pjdHcu4s4i6FMY3bVr5S+8RySO92v377wBlEl0iXuY8jRNDK7eNOF/KgEYwkxHpbIA Hr7QJGcSV5H5A== From: Sumit Garg To: andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg , Dmitry Baryshkov Subject: [PATCH v4 10/15] drm/msm: Switch to generic PAS TZ APIs Date: Mon, 27 Apr 2026 15:25:58 +0530 Message-ID: <20260427095603.1157963-11-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260427095603.1157963-1-sumit.garg@kernel.org> References: <20260427095603.1157963-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Switch drm/msm client drivers over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Acked-by: Dmitry Baryshkov Signed-off-by: Sumit Garg Reviewed-by: Mukesh Ojha =20 Tested-by: Mukesh Ojha # Lemans --- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 ++++++----- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 250246f81ea9..09469d56513b 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -21,6 +21,7 @@ config DRM_MSM select SHMEM select TMPFS select QCOM_SCM + select QCOM_PAS select QCOM_UBWC_CONFIG select WANT_DEV_COREDUMP select SND_SOC_HDMI_CODEC if SND_SOC diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a5xx_gpu.c index 79acae11154a..b556da823897 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -5,7 +5,7 @@ #include #include #include -#include +#include #include #include #include @@ -653,7 +653,7 @@ static int a5xx_zap_shader_resume(struct msm_gpu *gpu) if (adreno_is_a506(adreno_gpu)) return 0; =20 - ret =3D qcom_scm_set_remote_state(SCM_GPU_ZAP_SHADER_RESUME, GPU_PAS_ID); + ret =3D qcom_pas_set_remote_state(SCM_GPU_ZAP_SHADER_RESUME, GPU_PAS_ID); if (ret) DRM_ERROR("%s: zap-shader resume failed: %d\n", gpu->name, ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/= adreno/adreno_gpu.c index 66f80f2d12f9..6d68edf0578c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -8,6 +8,7 @@ =20 #include #include +#include #include #include #include @@ -146,10 +147,10 @@ static int zap_shader_load_mdt(struct msm_gpu *gpu, c= onst char *fwname, goto out; =20 /* Send the image to the secure world */ - ret =3D qcom_scm_pas_auth_and_reset(pasid); + ret =3D qcom_pas_auth_and_reset(pasid); =20 /* - * If the scm call returns -EOPNOTSUPP we assume that this target + * If the pas call returns -EOPNOTSUPP we assume that this target * doesn't need/support the zap shader so quietly fail */ if (ret =3D=3D -EOPNOTSUPP) @@ -175,9 +176,9 @@ int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pas= id) if (!zap_available) return -ENODEV; =20 - /* We need SCM to be able to load the firmware */ - if (!qcom_scm_is_available()) { - DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n"); + /* We need PAS to be able to load the firmware */ + if (!qcom_pas_is_available()) { + DRM_DEV_ERROR(&pdev->dev, "Qcom PAS is not available\n"); return -EPROBE_DEFER; } =20 --=20 2.51.0 From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA3F93B3C01; Mon, 27 Apr 2026 09:59:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283945; cv=none; b=i2MSl/VssJy+3/ME3mLze4ROSu7BDC6jjLFZ/cWfyEhuka4TpbQte+6k1TFFwenZbuH3CjxgjmXV+iIvm3UTyv3A1JjYPMdoHlszqc2b2U0PHrcsDbewkK0o+n5vqqBAAf4L0taXtvwF8qWAohdnLVTq/Eq33bSOy3lyod1D1O4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283945; c=relaxed/simple; bh=Ni6+wg4CR6E+75Ru3q2zrAVZ+Yap1oo6S9oO07k3EVk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=rJHnauLybz2HEYl3Ykkguq1BFl7yakm9hudZp9P0Z1q+BUSIk7eF+Wc/eTDjWshUw0OD0JEgPbMQ1TgqsbS+Gstzn7bvJJ6f1O+yL/H0z5KaiW4zDNbXLPlfLQ+jMaTzmqFvDBYUX+glAGLtli4IW+XzOAp2RjMIHE4Su2CgyVQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=dgaN450e; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="dgaN450e" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F12E8C19425; Mon, 27 Apr 2026 09:58:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777283944; bh=Ni6+wg4CR6E+75Ru3q2zrAVZ+Yap1oo6S9oO07k3EVk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dgaN450e0h0ICI9z944ifTNLQJwmjEeYSEBdBvF6ZqC3UIoeruB+X2ZUV5qh7oF0D HQsUx5Ea47XQdP9M0cn3MTvrUhqYrPLKyc9xwOF/eeqGJJ3wbY0I/lsyqdgKavMu8R V87hh8KKO6fLOWdtH5LwZMVnc3J+BKY+4fK+HyYkZ2SVexOLUCVCXxWIezNaz//2JN 4q25yPh1sIPUwqQdxbFNnjWS8Un3M81YhQ+Rsytemwd1aIsW1fB7gyWXrjKCroFdFr i3yzSzpTjx7MeY/DAxQBsulaB7HEoVJ7EFvTbNOWsbo95O3HZgO6PwaB4a63b3DODk J5MyXpUV9LaSA== From: Sumit Garg To: andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v4 11/15] media: qcom: Switch to generic PAS TZ APIs Date: Mon, 27 Apr 2026 15:25:59 +0530 Message-ID: <20260427095603.1157963-12-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260427095603.1157963-1-sumit.garg@kernel.org> References: <20260427095603.1157963-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Switch qcom media client drivers over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Along with that pass proper PAS ID to set_remote_state API. As per testing the SCM backend just ignores it while OP-TEE makes use of it to for proper book keeping purpose. Signed-off-by: Sumit Garg Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans --- drivers/media/platform/qcom/iris/Kconfig | 25 ++++++++++--------- .../media/platform/qcom/iris/iris_firmware.c | 9 ++++--- drivers/media/platform/qcom/venus/Kconfig | 1 + drivers/media/platform/qcom/venus/firmware.c | 11 ++++---- 4 files changed, 25 insertions(+), 21 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Kconfig b/drivers/media/platf= orm/qcom/iris/Kconfig index 3c803a05305a..f54b759c18aa 100644 --- a/drivers/media/platform/qcom/iris/Kconfig +++ b/drivers/media/platform/qcom/iris/Kconfig @@ -1,13 +1,14 @@ config VIDEO_QCOM_IRIS - tristate "Qualcomm iris V4L2 decoder driver" - depends on VIDEO_DEV - depends on ARCH_QCOM || COMPILE_TEST - select V4L2_MEM2MEM_DEV - select QCOM_MDT_LOADER if ARCH_QCOM - select QCOM_SCM - select VIDEOBUF2_DMA_CONTIG - help - This is a V4L2 driver for Qualcomm iris video accelerator - hardware. It accelerates decoding operations on various - Qualcomm SoCs. - To compile this driver as a module choose m here. + tristate "Qualcomm iris V4L2 decoder driver" + depends on VIDEO_DEV + depends on ARCH_QCOM || COMPILE_TEST + select V4L2_MEM2MEM_DEV + select QCOM_MDT_LOADER if ARCH_QCOM + select QCOM_SCM + select QCOM_PAS + select VIDEOBUF2_DMA_CONTIG + help + This is a V4L2 driver for Qualcomm iris video accelerator + hardware. It accelerates decoding operations on various + Qualcomm SoCs. + To compile this driver as a module choose m here. diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/med= ia/platform/qcom/iris/iris_firmware.c index 5f408024e967..856fa6a79064 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -4,6 +4,7 @@ */ =20 #include +#include #include #include #include @@ -79,7 +80,7 @@ int iris_fw_load(struct iris_core *core) return -ENOMEM; } =20 - ret =3D qcom_scm_pas_auth_and_reset(core->iris_platform_data->pas_id); + ret =3D qcom_pas_auth_and_reset(core->iris_platform_data->pas_id); if (ret) { dev_err(core->dev, "auth and reset failed: %d\n", ret); return ret; @@ -93,7 +94,7 @@ int iris_fw_load(struct iris_core *core) cp_config->cp_nonpixel_size); if (ret) { dev_err(core->dev, "qcom_scm_mem_protect_video_var failed: %d\n", ret); - qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); + qcom_pas_shutdown(core->iris_platform_data->pas_id); return ret; } } @@ -103,10 +104,10 @@ int iris_fw_load(struct iris_core *core) =20 int iris_fw_unload(struct iris_core *core) { - return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); + return qcom_pas_shutdown(core->iris_platform_data->pas_id); } =20 int iris_set_hw_state(struct iris_core *core, bool resume) { - return qcom_scm_set_remote_state(resume, 0); + return qcom_pas_set_remote_state(resume, core->iris_platform_data->pas_id= ); } diff --git a/drivers/media/platform/qcom/venus/Kconfig b/drivers/media/plat= form/qcom/venus/Kconfig index ffb731ecd48c..574172724e8f 100644 --- a/drivers/media/platform/qcom/venus/Kconfig +++ b/drivers/media/platform/qcom/venus/Kconfig @@ -6,6 +6,7 @@ config VIDEO_QCOM_VENUS select OF_DYNAMIC if ARCH_QCOM select QCOM_MDT_LOADER if ARCH_QCOM select QCOM_SCM + select QCOM_PAS select VIDEOBUF2_DMA_CONTIG select V4L2_MEM2MEM_DEV help diff --git a/drivers/media/platform/qcom/venus/firmware.c b/drivers/media/p= latform/qcom/venus/firmware.c index 1de7436713ed..3c0727ea137d 100644 --- a/drivers/media/platform/qcom/venus/firmware.c +++ b/drivers/media/platform/qcom/venus/firmware.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -58,7 +59,7 @@ int venus_set_hw_state(struct venus_core *core, bool resu= me) int ret; =20 if (core->use_tz) { - ret =3D qcom_scm_set_remote_state(resume, 0); + ret =3D qcom_pas_set_remote_state(resume, VENUS_PAS_ID); if (resume && ret =3D=3D -EINVAL) ret =3D 0; return ret; @@ -218,7 +219,7 @@ int venus_boot(struct venus_core *core) int ret; =20 if (!IS_ENABLED(CONFIG_QCOM_MDT_LOADER) || - (core->use_tz && !qcom_scm_is_available())) + (core->use_tz && !qcom_pas_is_available())) return -EPROBE_DEFER; =20 ret =3D of_property_read_string_index(dev->of_node, "firmware-name", 0, @@ -236,7 +237,7 @@ int venus_boot(struct venus_core *core) core->fw.mem_phys =3D mem_phys; =20 if (core->use_tz) - ret =3D qcom_scm_pas_auth_and_reset(VENUS_PAS_ID); + ret =3D qcom_pas_auth_and_reset(VENUS_PAS_ID); else ret =3D venus_boot_no_tz(core, mem_phys, mem_size); =20 @@ -259,7 +260,7 @@ int venus_boot(struct venus_core *core) res->cp_nonpixel_start, res->cp_nonpixel_size); if (ret) { - qcom_scm_pas_shutdown(VENUS_PAS_ID); + qcom_pas_shutdown(VENUS_PAS_ID); dev_err(dev, "set virtual address ranges fail (%d)\n", ret); return ret; @@ -274,7 +275,7 @@ int venus_shutdown(struct venus_core *core) int ret; =20 if (core->use_tz) - ret =3D qcom_scm_pas_shutdown(VENUS_PAS_ID); + ret =3D qcom_pas_shutdown(VENUS_PAS_ID); else ret =3D venus_shutdown_no_tz(core); =20 --=20 2.51.0 From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D024C3B3BE9; Mon, 27 Apr 2026 09:59:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283958; cv=none; b=XED/x+7NwFoPl0pPbW91v6ynWlc8a/CQIRSikRvuYnN7H0nKSR8jxzQ1lhU8f8caa/DE7sfrNjydd2iw6Sh9WLtjnAiFPzNHITO5htPUOGHOVH918Qm9aIC71xbV83QD104OvauQZwb44nOl/Qp/VtwDLXLDZYaTAh185VZ219I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777283958; c=relaxed/simple; bh=RSNfV6exKvq+zvrQNX0xnasMhRBhyfJlznDBh2Dgzrw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=fmA+A6x3s/f5TQxnLEx49Rn5POhk+tvtQ6vqk8kBdd6sBPlMH7Wsg+i1VpckXF9xlBL5GyOkLpc907UL598AR8Tcz03DKUoyOykVD60ErpXPMcHy8Pd8d9P0vAXCgk9YWcY6gFRLOthuQnUBQk7pXylAvSIzr7mvUabewsaSiqo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=k7T+CluJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="k7T+CluJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 29349C19425; Mon, 27 Apr 2026 09:59:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777283958; bh=RSNfV6exKvq+zvrQNX0xnasMhRBhyfJlznDBh2Dgzrw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=k7T+CluJITwcmx+92RW90GFd92ds95jYeXpF9w/0XmknR12IOZrYP4d+yeWTeM3mw annKV+extW0h61NMyHURgvXxInfhgO2JyApexZfRe3LgfvWs1EP8nk+l+DO5tY0dan f/5+cfiwk2m4f8CvONTA2kAkEh2vqF1iKpHdPjKcHhSn4TCFcCmX0srwT+CaigH7Dc f0Bb4P4S3x8QMJ+UWqqXXU7t4UBaBhqa3s61NQrh5k1OUgZlq+s8RA6VQ8e9kM4Amb 6u4lR6iNN+4PDx47rHgt6jCqx0CRx+LA2nc4tnELJ9yxwwA+gO4NagRzAqpHoOTfWV hZPICunebgEDw== From: Sumit Garg To: andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v4 12/15] net: ipa: Switch to generic PAS TZ APIs Date: Mon, 27 Apr 2026 15:26:00 +0530 Message-ID: <20260427095603.1157963-13-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260427095603.1157963-1-sumit.garg@kernel.org> References: <20260427095603.1157963-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Switch ipa client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Signed-off-by: Sumit Garg Reviewed-by: Alex Elder Tested-by: Mukesh Ojha # Lemans --- drivers/net/ipa/Kconfig | 2 +- drivers/net/ipa/ipa_main.c | 13 ++++++++----- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/net/ipa/Kconfig b/drivers/net/ipa/Kconfig index 01d219d3760c..a9aff1b7977d 100644 --- a/drivers/net/ipa/Kconfig +++ b/drivers/net/ipa/Kconfig @@ -6,7 +6,7 @@ config QCOM_IPA depends on QCOM_RPROC_COMMON || (QCOM_RPROC_COMMON=3Dn && COMPILE_TEST) depends on QCOM_AOSS_QMP || QCOM_AOSS_QMP=3Dn select QCOM_MDT_LOADER - select QCOM_SCM + select QCOM_PAS select QCOM_QMI_HELPERS help Choose Y or M here to include support for the Qualcomm diff --git a/drivers/net/ipa/ipa_main.c b/drivers/net/ipa/ipa_main.c index 788dd99af2a4..3cd9e44680e9 100644 --- a/drivers/net/ipa/ipa_main.c +++ b/drivers/net/ipa/ipa_main.c @@ -14,7 +14,7 @@ #include #include =20 -#include +#include #include =20 #include "ipa.h" @@ -624,10 +624,13 @@ static int ipa_firmware_load(struct device *dev) } =20 ret =3D qcom_mdt_load(dev, fw, path, IPA_PAS_ID, virt, phys, size, NULL); - if (ret) + if (ret) { dev_err(dev, "error %d loading \"%s\"\n", ret, path); - else if ((ret =3D qcom_scm_pas_auth_and_reset(IPA_PAS_ID))) - dev_err(dev, "error %d authenticating \"%s\"\n", ret, path); + } else { + ret =3D qcom_pas_auth_and_reset(IPA_PAS_ID); + if (ret) + dev_err(dev, "error %d authenticating \"%s\"\n", ret, path); + } =20 memunmap(virt); out_release_firmware: @@ -758,7 +761,7 @@ static enum ipa_firmware_loader ipa_firmware_loader(str= uct device *dev) return IPA_LOADER_INVALID; out_self: /* We need Trust Zone to load firmware; make sure it's available */ - if (qcom_scm_is_available()) + if (qcom_pas_is_available()) return IPA_LOADER_SELF; =20 return IPA_LOADER_DEFER; --=20 2.51.0 From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0872839FCC4; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QVDKeuun" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5753DC2BCB6; Mon, 27 Apr 2026 09:59:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777283972; bh=hXxx+4QUgMOw3htf/QGDwyguBASyu2uqZ06knOuCGaA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QVDKeuunL76HM1861au4fRPSLOyaDFWyKt4ECY432CoPxvvp0x4XVh2Tpuv+CYTEK vcx4tgtwsm2mSL1EePtBXXBl5vXCPAU+XvsSF0GO2Mn7wWDBT8C6vekkVrsbDVkImj B2VWX7AqTfEvbl/VlP5LZwvHsTcSLsE/EEPEz5sJFFCuLA4vJ3fsoGfWsqBmjnOHFI wy2UyLTcDIDKsCmdPud8yfCvcUYbJWNnqRZtni3f7w97FvXi8/IOruHhF/uPcqvG5k OAgpCeXdq1qC/8h1oI04a/S3VEf9/7duELX0Q00AfqmHjcZuMxCquCijDU75ch78hP xJB6V3R9Czn9Q== From: Sumit Garg To: andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v4 13/15] wifi: ath12k: Switch to generic PAS TZ APIs Date: Mon, 27 Apr 2026 15:26:01 +0530 Message-ID: <20260427095603.1157963-14-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260427095603.1157963-1-sumit.garg@kernel.org> References: <20260427095603.1157963-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Switch ath12k client driver over to generic PAS TZ APIs. Generic PAS TZ service allows to support multiple TZ implementation backends like QTEE based SCM PAS service, OP-TEE based PAS service and any further future TZ backend service. Acked-by: Jeff Johnson Signed-off-by: Sumit Garg Tested-by: Mukesh Ojha # Lemans --- drivers/net/wireless/ath/ath12k/Kconfig | 2 +- drivers/net/wireless/ath/ath12k/ahb.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/wireless/ath/ath12k/Kconfig b/drivers/net/wireless= /ath/ath12k/Kconfig index d39c075758bd..2b8b87931330 100644 --- a/drivers/net/wireless/ath/ath12k/Kconfig +++ b/drivers/net/wireless/ath/ath12k/Kconfig @@ -18,7 +18,7 @@ config ATH12K_AHB bool "QTI ath12k AHB support" depends on ATH12K && REMOTEPROC select QCOM_MDT_LOADER - select QCOM_SCM + select QCOM_PAS help Enable support for Ath12k AHB bus chipsets, example IPQ5332. =20 diff --git a/drivers/net/wireless/ath/ath12k/ahb.c b/drivers/net/wireless/a= th/ath12k/ahb.c index 2dcf0a52e4c1..c5ba91e6f95e 100644 --- a/drivers/net/wireless/ath/ath12k/ahb.c +++ b/drivers/net/wireless/ath/ath12k/ahb.c @@ -5,7 +5,7 @@ */ =20 #include -#include +#include #include #include #include @@ -420,7 +420,7 @@ static int ath12k_ahb_power_up(struct ath12k_base *ab) =20 if (ab_ahb->scm_auth_enabled) { /* Authenticate FW image using peripheral ID */ - ret =3D qcom_scm_pas_auth_and_reset(pasid); + ret =3D qcom_pas_auth_and_reset(pasid); if (ret) { ath12k_err(ab, "failed to boot the remote processor %d\n", ret); goto err_fw2; @@ -485,9 +485,9 @@ static void ath12k_ahb_power_down(struct ath12k_base *a= b, bool is_suspend) pasid =3D (u32_encode_bits(ab_ahb->userpd_id, ATH12K_USERPD_ID_MASK)) | ATH12K_AHB_UPD_SWID; /* Release the firmware */ - ret =3D qcom_scm_pas_shutdown(pasid); + ret =3D qcom_pas_shutdown(pasid); if (ret) - ath12k_err(ab, "scm pas shutdown failed for userPD%d\n", + ath12k_err(ab, "pas shutdown failed for userPD%d: %d\n", ab_ahb->userpd_id); } } --=20 2.51.0 From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2534F3B634E; Mon, 27 Apr 2026 09:59:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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Mon, 27 Apr 2026 09:59:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777283987; bh=2kVIdCewqrWUGMzQzXyJVUFLeH6Ou1nMji+gPo6PG4A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Maij94Rs/RbIWoR9L7Ig6bbQn6AFmWhfeKgctH+MJxun9zx39QlN/eUqU+dTQ14fM ynwOoz+Rq9QpLJwA6AoLpkPYIWPCV8YF4zC6WaVJXHpJm2sf9CFHj47HiMgVbbq5Tx whLNJmuVUT/0heOtM3XbF9h07jsE/YX0jQ98khloP5HwOrmZ4EE7YwJWuM+A/wHK/d zgPRh4CqTXqWb6cWXl6L1ejGI+2fBV3TOGCgY58yjEPVUeQF5+8Zfk3y89XNK1dwQb ONyotvEinRvSmXr0ogy1tZSClSyls+SxZ2oMCmhMTKuEpMtk4bjv6dvSGfUVzVQH+L V8LJSMfRWUhEw== From: Sumit Garg To: andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v4 14/15] firmware: qcom_scm: Remove SCM PAS wrappers Date: Mon, 27 Apr 2026 15:26:02 +0530 Message-ID: <20260427095603.1157963-15-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260427095603.1157963-1-sumit.garg@kernel.org> References: <20260427095603.1157963-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Now since all the Qcom SCM client drivers have been migrated over to generic PAS TZ service, let's drop the exported SCM PAS wrappers. Signed-off-by: Sumit Garg Reviewed-by: Mukesh Ojha Tested-by: Mukesh Ojha # Lemans --- drivers/firmware/qcom/qcom_scm.c | 143 +++++-------------------- include/linux/firmware/qcom/qcom_scm.h | 29 ----- 2 files changed, 29 insertions(+), 143 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index d87a962e93da..2493b200696b 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -553,26 +553,6 @@ static void qcom_scm_set_download_mode(u32 dload_mode) dev_err(__scm->dev, "failed to set download mode: %d\n", ret); } =20 -struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device= *dev, - u32 pas_id, - phys_addr_t mem_phys, - size_t mem_size) -{ - struct qcom_pas_context *ctx; - - ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return ERR_PTR(-ENOMEM); - - ctx->dev =3D dev; - ctx->pas_id =3D pas_id; - ctx->mem_phys =3D mem_phys; - ctx->mem_size =3D mem_size; - - return (struct qcom_scm_pas_context *)ctx; -} -EXPORT_SYMBOL_GPL(devm_qcom_scm_pas_context_alloc); - static int __qcom_scm_pas_init_image(struct device *dev, u32 pas_id, dma_addr_t mdata_phys, struct qcom_scm_res *res) @@ -630,9 +610,9 @@ static int qcom_scm_pas_prep_and_init_image(struct devi= ce *dev, return ret ? : res.result[0]; } =20 -static int __qcom_scm_pas_init_image2(struct device *dev, u32 pas_id, - const void *metadata, size_t size, - struct qcom_pas_context *ctx) +static int qcom_scm_pas_init_image(struct device *dev, u32 pas_id, + const void *metadata, size_t size, + struct qcom_pas_context *ctx) { struct qcom_scm_res res; dma_addr_t mdata_phys; @@ -672,16 +652,8 @@ static int __qcom_scm_pas_init_image2(struct device *d= ev, u32 pas_id, return ret ? : res.result[0]; } =20 -int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size, - struct qcom_scm_pas_context *ctx) -{ - return __qcom_scm_pas_init_image2(__scm->dev, pas_id, metadata, size, - (struct qcom_pas_context *)ctx); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image); - -static void __qcom_scm_pas_metadata_release(struct device *dev, - struct qcom_pas_context *ctx) +static void qcom_scm_pas_metadata_release(struct device *dev, + struct qcom_pas_context *ctx) { if (ctx->use_tzmem) qcom_tzmem_free(ctx->ptr); @@ -691,15 +663,8 @@ static void __qcom_scm_pas_metadata_release(struct dev= ice *dev, ctx->ptr =3D NULL; } =20 -void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx) -{ - __qcom_scm_pas_metadata_release(__scm->dev, - (struct qcom_pas_context *)ctx); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release); - -static int __qcom_scm_pas_mem_setup(struct device *dev, u32 pas_id, - phys_addr_t addr, phys_addr_t size) +static int qcom_scm_pas_mem_setup(struct device *dev, u32 pas_id, + phys_addr_t addr, phys_addr_t size) { int ret; struct qcom_scm_desc desc =3D { @@ -730,12 +695,6 @@ static int __qcom_scm_pas_mem_setup(struct device *dev= , u32 pas_id, return ret ? : res.result[0]; } =20 -int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size) -{ - return __qcom_scm_pas_mem_setup(__scm->dev, pas_id, addr, size); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup); - static void *__qcom_scm_pas_get_rsc_table(struct device *dev, u32 pas_id, void *input_rt_tzm, size_t input_rt_size, @@ -789,11 +748,10 @@ static void *__qcom_scm_pas_get_rsc_table(struct devi= ce *dev, u32 pas_id, return ret ? ERR_PTR(ret) : output_rt_tzm; } =20 -static void *__qcom_scm_pas_get_rsc_table2(struct device *dev, - struct qcom_pas_context *ctx, - void *input_rt, - size_t input_rt_size, - size_t *output_rt_size) +static void *qcom_scm_pas_get_rsc_table(struct device *dev, + struct qcom_pas_context *ctx, + void *input_rt, size_t input_rt_size, + size_t *output_rt_size) { struct resource_table empty_rsc =3D {}; size_t size =3D SZ_16K; @@ -864,19 +822,7 @@ static void *__qcom_scm_pas_get_rsc_table2(struct devi= ce *dev, return ret ? ERR_PTR(ret) : tbl_ptr; } =20 -struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_cont= ext *ctx, - void *input_rt, - size_t input_rt_size, - size_t *output_rt_size) -{ - return __qcom_scm_pas_get_rsc_table2(__scm->dev, - (struct qcom_pas_context *)ctx, - input_rt, input_rt_size, - output_rt_size); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_get_rsc_table); - -static int __qcom_scm_pas_auth_and_reset(struct device *dev, u32 pas_id) +static int qcom_scm_pas_auth_and_reset(struct device *dev, u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { @@ -905,14 +851,8 @@ static int __qcom_scm_pas_auth_and_reset(struct device= *dev, u32 pas_id) return ret ? : res.result[0]; } =20 -int qcom_scm_pas_auth_and_reset(u32 pas_id) -{ - return __qcom_scm_pas_auth_and_reset(__scm->dev, pas_id); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset); - -static int __qcom_scm_pas_prepare_and_auth_reset(struct device *dev, - struct qcom_pas_context *ctx) +static int qcom_scm_pas_prepare_and_auth_reset(struct device *dev, + struct qcom_pas_context *ctx) { u64 handle; int ret; @@ -923,7 +863,7 @@ static int __qcom_scm_pas_prepare_and_auth_reset(struct= device *dev, * memory region and then invokes a call to TrustZone to authenticate. */ if (!ctx->use_tzmem) - return __qcom_scm_pas_auth_and_reset(dev, ctx->pas_id); + return qcom_scm_pas_auth_and_reset(dev, ctx->pas_id); =20 /* * When Linux runs @ EL2 Linux must create the shmbridge itself and then @@ -933,21 +873,14 @@ static int __qcom_scm_pas_prepare_and_auth_reset(stru= ct device *dev, if (ret) return ret; =20 - ret =3D __qcom_scm_pas_auth_and_reset(dev, ctx->pas_id); + ret =3D qcom_scm_pas_auth_and_reset(dev, ctx->pas_id); qcom_tzmem_shm_bridge_delete(handle); =20 return ret; } =20 -int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx) -{ - return __qcom_scm_pas_prepare_and_auth_reset(__scm->dev, - (struct qcom_pas_context *)ctx); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_prepare_and_auth_reset); - -static int __qcom_scm_pas_set_remote_state(struct device *dev, u32 state, - u32 pas_id) +static int qcom_scm_pas_set_remote_state(struct device *dev, u32 state, + u32 pas_id) { struct qcom_scm_desc desc =3D { .svc =3D QCOM_SCM_SVC_BOOT, @@ -965,13 +898,7 @@ static int __qcom_scm_pas_set_remote_state(struct devi= ce *dev, u32 state, return ret ? : res.result[0]; } =20 -int qcom_scm_set_remote_state(u32 state, u32 id) -{ - return __qcom_scm_pas_set_remote_state(__scm->dev, state, id); -} -EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state); - -static int __qcom_scm_pas_shutdown(struct device *dev, u32 pas_id) +static int qcom_scm_pas_shutdown(struct device *dev, u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { @@ -1000,13 +927,7 @@ static int __qcom_scm_pas_shutdown(struct device *dev= , u32 pas_id) return ret ? : res.result[0]; } =20 -int qcom_scm_pas_shutdown(u32 pas_id) -{ - return __qcom_scm_pas_shutdown(__scm->dev, pas_id); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_shutdown); - -static bool __qcom_scm_pas_supported(struct device *dev, u32 pas_id) +static bool qcom_scm_pas_supported(struct device *dev, u32 pas_id) { int ret; struct qcom_scm_desc desc =3D { @@ -1027,23 +948,17 @@ static bool __qcom_scm_pas_supported(struct device *= dev, u32 pas_id) return ret ? false : !!res.result[0]; } =20 -bool qcom_scm_pas_supported(u32 pas_id) -{ - return __qcom_scm_pas_supported(__scm->dev, pas_id); -} -EXPORT_SYMBOL_GPL(qcom_scm_pas_supported); - static struct qcom_pas_ops qcom_pas_ops_scm =3D { .drv_name =3D "qcom_scm", - .supported =3D __qcom_scm_pas_supported, - .init_image =3D __qcom_scm_pas_init_image2, - .mem_setup =3D __qcom_scm_pas_mem_setup, - .get_rsc_table =3D __qcom_scm_pas_get_rsc_table2, - .auth_and_reset =3D __qcom_scm_pas_auth_and_reset, - .prepare_and_auth_reset =3D __qcom_scm_pas_prepare_and_auth_reset, - .set_remote_state =3D __qcom_scm_pas_set_remote_state, - .shutdown =3D __qcom_scm_pas_shutdown, - .metadata_release =3D __qcom_scm_pas_metadata_release, + .supported =3D qcom_scm_pas_supported, + .init_image =3D qcom_scm_pas_init_image, + .mem_setup =3D qcom_scm_pas_mem_setup, + .get_rsc_table =3D qcom_scm_pas_get_rsc_table, + .auth_and_reset =3D qcom_scm_pas_auth_and_reset, + .prepare_and_auth_reset =3D qcom_scm_pas_prepare_and_auth_reset, + .set_remote_state =3D qcom_scm_pas_set_remote_state, + .shutdown =3D qcom_scm_pas_shutdown, + .metadata_release =3D qcom_scm_pas_metadata_release, }; =20 /** diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmwar= e/qcom/qcom_scm.h index 5747bd191bf1..a0a6bc0229c4 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -64,35 +64,6 @@ bool qcom_scm_is_available(void); int qcom_scm_set_cold_boot_addr(void *entry); int qcom_scm_set_warm_boot_addr(void *entry); void qcom_scm_cpu_power_down(u32 flags); -int qcom_scm_set_remote_state(u32 state, u32 id); - -struct qcom_scm_pas_context { - struct device *dev; - u32 pas_id; - phys_addr_t mem_phys; - size_t mem_size; - void *ptr; - dma_addr_t phys; - ssize_t size; - bool use_tzmem; -}; - -struct qcom_scm_pas_context *devm_qcom_scm_pas_context_alloc(struct device= *dev, - u32 pas_id, - phys_addr_t mem_phys, - size_t mem_size); -int qcom_scm_pas_init_image(u32 pas_id, const void *metadata, size_t size, - struct qcom_scm_pas_context *ctx); -void qcom_scm_pas_metadata_release(struct qcom_scm_pas_context *ctx); -int qcom_scm_pas_mem_setup(u32 pas_id, phys_addr_t addr, phys_addr_t size); -int qcom_scm_pas_auth_and_reset(u32 pas_id); -int qcom_scm_pas_shutdown(u32 pas_id); -bool qcom_scm_pas_supported(u32 pas_id); -struct resource_table *qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_cont= ext *ctx, - void *input_rt, size_t input_rt_size, - size_t *output_rt_size); - -int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_context *ctx); =20 int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val); int qcom_scm_io_writel(phys_addr_t addr, unsigned int val); --=20 2.51.0 From nobody Wed Jun 17 07:20:57 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 709263B4E84; Mon, 27 Apr 2026 10:00:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777284001; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1777284001; bh=yEIG92a1FH3cEp3tne1pDeDmYK3WLKv3UmItU7XJzvM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=qalb8byeKCMMPPdR3bDLqXrUNZ+T4+X41ohfZotvM9auPRR7bOGHhVHCLkIyfKCl8 pnLK46wiHan9Xfxjjz36dxDwTNFxa5f9q4LKwuawCeJaN1aC4iu8LonbB4lhg3hzBi cQxKOxHaO3lDsjmAB2YLNEX1HNKTZWvz5RIPGamsOtkK1INwJuOQSjoVOKfHENFxUb jxEiO3i1TaeqM8gMtKbZAI+juIF4MJLlyBLRB626lxjmsdGrKo2PxNQMBYbRm4IQKV zoB8Xr2Lgq66lOSvjvahrZWUGtvZAIe8zo+PyiYBOO/4DBu2VMxc/6uw34FALVJp4R 2+P8PGOw11Khg== From: Sumit Garg To: andersson@kernel.org, konradybcio@kernel.org Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-media@vger.kernel.org, netdev@vger.kernel.org, linux-wireless@vger.kernel.org, ath12k@lists.infradead.org, linux-remoteproc@vger.kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.clark@oss.qualcomm.com, sean@poorly.run, akhilpo@oss.qualcomm.com, lumag@kernel.org, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, marijn.suijten@somainline.org, airlied@gmail.com, simona@ffwll.ch, vikash.garodia@oss.qualcomm.com, dikshita.agarwal@oss.qualcomm.com, bod@kernel.org, mchehab@kernel.org, elder@kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, jjohnson@kernel.org, mathieu.poirier@linaro.org, trilokkumar.soni@oss.qualcomm.com, mukesh.ojha@oss.qualcomm.com, pavan.kondeti@oss.qualcomm.com, jorge.ramirez@oss.qualcomm.com, tonyh@qti.qualcomm.com, vignesh.viswanathan@oss.qualcomm.com, srinivas.kandagatla@oss.qualcomm.com, amirreza.zarrabi@oss.qualcomm.com, jens.wiklander@linaro.org, op-tee@lists.trustedfirmware.org, apurupa@qti.qualcomm.com, skare@qti.qualcomm.com, linux-kernel@vger.kernel.org, Sumit Garg Subject: [PATCH v4 15/15] MAINTAINERS: Add maintainer entry for Qualcomm PAS TZ service Date: Mon, 27 Apr 2026 15:26:03 +0530 Message-ID: <20260427095603.1157963-16-sumit.garg@kernel.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260427095603.1157963-1-sumit.garg@kernel.org> References: <20260427095603.1157963-1-sumit.garg@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Sumit Garg Add Sumit Garg as the maintainer for the Qualcomm generic Peripheral Authentication Service (PAS) as well as the PAS TEE backend driver. Signed-off-by: Sumit Garg Tested-by: Mukesh Ojha # Lemans --- MAINTAINERS | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2fb1c75afd16..6d3fc5145f0a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22007,6 +22007,15 @@ F: Documentation/devicetree/bindings/media/*qcom* F: drivers/media/platform/qcom F: include/dt-bindings/media/*qcom* =20 +QUALCOMM PAS TZ SERVICE +M: Sumit Garg +L: linux-arm-msm@vger.kernel.org +S: Maintained +F: drivers/firmware/qcom/qcom_pas.c +F: drivers/firmware/qcom/qcom_pas.h +F: drivers/firmware/qcom/qcom_pas_tee.c +F: include/linux/firmware/qcom/qcom_pas.h + QUALCOMM SMB CHARGER DRIVER M: Casey Connolly L: linux-arm-msm@vger.kernel.org --=20 2.51.0