From nobody Wed Jun 17 07:20:57 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85359370D4F; Mon, 27 Apr 2026 09:00:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777280418; cv=none; b=Z/iwIho2ayUAm6ETJ4yLoHHWuC8Vn7LGPVAfLYgR85Tt1HaQIOD/Lww00nKbS6FXfqUMQOkgME/MIrFhgtjAHQrxTTxRfTvkGEEjeomyT/7DBthE7iCAkiCJDLNlx2lakTJPSXjUq/KBWsCKKIMNe/UgQiya0qFMPok0y4nr4VY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777280418; c=relaxed/simple; bh=nK1rDZVAfufYW3vFHcgbHqcBeP8uEYPME2B5Cm9dQss=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Cxv/vhPg6rOpfMzxW/ckBUhERAIFeC67TxmCDzZMLBMl6CwWwrjGvRkoosHCE6TdtBffVF5Z2uidTo40rm2FtMu/Nb/ie5RcVI6yLbdrsTrrqa5nd5VV8GgRZyxUqD1c6kmcO22hYgxU1qOW8nbdaXx7dauTFuej0vavZ4aAS1s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=TEb7rmvO; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="TEb7rmvO" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777280417; x=1808816417; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nK1rDZVAfufYW3vFHcgbHqcBeP8uEYPME2B5Cm9dQss=; b=TEb7rmvO1a4MlyoIh6HH9W7nMSLCqDHchfs7YhRddQ5IyBQKS/Ya4llj MuH7erlnoDwM4oO5jU1M/iCfD6KJdBISBWoNFVpQBvw30B/i5oOuUc1G9 otUBnnXdeDUpmWKccZu9zQXWDi7vMeyqauesrdZn9mMDEN/ER3XIN/+Wv X0CYC68B62IMoLqw/DiiO4OAB3Phe5pV51ISviFlqw0KGYCL6CsI2YjAU kOWep7NM0db0geUZR+K3BeqeTKVR3WU+ZZBnEX0ITTBjFDwwXsQLvxY67 9ioZW6auwXZASzeOnxLpPHE7oytbLWiPW1K9MxfdNdX9K7attA5HkR2zi g==; X-CSE-ConnectionGUID: V1sx/m5xSGen1JuKHHgbOw== X-CSE-MsgGUID: qNP1ZngNR4iRu4iSqZ8LCg== X-IronPort-AV: E=McAfee;i="6800,10657,11768"; a="88476330" X-IronPort-AV: E=Sophos;i="6.23,201,1770624000"; d="scan'208";a="88476330" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 02:00:17 -0700 X-CSE-ConnectionGUID: 4lKUi6WyT4qjSv7btlrTZg== X-CSE-MsgGUID: /LP5uMb3S+qTzyzU+eJTDQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,201,1770624000"; d="scan'208";a="233850599" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa007.jf.intel.com with ESMTP; 27 Apr 2026 02:00:13 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi , stable@vger.kernel.org Subject: [Patch v3 1/4] perf/x86/intel: Improve validation and configuration of ACR masks Date: Mon, 27 Apr 2026 16:55:10 +0800 Message-Id: <20260427085513.3728672-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260427085513.3728672-1-dapeng1.mi@linux.intel.com> References: <20260427085513.3728672-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently there are several issues on the user space ACR mask validation and configuration. - The validation for user space ACR mask (attr.config2) is incomplete, e.g., the ACR mask could include the index which belongs to another ACR events group, but it's not validated. - An early return on an invalid ACR mask caused all subsequent ACR groups to be skipped. - The stale hardware ACR mask (hw.config1) is not cleared before setting new hardware ACR mask. The following changes address all of the above issues. - Calculate the indices bitmap for each ACR events group. Any bits in the user-space mask not present in the group's bitmap are now dropped. - Instead of an early return on invalid bits, drop only the invalid portions and continue iterating through all ACR events to ensure full configuration. - Explicitly clear the stale hardware ACR mask for each event prior to writing the new configuration. Cc: stable@vger.kernel.org Fixes: ec980e4facef ("perf/x86/intel: Support auto counter reload") Signed-off-by: Dapeng Mi --- v3: new patch. arch/x86/events/intel/core.c | 32 +++++++++++++++++++++++++------- 1 file changed, 25 insertions(+), 7 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 4768236c054b..1a2c268018a2 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3332,23 +3332,41 @@ static void intel_pmu_enable_event(struct perf_even= t *event) static void intel_pmu_acr_late_setup(struct cpu_hw_events *cpuc) { struct perf_event *event, *leader; - int i, j, idx; + int i, j, k, bit, idx; + u64 group_mask; =20 for (i =3D 0; i < cpuc->n_events; i++) { leader =3D cpuc->event_list[i]; if (!is_acr_event_group(leader)) continue; =20 - /* The ACR events must be contiguous. */ + /* Find the last event of the ACR group. */ for (j =3D i; j < cpuc->n_events; j++) { event =3D cpuc->event_list[j]; if (event->group_leader !=3D leader->group_leader) break; - for_each_set_bit(idx, (unsigned long *)&event->attr.config2, X86_PMC_ID= X_MAX) { - if (i + idx >=3D cpuc->n_events || - !is_acr_event_group(cpuc->event_list[i + idx])) - return; - __set_bit(cpuc->assign[i + idx], (unsigned long *)&event->hw.config1); + } + + /* Figure out the group indices bitmap. */ + group_mask =3D 0; + for (k =3D i; k < j; k++) + group_mask |=3D BIT_ULL(cpuc->assign[k]); + + /* + * Translate the user-space ACR mask (attr.config2) into the physical + * counter bitmask (hw.config1) for each ACR event in the group. + * NOTE: ACR event contiguity is guaranteed by intel_pmu_hw_config(). + */ + for (k =3D i; k < j; k++) { + event =3D cpuc->event_list[k]; + event->hw.config1 =3D 0; + for_each_set_bit(bit, (unsigned long *)&event->attr.config2, X86_PMC_ID= X_MAX) { + idx =3D i + bit; + if (idx >=3D cpuc->n_events || + !(BIT_ULL(cpuc->assign[idx]) & group_mask) || + !is_acr_event_group(cpuc->event_list[idx])) + continue; + __set_bit(cpuc->assign[idx], (unsigned long *)&event->hw.config1); } } i =3D j - 1; --=20 2.34.1 From nobody Wed Jun 17 07:20:57 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B3FF3A0E99; Mon, 27 Apr 2026 09:00:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777280421; cv=none; b=iM6f3Nr0WFhVNGfEYi4MJm19JnkJo/nvRcP9SA81skkaxrh+M4XRmx+Z/8gBGI1+80nQ4DQRO9VDyjXvsYp5fFPvqdm7XOuTL2NUoE3UAVnyLMllg6zkDsmSa9QG/AKiA2Kjdc0AoaRrEpUFRwxo4PKrlWzpl9YL2RTlhAHPoxY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777280421; c=relaxed/simple; bh=1Y5MnRG/1o8wFsR2/x7ymmXvutjdTzy2CcOaCVPodt4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Aspi8b7X2A/2DSaJDj/yesPKhs7GlsrhTRcF10slGilg1kVP3u9g1K/wB1RyoyrnAXRWPXjSh6mwKi/3K/YTioVzjq9AWmtfoCJnNZTEq4AedU+RkZZUTaMJyR/wePmuXu4MF7uKzTOQw1yPyfsXwGIb1LMzz6E7/vABtgUPHzo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CNhFpwXA; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CNhFpwXA" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777280421; x=1808816421; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=1Y5MnRG/1o8wFsR2/x7ymmXvutjdTzy2CcOaCVPodt4=; b=CNhFpwXAjh/EtVUUjy+U6zI0sQKFLqdx4u8CiogvKdtXNoMeGXeZwjie mvmgJ4fQurqSq1/dQk0anDg2HzAUFpfvioPwv1iN8j9gd5CncuLbaIfrc h7Q3BaDzWrpzTkerQ/he0yB+f1MNEEmvxqNIB5TTJ7yMEj70gwQxSgPr/ 65uoFjmWeiz8oLXUzs5BQfFDaRuWLnb+51HrbTVoNKSw9OcSxvjvk21vx d/u1YYkcT3DZIabObpEggZEiwncH7SzvFvMbPmX8iFOijLnojAt/YyJTd Qqc8BNy70vWECAbhOf25tjQigEihHsP4W2OxQbVztB5isqxT2bJPYIfJY Q==; X-CSE-ConnectionGUID: SpFaqobxSkq2g6zCsRR9jg== X-CSE-MsgGUID: urwG5uudRIetY+5L4dwmvQ== X-IronPort-AV: E=McAfee;i="6800,10657,11768"; a="88476340" X-IronPort-AV: E=Sophos;i="6.23,201,1770624000"; d="scan'208";a="88476340" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 02:00:21 -0700 X-CSE-ConnectionGUID: NVAG3SZ8QfWiSZesu8wTKg== X-CSE-MsgGUID: F0L2+HZQR5+P/CccpFKD6A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,201,1770624000"; d="scan'208";a="233850615" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa007.jf.intel.com with ESMTP; 27 Apr 2026 02:00:17 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi , stable@vger.kernel.org Subject: [Patch v3 2/4] perf/x86/intel: Disable PMI for self-reloaded ACR events Date: Mon, 27 Apr 2026 16:55:11 +0800 Message-Id: <20260427085513.3728672-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260427085513.3728672-1-dapeng1.mi@linux.intel.com> References: <20260427085513.3728672-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On platforms with Auto Counter Reload (ACR) support, such as NVL, a "NMI received for unknown reason 30" warning is observed when running multiple events in a group with ACR enabled: $ perf record -e '{instructions/period=3D20000,acr_mask=3D0x2/u,\ cycles/period=3D40000,acr_mask=3D0x3/u}' ./test The warning occurs because the Performance Monitoring Interrupt (PMI) is enabled for the self-reloaded event (the cycles event in this case). According to the Intel SDM, the overflow bit (IA32_PERF_GLOBAL_STATUS.PMCn_OVF) is never set for self-reloaded events. Since the bit is not set, the perf NMI handler cannot identify the source of the interrupt, leading to the "unknown reason" message. Furthermore, enabling PMI for self-reloaded events is unnecessary and can lead to extraneous records that pollute the user's requested data. Disable the interrupt bit for all events configured with ACR self-reload. Reported-by: Andi Kleen Cc: stable@vger.kernel.org Fixes: ec980e4facef ("perf/x86/intel: Support auto counter reload") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/core.c | 17 +++++++++++++---- arch/x86/events/perf_event.h | 10 ++++++++++ 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 1a2c268018a2..c1841fa89908 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3118,11 +3118,11 @@ static void intel_pmu_enable_fixed(struct perf_even= t *event) intel_set_masks(event, idx); =20 /* - * Enable IRQ generation (0x8), if not PEBS, - * and enable ring-3 counting (0x2) and ring-0 counting (0x1) - * if requested: + * Enable IRQ generation (0x8), if not PEBS and self-reloaded + * ACR event, and enable ring-3 counting (0x2) and ring-0 + * counting (0x1) if requested: */ - if (!event->attr.precise_ip) + if (!event->attr.precise_ip && !is_acr_self_reload_event(event)) bits |=3D INTEL_FIXED_0_ENABLE_PMI; if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) bits |=3D INTEL_FIXED_0_USER; @@ -3306,6 +3306,15 @@ static void intel_pmu_enable_event(struct perf_event= *event) intel_set_masks(event, idx); static_call_cond(intel_pmu_enable_acr_event)(event); static_call_cond(intel_pmu_enable_event_ext)(event); + /* + * For self-reloaded ACR event, don't enable PMI since + * HW won't set overflow bit in GLOBAL_STATUS. Otherwise, + * the PMI would be recognized as a suspicious NMI. + */ + if (is_acr_self_reload_event(event)) + hwc->config &=3D ~ARCH_PERFMON_EVENTSEL_INT; + else if (!event->attr.precise_ip) + hwc->config |=3D ARCH_PERFMON_EVENTSEL_INT; __x86_pmu_enable_event(hwc, enable_mask); break; case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index fad87d3c8b2c..524668dcf4cc 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -137,6 +137,16 @@ static inline bool is_acr_event_group(struct perf_even= t *event) return check_leader_group(event->group_leader, PERF_X86_EVENT_ACR); } =20 +static inline bool is_acr_self_reload_event(struct perf_event *event) +{ + struct hw_perf_event *hwc =3D &event->hw; + + if (hwc->idx < 0) + return false; + + return test_bit(hwc->idx, (unsigned long *)&hwc->config1); +} + struct amd_nb { int nb_id; /* NorthBridge id */ int refcnt; /* reference count */ --=20 2.34.1 From nobody Wed Jun 17 07:20:57 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 686893ACA6A; Mon, 27 Apr 2026 09:00:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777280425; cv=none; b=E1SJyHo9fgENJc2M3V8k+ZKz1jQFq/4G5bPvkZNZktt1IdZ5Wo9Bz1o6k+Uhsd0ZqMasESZjyfM8eFZoZxPjJBH+M/vFtNjn+t/WOfnq1lNGNTCTxnUcdoEwcgGNasdtoiwnWCBy4demFdfUsI5zwi2oxtaIUGtV99siMW/0SS0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777280425; c=relaxed/simple; bh=p11m1qkgDiZhbp7WCgA/lTdQ6yP2okCMD8NKm+Lhho8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=Y2ZCXhdnVwRCYXg+xCLEc5wSiOkSiqJuw7xGL4lyHhvv4oa8MedrItVCac1HdIyg4tu795ZPqNm7SeZlDaPCPxqxFGtYSQiN9TedF2Mt1Ha12BxiStNVNDG+qnNJB7nrSPhsaeVgFO+Nw0R1AYLXI746DWmiljvpT6qO+dySJG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mOnddLmi; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mOnddLmi" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777280425; x=1808816425; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=p11m1qkgDiZhbp7WCgA/lTdQ6yP2okCMD8NKm+Lhho8=; b=mOnddLmi/8Ieqzo4IvhW320ZkCUEy1qg1e81FeIp3jQtOJTYCs5oD7Xi 9tTZgrOu/ZcFMcBOCaThCrnIFqZ5niVhGhz7zkJdkgpHDI6kop4b4g8nl /Jge72mFyHtcOXTr4mA+XmeT2YjiKT/w8MnIIMDKjgve8q2cRh6ZXN5gP sLi2mIt+jTfvM4NlLAC37CCa8mO2xxbNyfMaSYz+6zE4KOBV+kwMn1cPH 8wT9R7Lob2o1Ba/9NvS4g3FxitAVIJ/avCR1z6kg2LYaMn8DXXeULVg6a Ldo2ZAnp4obj9e9iIbmEyTzwy6+2jQnPg/7lU+cY5DDYxWzc3+YGMluZy Q==; X-CSE-ConnectionGUID: 9IXb9OfWRdiDfhLhol+3Sw== X-CSE-MsgGUID: ZWPYmgu3SrG4s6phSSskOQ== X-IronPort-AV: E=McAfee;i="6800,10657,11768"; a="88476349" X-IronPort-AV: E=Sophos;i="6.23,201,1770624000"; d="scan'208";a="88476349" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 02:00:25 -0700 X-CSE-ConnectionGUID: iPoYK+znQwKbu543zfQM7A== X-CSE-MsgGUID: G34I9i8PQVSpwCxE9kEhLw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,201,1770624000"; d="scan'208";a="233850645" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa007.jf.intel.com with ESMTP; 27 Apr 2026 02:00:21 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi , stable@vger.kernel.org Subject: [Patch v3 3/4] perf/x86/intel: Enable auto counter reload for DMR Date: Mon, 27 Apr 2026 16:55:12 +0800 Message-Id: <20260427085513.3728672-4-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260427085513.3728672-1-dapeng1.mi@linux.intel.com> References: <20260427085513.3728672-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Panther cove =C2=B5arch starts to support auto counter reload (ACR), but the static_call intel_pmu_enable_acr_event() is not updated for the Panther Cove =C2=B5arch used by DMR. It leads to the auto counter reload is not really enabled on DMR. Update static_call intel_pmu_enable_acr_event() in intel_pmu_init_pnc(). Cc: stable@vger.kernel.org Fixes: d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index c1841fa89908..60568a9ce06b 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -7518,6 +7518,7 @@ static __always_inline void intel_pmu_init_pnc(struct= pmu *pmu) hybrid(pmu, event_constraints) =3D intel_pnc_event_constraints; hybrid(pmu, pebs_constraints) =3D intel_pnc_pebs_event_constraints; hybrid(pmu, extra_regs) =3D intel_pnc_extra_regs; + static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); } =20 static __always_inline void intel_pmu_init_skt(struct pmu *pmu) --=20 2.34.1 From nobody Wed Jun 17 07:20:57 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29C753AD50D; Mon, 27 Apr 2026 09:00:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.11 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777280429; cv=none; b=nJ0vknfpCTGfNhiCb7B7W53IBA/8++Q4vFkYKVlimVjbBsBDykseD9eqiZOdwsljQK9DgFVnBDtrW86Tv2x//IniYLV1QDqlWmcZ8U/EVYpsOc7bs7SmvClE26HGqhw3fIO73lMCcHV2UtGjrFsTxKqbZuEgmL4Al8KTREWQPAY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777280429; c=relaxed/simple; bh=BSiRhiJaK8vaseOEYBdc8h6BfjVONGImkHO7urgWINQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=k2U3OJnnl+cS1no4YybshiX+NHewUY1VPEOjs45n/GGT7msR0eZH8swI4tW4G3MyziBxyu4ExARtGU51YNgpcERiVrMpqZ9sV7UEUsQqyHykINjXhgXou6y+3Y4LSAhaQrOPGtdR7r5HRNninfOmeQBXbNXL4kYALii/F/5puiY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FUNDCFCr; arc=none smtp.client-ip=198.175.65.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FUNDCFCr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1777280429; x=1808816429; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BSiRhiJaK8vaseOEYBdc8h6BfjVONGImkHO7urgWINQ=; b=FUNDCFCrcsxegzXVo7OfCAGVE1GppxgpopeMWkrtc4dT2LTXmJ24Eoyf 5B61F1qCJ1xp7xH5RwK/KshPVDdMKGCmb056tnwd+u9iq7ENSy0Jbd40s iK8NhAZgikPd5Zz6spptHVbGGAdpEF7MVuSYnAM77s1z5is2WKFf9Zekc 7bjZfSa/Hvne6/uue/dSDrqcHPeGQcL8uMbP1KvPtmBnGbaYufatpDezy O/Lt7sp7083k7KXuz7SZv3Vc7A2bDoLVI7QUgvTBtOOaEb3G72S62YmID KAt8u3GrSK7XeyMzEEuaC8vQc8Re4Dcu+wWbrqypsPe7p6HOy5v7pHaM5 Q==; X-CSE-ConnectionGUID: d6eVUaqiQ1i+TdFNzB5hkg== X-CSE-MsgGUID: IjmhjGgKS6qimaVUMEu83Q== X-IronPort-AV: E=McAfee;i="6800,10657,11768"; a="88476356" X-IronPort-AV: E=Sophos;i="6.23,201,1770624000"; d="scan'208";a="88476356" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by orvoesa103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Apr 2026 02:00:29 -0700 X-CSE-ConnectionGUID: pUGuhvURSneTkupXfqhhPQ== X-CSE-MsgGUID: fWs4P+NYR6+cuFq4Z0Oopw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,201,1770624000"; d="scan'208";a="233850655" Received: from spr.sh.intel.com ([10.112.229.196]) by orviesa007.jf.intel.com with ESMTP; 27 Apr 2026 02:00:25 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [Patch v3 4/4] perf/x86/intel: Consolidate MSR_IA32_PERF_CFG_C tracking Date: Mon, 27 Apr 2026 16:55:13 +0800 Message-Id: <20260427085513.3728672-5-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260427085513.3728672-1-dapeng1.mi@linux.intel.com> References: <20260427085513.3728672-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Both Auto Counter Reload (ACR) and Architectural PEBS use the PERF_CFG_C MSRs to configure event behavior. Currently, the driver maintains two independent variables acr_cfg_c and cfg_c_val to cache the values intended for these MSRs. Using separate variables to track a single hardware register state is error-prone and can lead to configuration conflicts. Consolidate the tracking into a single cfg_c_val variable to ensure a unified and consistent view of the PERF_CFG_C MSR state. Signed-off-by: Dapeng Mi --- arch/x86/events/intel/core.c | 13 +++++++------ arch/x86/events/perf_event.h | 4 +--- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 60568a9ce06b..013e6e02706d 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3169,10 +3169,10 @@ static void intel_pmu_config_acr(int idx, u64 mask,= u32 reload) wrmsrl(msr_b + msr_offset, mask); cpuc->acr_cfg_b[idx] =3D mask; } - /* Only need to update the reload value when there is a valid config valu= e. */ - if (mask && cpuc->acr_cfg_c[idx] !=3D reload) { + /* Only update CFG_C reload when ACR is actively enabled (mask !=3D 0) */ + if (mask && ((cpuc->cfg_c_val[idx] & ARCH_PEBS_RELOAD) !=3D reload)) { wrmsrl(msr_c + msr_offset, reload); - cpuc->acr_cfg_c[idx] =3D reload; + cpuc->cfg_c_val[idx] =3D reload; } } =20 @@ -3198,14 +3198,15 @@ static void intel_pmu_enable_event_ext(struct perf_= event *event) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); struct hw_perf_event *hwc =3D &event->hw; - union arch_pebs_index old, new; - struct arch_pebs_cap cap; u64 ext =3D 0; =20 - cap =3D hybrid(cpuc->pmu, arch_pebs_cap); + if (is_acr_event_group(event)) + ext |=3D (-hwc->sample_period) & ARCH_PEBS_RELOAD; =20 if (event->attr.precise_ip) { u64 pebs_data_cfg =3D intel_get_arch_pebs_data_config(event); + struct arch_pebs_cap cap =3D hybrid(cpuc->pmu, arch_pebs_cap); + union arch_pebs_index old, new; =20 ext |=3D ARCH_PEBS_EN; if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 524668dcf4cc..40d6fe0afc4a 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -322,10 +322,8 @@ struct cpu_hw_events { u64 fixed_ctrl_val; u64 active_fixed_ctrl_val; =20 - /* Intel ACR configuration */ + /* Intel ACR/arch-PEBS configuration */ u64 acr_cfg_b[X86_PMC_IDX_MAX]; - u64 acr_cfg_c[X86_PMC_IDX_MAX]; - /* Cached CFG_C values */ u64 cfg_c_val[X86_PMC_IDX_MAX]; =20 /* --=20 2.34.1