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charset="utf-8" Document the device tree binding for the Tegra238 memory controller. Tegra238 has 8 memory controller channels plus broadcast and stream-id registers. Add the stream ID header (nvidia,tegra238-mc.h) defining ISO and NISO stream IDs for SMMU configuration. Signed-off-by: Ashish Mhetre Reviewed-by: Jon Hunter --- .../nvidia,tegra186-mc.yaml | 31 ++++++++ .../dt-bindings/memory/nvidia,tegra238-mc.h | 74 +++++++++++++++++++ 2 files changed, 105 insertions(+) create mode 100644 include/dt-bindings/memory/nvidia,tegra238-mc.h diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,te= gra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidi= a,tegra186-mc.yaml index 7b03b589168b..6c374e2b1543 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-= mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-= mc.yaml @@ -32,6 +32,7 @@ properties: - nvidia,tegra186-mc - nvidia,tegra194-mc - nvidia,tegra234-mc + - nvidia,tegra238-mc - nvidia,tegra264-mc =20 reg: @@ -266,6 +267,36 @@ allOf: =20 interrupt-names: false =20 + - if: + properties: + compatible: + const: nvidia,tegra238-mc + then: + properties: + reg: + minItems: 10 + maxItems: 10 + description: 9 memory controller channels and 1 for stream-id re= gisters + + reg-names: + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + + interrupts: + items: + - description: MC general interrupt + + interrupt-names: false + - if: properties: compatible: diff --git a/include/dt-bindings/memory/nvidia,tegra238-mc.h b/include/dt-b= indings/memory/nvidia,tegra238-mc.h new file mode 100644 index 000000000000..be24c0eb3f15 --- /dev/null +++ b/include/dt-bindings/memory/nvidia,tegra238-mc.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */ + +#ifndef DT_BINDINGS_MEMORY_TEGRA238_MC_H +#define DT_BINDINGS_MEMORY_TEGRA238_MC_H + +/* special clients */ +#define TEGRA238_SID_INVALID 0x0 +#define TEGRA238_SID_PASSTHROUGH 0x7f + +/* ISO stream IDs */ +#define TEGRA238_SID_ISO_NVDISPLAY 0x1 +#define TEGRA238_SID_ISO_APE0 0x2 +#define TEGRA238_SID_ISO_APE1 0x3 + +/* NISO stream IDs */ +#define TEGRA238_SID_AON 0x1 +#define TEGRA238_SID_BPMP 0x2 +#define TEGRA238_SID_ETR 0x3 +#define TEGRA238_SID_FDE 0x4 +#define TEGRA238_SID_HC 0x5 +#define TEGRA238_SID_HDA 0x6 +#define TEGRA238_SID_NVDEC 0x7 +#define TEGRA238_SID_NVDISPLAY 0x8 +#define TEGRA238_SID_NVENC 0x9 +#define TEGRA238_SID_OFA 0xa +#define TEGRA238_SID_PCIE0 0xb +#define TEGRA238_SID_PCIE1 0xc +#define TEGRA238_SID_PCIE2 0xd +#define TEGRA238_SID_PCIE3 0xe +#define TEGRA238_SID_HWMP_PMA 0xf +#define TEGRA238_SID_PSC 0x10 +#define TEGRA238_SID_SDMMC1A 0x11 +#define TEGRA238_SID_SDMMC4A 0x12 +#define TEGRA238_SID_SES_SE0 0x13 +#define TEGRA238_SID_SES_SE1 0x14 +#define TEGRA238_SID_SES_SE2 0x15 +#define TEGRA238_SID_SEU1_SE0 0x16 +#define TEGRA238_SID_SEU1_SE1 0x17 +#define TEGRA238_SID_SEU1_SE2 0x18 +#define TEGRA238_SID_TSEC 0x19 +#define TEGRA238_SID_UFSHC 0x1a +#define TEGRA238_SID_VIC 0x1b +#define TEGRA238_SID_XUSB_HOST 0x1c +#define TEGRA238_SID_XUSB_DEV 0x1d +#define TEGRA238_SID_GPCDMA_0 0x1e +#define TEGRA238_SID_SMMU_TEST 0x1f + +/* Host1x virtualization clients. */ +#define TEGRA238_SID_HOST1X_CTX0 0x20 +#define TEGRA238_SID_HOST1X_CTX1 0x21 +#define TEGRA238_SID_HOST1X_CTX2 0x22 +#define TEGRA238_SID_HOST1X_CTX3 0x23 +#define TEGRA238_SID_HOST1X_CTX4 0x24 +#define TEGRA238_SID_HOST1X_CTX5 0x25 +#define TEGRA238_SID_HOST1X_CTX6 0x26 +#define TEGRA238_SID_HOST1X_CTX7 0x27 + +#define TEGRA238_SID_XUSB_VF0 0x28 +#define TEGRA238_SID_XUSB_VF1 0x29 +#define TEGRA238_SID_XUSB_VF2 0x2a +#define TEGRA238_SID_XUSB_VF3 0x2b + +/* Host1x command buffers */ +#define TEGRA238_SID_HC_VM0 0x2c +#define TEGRA238_SID_HC_VM1 0x2d +#define TEGRA238_SID_HC_VM2 0x2e +#define TEGRA238_SID_HC_VM3 0x2f +#define TEGRA238_SID_HC_VM4 0x30 +#define TEGRA238_SID_HC_VM5 0x31 +#define TEGRA238_SID_HC_VM6 0x32 +#define TEGRA238_SID_HC_VM7 0x33 + +#endif --=20 2.50.1 From nobody Sun Jun 14 00:39:52 2026 Received: from CH5PR02CU005.outbound.protection.outlook.com (mail-northcentralusazon11012011.outbound.protection.outlook.com [40.107.200.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 128673803D8; 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charset="utf-8" Add Memory Controller driver support for Tegra238 SOC, including: - MC client definitions with Tegra238-specific stream IDs - Reuse of Tegra234 ICC operations for bandwidth management via BPMP-FW - Device tree compatible string "nvidia,tegra238-mc" Export tegra234_mc_icc_ops so it can be shared with the Tegra238 MC driver, as both SoCs use the same ICC aggregation and bandwidth management logic. Signed-off-by: Ashish Mhetre Reviewed-by: Jon Hunter --- drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/mc.c | 3 + drivers/memory/tegra/mc.h | 9 + drivers/memory/tegra/tegra234.c | 2 +- drivers/memory/tegra/tegra238.c | 391 ++++++++++++++++++++++++++++++++ 5 files changed, 405 insertions(+), 1 deletion(-) create mode 100644 drivers/memory/tegra/tegra238.c diff --git a/drivers/memory/tegra/Makefile b/drivers/memory/tegra/Makefile index 6334601e6120..7c2fca12076b 100644 --- a/drivers/memory/tegra/Makefile +++ b/drivers/memory/tegra/Makefile @@ -10,6 +10,7 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) +=3D tegra210.o tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) +=3D tegra186.o tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) +=3D tegra186.o tegra194.o tegra-mc-$(CONFIG_ARCH_TEGRA_234_SOC) +=3D tegra186.o tegra234.o +tegra-mc-$(CONFIG_ARCH_TEGRA_238_SOC) +=3D tegra186.o tegra234.o tegra238.o tegra-mc-$(CONFIG_ARCH_TEGRA_264_SOC) +=3D tegra186.o tegra264.o =20 obj-$(CONFIG_TEGRA_MC) +=3D tegra-mc.o diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index d620660da331..10ef3c323e22 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -49,6 +49,9 @@ static const struct of_device_id tegra_mc_of_match[] =3D { #ifdef CONFIG_ARCH_TEGRA_234_SOC { .compatible =3D "nvidia,tegra234-mc", .data =3D &tegra234_mc_soc }, #endif +#ifdef CONFIG_ARCH_TEGRA_238_SOC + { .compatible =3D "nvidia,tegra238-mc", .data =3D &tegra238_mc_soc }, +#endif #ifdef CONFIG_ARCH_TEGRA_264_SOC { .compatible =3D "nvidia,tegra264-mc", .data =3D &tegra264_mc_soc }, #endif diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h index 649b54369263..e94d265d7b67 100644 --- a/drivers/memory/tegra/mc.h +++ b/drivers/memory/tegra/mc.h @@ -240,6 +240,14 @@ extern const struct tegra_mc_soc tegra194_mc_soc; extern const struct tegra_mc_soc tegra234_mc_soc; #endif =20 +#if defined(CONFIG_ARCH_TEGRA_234_SOC) || defined(CONFIG_ARCH_TEGRA_238_SO= C) +extern const struct tegra_mc_icc_ops tegra234_mc_icc_ops; +#endif + +#ifdef CONFIG_ARCH_TEGRA_238_SOC +extern const struct tegra_mc_soc tegra238_mc_soc; +#endif + #ifdef CONFIG_ARCH_TEGRA_264_SOC extern const struct tegra_mc_soc tegra264_mc_soc; #endif @@ -256,6 +264,7 @@ extern const struct tegra_mc_ops tegra30_mc_ops; #if defined(CONFIG_ARCH_TEGRA_186_SOC) || \ defined(CONFIG_ARCH_TEGRA_194_SOC) || \ defined(CONFIG_ARCH_TEGRA_234_SOC) || \ + defined(CONFIG_ARCH_TEGRA_238_SOC) || \ defined(CONFIG_ARCH_TEGRA_264_SOC) extern const struct tegra_mc_ops tegra186_mc_ops; #endif diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra23= 4.c index 87b22038a5fb..9fbd34d4abe0 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -1125,7 +1125,7 @@ static int tegra234_mc_icc_get_init_bw(struct icc_nod= e *node, u32 *avg, u32 *pea return 0; } =20 -static const struct tegra_mc_icc_ops tegra234_mc_icc_ops =3D { +const struct tegra_mc_icc_ops tegra234_mc_icc_ops =3D { .xlate =3D tegra_mc_icc_xlate, .aggregate =3D tegra234_mc_icc_aggregate, .get_bw =3D tegra234_mc_icc_get_init_bw, diff --git a/drivers/memory/tegra/tegra238.c b/drivers/memory/tegra/tegra23= 8.c new file mode 100644 index 000000000000..938c8985600e --- /dev/null +++ b/drivers/memory/tegra/tegra238.c @@ -0,0 +1,391 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2026, NVIDIA CORPORATION. All rights reserved. + */ + +#include + +#include +#include +#include +#include + +#include +#include "mc.h" + +static const struct tegra_mc_client tegra238_mc_clients[] =3D { + { + .id =3D TEGRA234_MEMORY_CLIENT_HDAR, + .name =3D "hdar", + .bpmp_id =3D TEGRA_ICC_BPMP_HDA, + .type =3D TEGRA_ICC_ISO_AUDIO, + .sid =3D TEGRA238_SID_HDA, + .regs =3D { + .sid =3D { + .override =3D 0xa8, + .security =3D 0xac, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_HDAW, + .name =3D "hdaw", + .bpmp_id =3D TEGRA_ICC_BPMP_HDA, + .type =3D TEGRA_ICC_ISO_AUDIO, + .sid =3D TEGRA238_SID_HDA, + .regs =3D { + .sid =3D { + .override =3D 0x1a8, + .security =3D 0x1ac, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_SDMMCRAB, + .name =3D "sdmmcrab", + .bpmp_id =3D TEGRA_ICC_BPMP_SDMMC_4, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_SDMMC4A, + .regs =3D { + .sid =3D { + .override =3D 0x318, + .security =3D 0x31c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_SDMMCWAB, + .name =3D "sdmmcwab", + .bpmp_id =3D TEGRA_ICC_BPMP_SDMMC_4, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_SDMMC4A, + .regs =3D { + .sid =3D { + .override =3D 0x338, + .security =3D 0x33c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_APER, + .name =3D "aper", + .bpmp_id =3D TEGRA_ICC_BPMP_APE, + .type =3D TEGRA_ICC_ISO_AUDIO, + .sid =3D TEGRA238_SID_ISO_APE0, + .regs =3D { + .sid =3D { + .override =3D 0x3d0, + .security =3D 0x3d4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_APEW, + .name =3D "apew", + .bpmp_id =3D TEGRA_ICC_BPMP_APE, + .type =3D TEGRA_ICC_ISO_AUDIO, + .sid =3D TEGRA238_SID_ISO_APE0, + .regs =3D { + .sid =3D { + .override =3D 0x3d8, + .security =3D 0x3dc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVDISPLAYR, + .name =3D "nvdisplayr", + .bpmp_id =3D TEGRA_ICC_BPMP_DISPLAY, + .type =3D TEGRA_ICC_ISO_DISPLAY, + .sid =3D TEGRA238_SID_ISO_NVDISPLAY, + .regs =3D { + .sid =3D { + .override =3D 0x490, + .security =3D 0x494, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVDISPLAYR1, + .name =3D "nvdisplayr1", + .bpmp_id =3D TEGRA_ICC_BPMP_DISPLAY, + .type =3D TEGRA_ICC_ISO_DISPLAY, + .sid =3D TEGRA238_SID_ISO_NVDISPLAY, + .regs =3D { + .sid =3D { + .override =3D 0x508, + .security =3D 0x50c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_BPMPR, + .name =3D "bpmpr", + .sid =3D TEGRA238_SID_BPMP, + .regs =3D { + .sid =3D { + .override =3D 0x498, + .security =3D 0x49c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_BPMPW, + .name =3D "bpmpw", + .sid =3D TEGRA238_SID_BPMP, + .regs =3D { + .sid =3D { + .override =3D 0x4a0, + .security =3D 0x4a4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_BPMPDMAR, + .name =3D "bpmpdmar", + .sid =3D TEGRA238_SID_BPMP, + .regs =3D { + .sid =3D { + .override =3D 0x4a8, + .security =3D 0x4ac, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_BPMPDMAW, + .name =3D "bpmpdmaw", + .sid =3D TEGRA238_SID_BPMP, + .regs =3D { + .sid =3D { + .override =3D 0x4b0, + .security =3D 0x4b4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_APEDMAR, + .name =3D "apedmar", + .bpmp_id =3D TEGRA_ICC_BPMP_APEDMA, + .type =3D TEGRA_ICC_ISO_AUDIO, + .sid =3D TEGRA238_SID_ISO_APE1, + .regs =3D { + .sid =3D { + .override =3D 0x4f8, + .security =3D 0x4fc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_APEDMAW, + .name =3D "apedmaw", + .bpmp_id =3D TEGRA_ICC_BPMP_APEDMA, + .type =3D TEGRA_ICC_ISO_AUDIO, + .sid =3D TEGRA238_SID_ISO_APE1, + .regs =3D { + .sid =3D { + .override =3D 0x500, + .security =3D 0x504, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_VICSRD, + .name =3D "vicsrd", + .bpmp_id =3D TEGRA_ICC_BPMP_VIC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_VIC, + .regs =3D { + .sid =3D { + .override =3D 0x360, + .security =3D 0x364, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_VICSWR, + .name =3D "vicswr", + .bpmp_id =3D TEGRA_ICC_BPMP_VIC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_VIC, + .regs =3D { + .sid =3D { + .override =3D 0x368, + .security =3D 0x36c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVDECSRD, + .name =3D "nvdecsrd", + .bpmp_id =3D TEGRA_ICC_BPMP_NVDEC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_NVDEC, + .regs =3D { + .sid =3D { + .override =3D 0x3c0, + .security =3D 0x3c4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVDECSWR, + .name =3D "nvdecswr", + .bpmp_id =3D TEGRA_ICC_BPMP_NVDEC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_NVDEC, + .regs =3D { + .sid =3D { + .override =3D 0x3c8, + .security =3D 0x3cc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVENCSRD, + .name =3D "nvencsrd", + .bpmp_id =3D TEGRA_ICC_BPMP_NVENC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_NVENC, + .regs =3D { + .sid =3D { + .override =3D 0xe0, + .security =3D 0xe4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVENCSWR, + .name =3D "nvencswr", + .bpmp_id =3D TEGRA_ICC_BPMP_NVENC, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_NVENC, + .regs =3D { + .sid =3D { + .override =3D 0x158, + .security =3D 0x15c, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE0R, + .name =3D "pcie0r", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_0, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE0, + .regs =3D { + .sid =3D { + .override =3D 0x6c0, + .security =3D 0x6c4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE0W, + .name =3D "pcie0w", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_0, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE0, + .regs =3D { + .sid =3D { + .override =3D 0x6c8, + .security =3D 0x6cc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE1R, + .name =3D "pcie1r", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_1, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE1, + .regs =3D { + .sid =3D { + .override =3D 0x6d0, + .security =3D 0x6d4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE1W, + .name =3D "pcie1w", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_1, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE1, + .regs =3D { + .sid =3D { + .override =3D 0x6d8, + .security =3D 0x6dc, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE2AR, + .name =3D "pcie2ar", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_2, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE2, + .regs =3D { + .sid =3D { + .override =3D 0x6e0, + .security =3D 0x6e4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE2AW, + .name =3D "pcie2aw", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_2, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE2, + .regs =3D { + .sid =3D { + .override =3D 0x6e8, + .security =3D 0x6ec, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE3R, + .name =3D "pcie3r", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_3, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE3, + .regs =3D { + .sid =3D { + .override =3D 0x6f0, + .security =3D 0x6f4, + }, + }, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_PCIE3W, + .name =3D "pcie3w", + .bpmp_id =3D TEGRA_ICC_BPMP_PCIE_3, + .type =3D TEGRA_ICC_NISO, + .sid =3D TEGRA238_SID_PCIE3, + .regs =3D { + .sid =3D { + .override =3D 0x6f8, + .security =3D 0x6fc, + }, + }, + }, { + .id =3D TEGRA_ICC_MC_CPU_CLUSTER0, + .name =3D "sw_cluster0", + .bpmp_id =3D TEGRA_ICC_BPMP_CPU_CLUSTER0, + .type =3D TEGRA_ICC_NISO, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVL1R, + .name =3D "nvl1r", + .bpmp_id =3D TEGRA_ICC_BPMP_GPU, + .type =3D TEGRA_ICC_NISO, + }, { + .id =3D TEGRA234_MEMORY_CLIENT_NVL1W, + .name =3D "nvl1w", + .bpmp_id =3D TEGRA_ICC_BPMP_GPU, + .type =3D TEGRA_ICC_NISO, + } +}; + +static const struct tegra_mc_intmask tegra238_mc_intmasks[] =3D { + { + .reg =3D MC_INTMASK, + .mask =3D MC_INT_DECERR_ROUTE_SANITY | MC_INT_DECERR_GENERALIZED_CARVEOU= T | + MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR | + MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM, + }, +}; + +const struct tegra_mc_soc tegra238_mc_soc =3D { + .num_clients =3D ARRAY_SIZE(tegra238_mc_clients), + .clients =3D tegra238_mc_clients, + .num_address_bits =3D 40, + .num_channels =3D 8, + .client_id_mask =3D 0x1ff, + .intmasks =3D tegra238_mc_intmasks, + .num_intmasks =3D ARRAY_SIZE(tegra238_mc_intmasks), + .has_addr_hi_reg =3D true, + .ops =3D &tegra186_mc_ops, + .icc_ops =3D &tegra234_mc_icc_ops, + .ch_intmask =3D 0x0000ff00, + .global_intstatus_channel_shift =3D 8, + .num_carveouts =3D 32, + .regs =3D &tegra20_mc_regs, + .handle_irq =3D tegra30_mc_irq_handlers, + .num_interrupts =3D ARRAY_SIZE(tegra30_mc_irq_handlers), + .mc_addr_hi_mask =3D 0x3, + .mc_err_status_type_mask =3D (0x7 << 28), +}; --=20 2.50.1