From nobody Wed Jun 17 07:26:44 2026 Received: from mail-m19731117.qiye.163.com (mail-m19731117.qiye.163.com [220.197.31.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A22F248166; Mon, 27 Apr 2026 06:28:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.117 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777271340; cv=none; b=p5xhIIXZBreKZQACnG8daQsFqYwozvMzm5JdRUOX6H1dM+eSY2efdCZmKPoc9LSYJUHKDwGn9QgXdpt4KWs2K91xgbSvezu448pnHPgeKxYNoQ7+Fhvj9r/bugBoRzgt3719pAP6UCfPYQA+z51UKvG1WN4CB6odZ9VBHFySHBU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777271340; c=relaxed/simple; bh=hzIoHfnPdYQMF9GtwItmBDS7TD1MqyYSOUvBP3HWYXU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sCwDJR7MqbUknrRkcY2Ky5D0VAkM4uWQ+sY3oVExDMxzGP1w3UOkVx5cbWzN/ysxd7gZ9WpVGGTTq8XKsd3+nzLoJQSE2dw2djsPQB1w+y8sykkwyotBYkB4Ldm/58G1x0hiTyPl/sei0yU2x2wto1yrQW2zZ3pzI/0HgS9k7Bs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com; spf=pass smtp.mailfrom=thundersoft.com; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b=dUkLNg4b; arc=none smtp.client-ip=220.197.31.117 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b="dUkLNg4b" Received: from albert-OptiPlex-7080.. (unknown [112.65.126.162]) by smtp.qiye.163.com (Hmail) with ESMTP id 3c40fa9e6; Mon, 27 Apr 2026 14:23:27 +0800 (GMT+08:00) From: Albert Yang To: gordon.ge@bst.ai, krzk@kernel.org, krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org, arnd@arndb.de, catalin.marinas@arm.com, will@kernel.org Cc: bst-upstream@bstai.top, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 1/2] arm64: dts: bst: enable eMMC controller in C1200 CDCU1.0 board Date: Mon, 27 Apr 2026 14:23:24 +0800 Message-ID: <20260427062326.3715732-2-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427062326.3715732-1-yangzh0906@thundersoft.com> References: <20260427062326.3715732-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9dcd9b696e09cckunm8f7dadf41a30ac X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVlDT0pCVh5JSUxMTRhKTUtITlYVFA kWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlKSklVTU5VSklNVUpNSVlXWRYaDxIVHRRZQVlPS0hVSk tJT09PSFVKS0tVSkJLS1kG DKIM-Signature: a=rsa-sha256; b=dUkLNg4bBJdd4jvIx6m6lYRzxha71NN9rvvOO3g42oQs1IT+FXjxyAgjbh+AMo5PcVCmX0aQSwSlcxm5rEA1+RyRJVVQD9wI4ZSxAtK8rbYFM17Ssdw6EuC20ZwoUhCI46PTr3qvx57/kmmNoiTNf3c5mt2kQAF84rVI/tgI8kw=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=I/Qf+Jt8jBH61yX/14Jp1btkMWzHWiNR5UF+Cn43c64=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Add eMMC controller support to the BST C1200 device tree: - bstc1200.dtsi: Add mmc0 node for the DWCMSHC SDHCI controller with basic configuration (disabled by default) - bstc1200.dtsi: Add fixed clock definition for MMC controller - bstc1200-cdcu1.0-adas_4c2g.dts: Enable mmc0 with board-specific configuration including 8-bit bus width and reserved SRAM buffer The bounce buffer in reserved SRAM addresses hardware constraints where the eMMC controller cannot access main system memory through SMMU due to a hardware bug, and all DRAM is located outside the 4GB boundary. Signed-off-by: Albert Yang Acked-by: Gordon Ge --- Changes for v8: - Collected Acked-by: Gordon Ge - Rebased onto v7.1-rc1 - No code changes Changes for v7: - No code changes; resend with corrected recipients Changes for v5: - Split from platform series per Arnd's feedback Changes for v4: - Change compatible to bst,c1200-sdhci - Move bus-width and non-removable to board dts Changes for v3: - Split defconfig into dedicated patch Changes for v2: - Reorganize memory map, standardize interrupt definitions --- .../dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts | 19 +++++++++++++++++++ arch/arm64/boot/dts/bst/bstc1200.dtsi | 18 ++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts b/arch/= arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts index 5eb9ef369d8c..178ad4bf4f0a 100644 --- a/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts +++ b/arch/arm64/boot/dts/bst/bstc1200-cdcu1.0-adas_4c2g.dts @@ -17,6 +17,25 @@ memory@810000000 { <0x8 0xc0000000 0x1 0x0>, <0xc 0x00000000 0x0 0x40000000>; }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + mmc0_reserved: mmc0-reserved@5160000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x5160000 0x0 0x10000>; + no-map; + }; + }; +}; + +&mmc0 { + bus-width =3D <8>; + memory-region =3D <&mmc0_reserved>; + non-removable; + status =3D "okay"; }; =20 &uart0 { diff --git a/arch/arm64/boot/dts/bst/bstc1200.dtsi b/arch/arm64/boot/dts/bs= t/bstc1200.dtsi index dd13c6bfc3c8..9660d8396e27 100644 --- a/arch/arm64/boot/dts/bst/bstc1200.dtsi +++ b/arch/arm64/boot/dts/bst/bstc1200.dtsi @@ -7,6 +7,12 @@ / { #address-cells =3D <2>; #size-cells =3D <2>; =20 + clk_mmc: clock-4000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <4000000>; + }; + cpus { #address-cells =3D <1>; #size-cells =3D <0>; @@ -72,6 +78,18 @@ uart0: serial@20008000 { status =3D "disabled"; }; =20 + mmc0: mmc@22200000 { + compatible =3D "bst,c1200-sdhci"; + reg =3D <0x0 0x22200000 0x0 0x1000>, + <0x0 0x23006000 0x0 0x1000>; + clocks =3D <&clk_mmc>; + clock-names =3D "core"; + dma-coherent; + interrupts =3D ; + max-frequency =3D <200000000>; + status =3D "disabled"; + }; + gic: interrupt-controller@32800000 { compatible =3D "arm,gic-v3"; reg =3D <0x0 0x32800000 0x0 0x10000>, --=20 2.43.0 From nobody Wed Jun 17 07:26:44 2026 Received: from mail-m21468.qiye.163.com (mail-m21468.qiye.163.com [117.135.214.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29D7E548EE; Mon, 27 Apr 2026 06:28:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=117.135.214.68 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777271329; cv=none; b=XTNbjud9q+DByj7dLNf7CDujZDOQDICALGYIWh5Z3ichZYOVmtKz0nRsZ/y7sgtHNS6mvc+H+R8HlGqcUIRq2/dKL4OCPQMY3+R1vVpBL/Egu3iY1kCU1eCNmMsH31OSUk0JPa3PjY5xCVVKStYuiVxOw0X9pgxHpYH1xngTAxk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777271329; c=relaxed/simple; bh=qwW76CLWmNRGsuW0SKRXiavxkeIgUMY4k8Ecx+1HzmQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lwMcLLCxAP1i8YnR0rvM6/GsFgvozaLXvIoVWtmhg2cvQyVPh0QgmGCgD27pOrGUAR/TzkNuAmtTJjeziPRJ9Q6P30Rmo0CRohMjJHxVEv2FhLLTTWB3D4kqxFhLgKY8ZwjB4Khmzze85XZDtyOtIkUjcCZJ5tQkce6oOz+fOcE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com; spf=pass smtp.mailfrom=thundersoft.com; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b=mArF+uuW; arc=none smtp.client-ip=117.135.214.68 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=thundersoft.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=thundersoft.com header.i=@thundersoft.com header.b="mArF+uuW" Received: from albert-OptiPlex-7080.. (unknown [112.65.126.162]) by smtp.qiye.163.com (Hmail) with ESMTP id 3c40fa9ef; Mon, 27 Apr 2026 14:23:28 +0800 (GMT+08:00) From: Albert Yang To: gordon.ge@bst.ai, krzk@kernel.org, krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org, arnd@arndb.de, catalin.marinas@arm.com, will@kernel.org Cc: bst-upstream@bstai.top, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v8 2/2] arm64: defconfig: enable BST SDHCI controller Date: Mon, 27 Apr 2026 14:23:25 +0800 Message-ID: <20260427062326.3715732-3-yangzh0906@thundersoft.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427062326.3715732-1-yangzh0906@thundersoft.com> References: <20260427062326.3715732-1-yangzh0906@thundersoft.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-HM-Tid: 0a9dcd9b6d8e09cckunm8f7dadf41a30b9 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVkaHh1IVkhIGU1CQ0xPTBgeT1YVFA kWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlKSklVTU5VSklNVUpNSVlXWRYaDxIVHRRZQVlPS0hVSk tJT09PSFVKS0tVSkJLS1kG DKIM-Signature: a=rsa-sha256; b=mArF+uuWr4C2cXUiQuTPGM8K5XKOcpmfHAIi5pfGGMC/boTXvd2WXJlR+XqwT8T7ZGDcQAWD6apTpFIRXjrxLgWTO6BKLfRc2P1gfUMhGztzEKfqTTSUw3KRwIIz2lWPPQvfPwuipiAzczfq14mNZfH0Mg8qPjVuv/YApL9lgTM=; c=relaxed/relaxed; s=default; d=thundersoft.com; v=1; bh=zLe/JUqnW5/3GA47FWix+U9BvqXd61kPAp78FpLV5z8=; h=date:mime-version:subject:message-id:from; Content-Type: text/plain; charset="utf-8" Enable CONFIG_MMC_SDHCI_BST to support eMMC on Black Sesame Technologies C1200 boards. Signed-off-by: Albert Yang Acked-by: Gordon Ge --- Changes for v8: - Collected Acked-by: Gordon Ge - Rebased onto v7.1-rc1 - No code changes Changes for v7: - No code changes; resend with corrected recipients Changes for v6: - Fix CONFIG_MMC_SDHCI_BST ordering to match Kconfig position (between CONFIG_MMC_SDHCI_TEGRA and CONFIG_MMC_SDHCI_F_SDH30) as pointed out by Krzysztof Kozlowski. Confirmed via savedefconfig. Changes for v5: - Split from platform series per Arnd's feedback Changes for v4: - Move CONFIG_MMC_SDHCI_BST before CONFIG_MMC_SDHCI_F_SDH30 Changes for v3: - Split from arm64: dts patch Changes for v2: - Initial defconfig change included in DTS patch --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index d905a0777f93..304e12c80af9 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1292,6 +1292,7 @@ CONFIG_MMC_SDHCI_OF_SPARX5=3Dy CONFIG_MMC_SDHCI_CADENCE=3Dy CONFIG_MMC_SDHCI_ESDHC_IMX=3Dy CONFIG_MMC_SDHCI_TEGRA=3Dy +CONFIG_MMC_SDHCI_BST=3Dy CONFIG_MMC_SDHCI_F_SDH30=3Dy CONFIG_MMC_MESON_GX=3Dy CONFIG_MMC_SDHCI_MSM=3Dy --=20 2.43.0