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Signed-off-by: Deepti Jaggi Signed-off-by: Shawn Guo Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml= b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml index 90bfde66cc4a..c8107d58f3d5 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -20,6 +20,7 @@ properties: - enum: - qcom,glymur-cpucp-mbox - qcom,kaanapali-cpucp-mbox + - qcom,nord-cpucp-mbox - qcom,sm8750-cpucp-mbox - const: qcom,x1e80100-cpucp-mbox - enum: --=20 2.43.0 From nobody Tue Jun 16 12:44:10 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 813EB188CC9 for ; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12dca2c1c16sm11449051c88.5.2026.04.26.17.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Apr 2026 17:52:58 -0700 (PDT) From: Shawn Guo To: Jassi Brar Cc: Sibi Sankar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Dmitry Baryshkov , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Shawn Guo Subject: [PATCH v2 2/2] mailbox: qcom-cpucp: Add support for Nord CPUCP mailbox controller Date: Mon, 27 Apr 2026 08:52:36 +0800 Message-ID: <20260427005236.230106-3-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260427005236.230106-1-shengchao.guo@oss.qualcomm.com> References: <20260427005236.230106-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: gcE6qyoV6t_vS7JtdL896gzMurKEx_Mv X-Proofpoint-ORIG-GUID: gcE6qyoV6t_vS7JtdL896gzMurKEx_Mv X-Authority-Analysis: v=2.4 cv=TuPWQjXh c=1 sm=1 tr=0 ts=69eeb36d cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=OYxAFmqQ0AEWrUtYbScA:9 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI3MDAwNiBTYWx0ZWRfXyNHjBtYmvJsH bbUGqqXIlLUGqf6M4w0A4Q9zmsZ/crdXj4nSu7A9tK7gNPi4YIsG/G1vn6FN64/TCczMKo9QAl5 yS28MA5lh7RY/toNJtHeTFlKNHVlVachKrkCF50dcnTQbwz6FIDDQiQnjxH6oxBJw13dwSoOfD4 /uoctybFJVohPB4tzs0gOocXWVeJDzH6hfflTsP4mau65NBzIjz8z1AUpjIFmF4tsVm3SPjQy9N Tx3wWxGmQryycbU2In79+7Ng+gFgjUVj2ujtxRm8wihk8tguTq39QquYkBS+H2vpAduTjwBz9aQ U09hDK3GQ75tm/ZMBoGiCXXp/dYEDXu2HoW24swhPIksSfA5QtMh08MkWBGWBd0pWNKYXooVj47 69LZkfrkrbqQE1WljUjcM4uFJs5UkN+/y/Sjo2aJuqG1CqsFabzICRRZ9lS1QnQv+M2Swmkca84 w3b/UMF6Faf8x5d9ncw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-26_07,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 adultscore=0 malwarescore=0 impostorscore=0 clxscore=1015 suspectscore=0 phishscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604270006 Content-Type: text/plain; charset="utf-8" From: Deepti Jaggi The Nord SoC CPUCP mailbox supports 16 IPC channels, compared to 3 on x1e80100. The existing driver hardcodes the channel count via a compile-time constant (APSS_CPUCP_IPC_CHAN_SUPPORTED), making it impossible to support hardware with a different number of channels. Introduce a qcom_cpucp_mbox_data per-hardware configuration struct that carries the channel count, and retrieve it via of_device_get_match_data() at probe time. Switch the channel array from a fixed-size member to a dynamically allocated buffer sized from the hardware data. Update the x1e80100 entry to supply its own data struct, and add a new Nord entry with num_chans =3D 16. Signed-off-by: Deepti Jaggi Signed-off-by: Shawn Guo Reviewed-by: Konrad Dybcio --- drivers/mailbox/qcom-cpucp-mbox.c | 35 ++++++++++++++++++++++++++----- 1 file changed, 30 insertions(+), 5 deletions(-) diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp= -mbox.c index 44f4ed15f818..862e45e8fbd5 100644 --- a/drivers/mailbox/qcom-cpucp-mbox.c +++ b/drivers/mailbox/qcom-cpucp-mbox.c @@ -12,7 +12,6 @@ #include #include =20 -#define APSS_CPUCP_IPC_CHAN_SUPPORTED 3 #define APSS_CPUCP_MBOX_CMD_OFF 0x4 =20 /* Tx Registers */ @@ -26,6 +25,14 @@ #define APSS_CPUCP_RX_MBOX_EN 0x4c00 #define APSS_CPUCP_RX_MBOX_CMD_MASK GENMASK_ULL(63, 0) =20 +/** + * struct qcom_cpucp_mbox_data - Per-hardware mailbox configuration data + * @num_chans: Number of IPC channels supported by this hardware + */ +struct qcom_cpucp_mbox_data { + int num_chans; +}; + /** * struct qcom_cpucp_mbox - Holder for the mailbox driver * @chans: The mailbox channel @@ -34,7 +41,7 @@ * @rx_base: Base address of the CPUCP rx registers */ struct qcom_cpucp_mbox { - struct mbox_chan chans[APSS_CPUCP_IPC_CHAN_SUPPORTED]; + struct mbox_chan *chans; struct mbox_controller mbox; void __iomem *tx_base; void __iomem *rx_base; @@ -53,7 +60,7 @@ static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *= data) =20 status =3D readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); =20 - for_each_set_bit(i, (unsigned long *)&status, APSS_CPUCP_IPC_CHAN_SUPPORT= ED) { + for_each_set_bit(i, (unsigned long *)&status, cpucp->mbox.num_chans) { u32 val =3D readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUC= P_MBOX_CMD_OFF); struct mbox_chan *chan =3D &cpucp->chans[i]; unsigned long flags; @@ -112,15 +119,24 @@ static const struct mbox_chan_ops qcom_cpucp_mbox_cha= n_ops =3D { =20 static int qcom_cpucp_mbox_probe(struct platform_device *pdev) { + const struct qcom_cpucp_mbox_data *data; struct device *dev =3D &pdev->dev; struct qcom_cpucp_mbox *cpucp; struct mbox_controller *mbox; int irq, ret; =20 + data =3D of_device_get_match_data(dev); + if (!data) + return dev_err_probe(dev, -EINVAL, "No match data found\n"); + cpucp =3D devm_kzalloc(dev, sizeof(*cpucp), GFP_KERNEL); if (!cpucp) return -ENOMEM; =20 + cpucp->chans =3D devm_kcalloc(dev, data->num_chans, sizeof(*cpucp->chans)= , GFP_KERNEL); + if (!cpucp->chans) + return -ENOMEM; + cpucp->rx_base =3D devm_of_iomap(dev, dev->of_node, 0, NULL); if (IS_ERR(cpucp->rx_base)) return PTR_ERR(cpucp->rx_base); @@ -146,7 +162,7 @@ static int qcom_cpucp_mbox_probe(struct platform_device= *pdev) =20 mbox =3D &cpucp->mbox; mbox->dev =3D dev; - mbox->num_chans =3D APSS_CPUCP_IPC_CHAN_SUPPORTED; + mbox->num_chans =3D data->num_chans; mbox->chans =3D cpucp->chans; mbox->ops =3D &qcom_cpucp_mbox_chan_ops; =20 @@ -157,8 +173,17 @@ static int qcom_cpucp_mbox_probe(struct platform_devic= e *pdev) return 0; } =20 +static const struct qcom_cpucp_mbox_data qcom_x1e80100_mbox_data =3D { + .num_chans =3D 3, +}; + +static const struct qcom_cpucp_mbox_data qcom_nord_mbox_data =3D { + .num_chans =3D 16, +}; + static const struct of_device_id qcom_cpucp_mbox_of_match[] =3D { - { .compatible =3D "qcom,x1e80100-cpucp-mbox" }, + { .compatible =3D "qcom,nord-cpucp-mbox", .data =3D &qcom_nord_mbox_data = }, + { .compatible =3D "qcom,x1e80100-cpucp-mbox", .data =3D &qcom_x1e80100_mb= ox_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_cpucp_mbox_of_match); --=20 2.43.0