From nobody Thu Jun 11 12:17:23 2026 Received: from ultrarisc.com (unknown [218.76.62.146]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A872726056C; Mon, 27 Apr 2026 01:32:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=218.76.62.146 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777253566; cv=none; b=Fb1X743AdCfZm4kTbyPPeW++yuoH2bzatZtKMIUO1B9SvHvuszpDCYFBA3u3k8iXqdlwM9NWa/yRCj3xU3j0HfGj9KvVnZttFUJ55KMlG+Ef2Zw+KRT/XjSBQ3I2DnFEAnckQJxSJWmI3RlS7dmsR1qy975bv69FLZCsEtYUxUI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777253566; c=relaxed/simple; bh=k7xaltOxr1FPtLfLBpXG0T+uklw6wvxgverm552wOjM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XKDU3w6KbBAVRj0Il5Pc6tSIcsBGT3DzYzf1jPxnbrBbInP3gBKgF0p/1x8/zbBjXR0zq3hpVujgpK5ZYfFB5RxwRb7QRuP1kntvrN3QST1D3cHZ+E7KSROOvNgmBvVtOMQ8Szz9HKPgwedtx4E2RZKWfNyk3T1D2VoX9MkxNn0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ultrarisc.com; spf=pass smtp.mailfrom=ultrarisc.com; dkim=pass (1024-bit key) header.d=ultrarisc.com header.i=@ultrarisc.com header.b=hKPFaOWu; arc=none smtp.client-ip=218.76.62.146 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ultrarisc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ultrarisc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ultrarisc.com header.i=@ultrarisc.com header.b="hKPFaOWu" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ultrarisc.com; s=dkim; h=Received:From:Date:Subject: MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id: References:In-Reply-To:To:Cc; bh=eQFrKZlyykJUvAf7cH1ltvcwo0fJKri xuIUmANqBSKM=; b=hKPFaOWurshbXRPwokWX++MQJ0h5ALZ1vk7HqZrShy1ai5H aAH0+CUxhoA6I8YaI4p0ZUYf/mJ/3qJIaPb9JttMuVU6wDJ5FRJdrGtSTgt1aU1M Blc/rSuyD0KMUyvUqk+UFXreQEcDWSQE0XML9sg2mPg/RiKuTGx9GJB50oxo= Received: from [127.0.0.1] (unknown [192.168.100.1]) by localhost.localdomain (Coremail) with SMTP id AQAAfwA3cULPvO5ps_0CAA--.1758S3; Mon, 27 Apr 2026 09:33:06 +0800 (CST) From: Jia Wang Date: Mon, 27 Apr 2026 09:32:10 +0800 Subject: [PATCH v4 1/3] riscv: add UltraRISC SoC family Kconfig support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260427-ultrarisc-pcie-v4-1-98935f6cdfb5@ultrarisc.com> References: <20260427-ultrarisc-pcie-v4-0-98935f6cdfb5@ultrarisc.com> In-Reply-To: <20260427-ultrarisc-pcie-v4-0-98935f6cdfb5@ultrarisc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Jingoo Han , Xincheng Zhang , Krzysztof Kozlowski , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Jia Wang , Conor Dooley X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1777253539; l=811; i=wangjia@ultrarisc.com; s=20260309; h=from:subject:message-id; bh=k7xaltOxr1FPtLfLBpXG0T+uklw6wvxgverm552wOjM=; b=zaln2mLqZ1Yv0Fad/TPkjQDpkYqh8P2/CDZDbEDXOJQ2aHm+YQx0BCCsrZqUwqQ/c6+1CnQ7h jm6uQnLUiWhBRsVJyQ6/6hJBb9dWVbls9r9OlCy6OpCwlicJfG6NJO5 X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=XvYkrelqJIIzobY7j+nIg8rsfv5kzaOzuc1UPhd087U= X-CM-TRANSID: AQAAfwA3cULPvO5ps_0CAA--.1758S3 X-Coremail-Antispam: 1UD129KBjvdXoW7Jw45XFy3Xry8JF1Uuw1Utrb_yoW3ZFb_C3 4xJ348ZFyrAFW09a98Wrs3WF95Aws5WFy5Gr1ftryDuryxXw1xW3yDKr1jyw1Uuw15Xay8 XrZayFWfAryayjkaLaAFLSUrUUUUjb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUUUUUUU X-CM-SenderInfo: pzdqwylld63zxwud2x1vfou0bp/1tbiAQAKEWnti78ABQAAsv The first SoC in the UltraRISC series is UR-DP1000, containing octa UltraRISC CP100 cores. Signed-off-by: Jia Wang Acked-by: Conor Dooley --- arch/riscv/Kconfig.socs | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index d621b85dd63b..0b4d06a7b4bf 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -84,6 +84,12 @@ config ARCH_THEAD help This enables support for the RISC-V based T-HEAD SoCs. =20 +config ARCH_ULTRARISC + bool "UltraRISC RISC-V SoCs" + help + This enables support for UltraRISC SoC platform hardware, + including boards based on the UR-DP1000. + config ARCH_VIRT bool "QEMU Virt Machine" select POWER_RESET --=20 2.34.1 From nobody Thu Jun 11 12:17:23 2026 Received: from ultrarisc.com (unknown [218.76.62.146]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C28E8175A9A; Mon, 27 Apr 2026 01:32:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=218.76.62.146 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777253565; cv=none; b=dgl0UVwVX9pxBG/riL/fdxAKVg2mrL+clC+ji9HXyt5PMkR6xCv8kZCnhmwtmrboB6/Yi4LA8T2zU9pbNfnb6tqcOZJrEizfHiA4jrh5DOKJnbv+QebuaJzYINrSXndWAcajcXmHXvU6Bi+qWmWv85ZPhv+8ek/gei8zGO1c0aE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777253565; c=relaxed/simple; bh=X2bzlR0Ihg946bcqWPf1jyyPRrQHRRPJWRN220hfPCo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Pk2jymAb5Wgv1+f8Dl29qUyVuarQTdICVlckgd+FzLgP5BgjiO9tNcxqgGnordVdxRwuei6B67Ib9Zws23MKiB2Fzme6hqm/szZBXH+fdheuDpHdF7ADS+RNrhFbDBMe4Qe8CdZfLQ4jSz4Uo1ve/wPa4oClruNw7EgbIfsjXVM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ultrarisc.com; spf=pass smtp.mailfrom=ultrarisc.com; dkim=pass (1024-bit key) header.d=ultrarisc.com header.i=@ultrarisc.com header.b=AFal1g22; arc=none smtp.client-ip=218.76.62.146 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ultrarisc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ultrarisc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ultrarisc.com header.i=@ultrarisc.com header.b="AFal1g22" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ultrarisc.com; s=dkim; h=Received:From:Date:Subject: MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id: References:In-Reply-To:To:Cc; bh=HYT/JtcTeb4xRDUsI9fYBdNKr0Iy0dm MBfAidPI4MF0=; b=AFal1g22bTU1RB0ZyPdZxZh1Gr5dgbxDw1U3ujsC7Ba4e19 g/Co9uTO78COGOtBGNerxdqBcZbJvRIVPeIzWswL3Yzx1q45rElfpcB/Vx40MiHJ 7gu9G9fbs7JSYHSlgxvu697lLEpkMAWy5VAM6rK79H8BElhFvnWGnyCW5CeU= Received: from [127.0.0.1] (unknown [192.168.100.1]) by localhost.localdomain (Coremail) with SMTP id AQAAfwA3cULPvO5ps_0CAA--.1758S4; Mon, 27 Apr 2026 09:33:07 +0800 (CST) From: Jia Wang Date: Mon, 27 Apr 2026 09:32:11 +0800 Subject: [PATCH v4 2/3] dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260427-ultrarisc-pcie-v4-2-98935f6cdfb5@ultrarisc.com> References: <20260427-ultrarisc-pcie-v4-0-98935f6cdfb5@ultrarisc.com> In-Reply-To: <20260427-ultrarisc-pcie-v4-0-98935f6cdfb5@ultrarisc.com> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Jingoo Han , Xincheng Zhang , Krzysztof Kozlowski , Conor Dooley Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Jia Wang , Krzysztof Kozlowski X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1777253539; l=3982; i=wangjia@ultrarisc.com; s=20260309; h=from:subject:message-id; bh=X2bzlR0Ihg946bcqWPf1jyyPRrQHRRPJWRN220hfPCo=; b=lshqQvLyVCLepawcXw2Cbbkx0v3nUFfXgwvfeqxhZwaD45Ew/JmEnP0f8MOvq2H/eUjgWrpFx rV+O9xzlmGQDmAr1ex4NAvl1/AGEZK4jTxc0cv1tFgVvXCt79CpmbSP X-Developer-Key: i=wangjia@ultrarisc.com; a=ed25519; pk=XvYkrelqJIIzobY7j+nIg8rsfv5kzaOzuc1UPhd087U= X-CM-TRANSID: AQAAfwA3cULPvO5ps_0CAA--.1758S4 X-Coremail-Antispam: 1UD129KBjvJXoWxGryDXryUGw15XrW5WFW8Xrb_yoW5Kw17pF WUCa4kuF4xtr13uw4fK3W0kF15XF4vkF9YywnFgw1UtFZYgw1jqrsIkw13G3W5Gr4UXry2 gFn0kr17Kw4UAw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnUUvcSsGvfC2KfnxnUUI43ZEXa7xR_UUUUUUUUU== X-CM-SenderInfo: pzdqwylld63zxwud2x1vfou0bp/1tbiAQAKEWnti78ABwAAst Add UltraRISC DP1000 SoC PCIe controller devicetree bindings. Signed-off-by: Jia Wang Reviewed-by: Krzysztof Kozlowski --- .../bindings/pci/ultrarisc,dp1000-pcie.yaml | 93 ++++++++++++++++++= ++++ MAINTAINERS | 7 ++ 2 files changed, 100 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.ya= ml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml new file mode 100644 index 000000000000..512b935bf5d1 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC DP1000 PCIe Host Controller + +description: + UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCI= e IP. + +maintainers: + - Xincheng Zhang + - Jia Wang + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: ultrarisc,dp1000-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: config + + num-lanes: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [4, 16] + description: Number of lanes to use. + + interrupts: + items: + - description: MSI interrupt + - description: Legacy INTA interrupt + - description: Legacy INTB interrupt + - description: Legacy INTC interrupt + - description: Legacy INTD interrupt + + interrupt-names: + items: + - const: msi + - const: inta + - const: intb + - const: intc + - const: intd + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@21000000 { + compatible =3D "ultrarisc,dp1000-pcie"; + reg =3D <0x0 0x21000000 0x0 0x01000000>, + <0x0 0x4fff0000 0x0 0x00010000>; + reg-names =3D "dbi", "config"; + ranges =3D <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x0040000= 0>, + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, + <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x0000000= 0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + #interrupt-cells =3D <1>; + device_type =3D "pci"; + dma-coherent; + bus-range =3D <0x0 0xff>; + num-lanes =3D <16>; + interrupt-parent =3D <&plic>; + interrupts =3D <43>, <44>, <45>, <46>, <47>; + interrupt-names =3D "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask =3D <0x0 0x0 0x0 0x7>; + interrupt-map =3D <0x0 0x0 0x0 0x1 &plic 44>, + <0x0 0x0 0x0 0x2 &plic 45>, + <0x0 0x0 0x0 0x3 &plic 46>, + <0x0 0x0 0x0 0x4 &plic 47>; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index d238590a31f2..818685933541 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20583,6 +20583,13 @@ S: Maintained F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml F: drivers/pci/controller/plda/pcie-starfive.c =20 +PCIE DRIVER FOR ULTRARISC DP1000 +M: Xincheng Zhang +M: Jia Wang +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml + PCIE ENDPOINT DRIVER FOR QUALCOMM M: Manivannan Sadhasivam L: linux-pci@vger.kernel.org --=20 2.34.1 From nobody Thu Jun 11 12:17:23 2026 Received: from ultrarisc.com (unknown [218.76.62.146]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 12A441E1DF0; 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The controller only supports 32-bit aligned configuration space accesses. Signed-off-by: Xincheng Zhang Signed-off-by: Jia Wang --- MAINTAINERS | 1 + drivers/pci/controller/dwc/Kconfig | 12 ++ drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-designware.h | 22 ++++ drivers/pci/controller/dwc/pcie-ultrarisc.c | 175 +++++++++++++++++++++++= ++++ 5 files changed, 211 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 818685933541..16203b804c16 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20589,6 +20589,7 @@ M: Jia Wang L: linux-pci@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml +F: drivers/pci/controller/dwc/pcie-ultrarisc.c =20 PCIE ENDPOINT DRIVER FOR QUALCOMM M: Manivannan Sadhasivam diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index d0aa031397fa..06f7d98259cd 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -548,4 +548,16 @@ config PCIE_VISCONTI_HOST Say Y here if you want PCIe controller support on Toshiba Visconti SoC. This driver supports TMPV7708 SoC. =20 +config PCIE_ULTRARISC + tristate "UltraRISC PCIe host controller" + depends on ARCH_ULTRARISC || COMPILE_TEST + select PCIE_DW_HOST + select PCI_MSI + default y if ARCH_ULTRARISC + help + Enables support for the PCIe controller in the UltraRISC SoC. + This driver supports UR-DP1000 SoC. + By default, this symbol is enabled when ARCH_ULTRARISC is active, + requiring no further configuration on that platform. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/d= wc/Makefile index 67ba59c02038..884c46b78e01 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -38,6 +38,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) +=3D pcie-rcar-gen4.o obj-$(CONFIG_PCIE_SPACEMIT_K1) +=3D pcie-spacemit-k1.o obj-$(CONFIG_PCIE_STM32_HOST) +=3D pcie-stm32.o obj-$(CONFIG_PCIE_STM32_EP) +=3D pcie-stm32-ep.o +obj-$(CONFIG_PCIE_ULTRARISC) +=3D pcie-ultrarisc.o =20 # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index ae6389dd9caa..88dcb0e7943a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -69,6 +69,8 @@ =20 /* Synopsys-specific PCIe configuration registers */ #define PCIE_PORT_FORCE 0x708 +/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */ +#define PORT_LINK_NUM_MASK GENMASK(7, 0) #define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23) =20 #define PCIE_PORT_AFR 0x70C @@ -96,6 +98,26 @@ #define PCIE_PORT_LANE_SKEW 0x714 #define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0) =20 +/* + * PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number + * Register. + * This register holds the ack frequency, latency, replay, fast link + * scaling timers, and max function number values. + * Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor. + * 0x0 (SF_1024):Scaling Factor is 1024 (1ms is 1us). + * When the LTSSM is in Config or L12 Entry State, 1ms + * timer is 2us, 2ms timer is 4us and 3ms timer is 6us. + * 0x1 (SF_256): Scaling Factor is 256 (1ms is 4us) + * 0x2 (SF_64): Scaling Factor is 64 (1ms is 16us) + * 0x3 (SF_16): Scaling Factor is 16 (1ms is 64us) + */ +#define PCIE_TIMER_CTRL_MAX_FUNC_NUM 0x718 +#define PORT_FLT_SF_MASK GENMASK(30, 29) +#define PORT_FLT_SF_VAL_1024 0x0 +#define PORT_FLT_SF_VAL_256 0x1 +#define PORT_FLT_SF_VAL_64 0x2 +#define PORT_FLT_SF_VAL_16 0x3 + #define PCIE_PORT_DEBUG0 0x728 #define PORT_LOGIC_LTSSM_STATE_MASK 0x3f #define PORT_LOGIC_LTSSM_STATE_L0 0x11 diff --git a/drivers/pci/controller/dwc/pcie-ultrarisc.c b/drivers/pci/cont= roller/dwc/pcie-ultrarisc.c new file mode 100644 index 000000000000..7326bd446590 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-ultrarisc.c @@ -0,0 +1,175 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * DWC PCIe RC driver for UltraRISC SoCs + * + * Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include + +#include "pcie-designware.h" + +#define PCIE_CUS_CORE 0x400000 + +#define LTSSM_ENABLE BIT(7) +#define FAST_LINK_MODE BIT(12) +#define HOLD_PHY_RST BIT(14) +#define L1SUB_DISABLE BIT(15) + +#define ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS 0x6 + +static struct pci_ops ultrarisc_pci_ops =3D { + .map_bus =3D dw_pcie_own_conf_map_bus, + .read =3D pci_generic_config_read32, + .write =3D pci_generic_config_write32, +}; + +static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct pci_host_bridge *bridge =3D pp->bridge; + u8 cap_exp; + u32 val; + + bridge->ops =3D &ultrarisc_pci_ops; + + if (dw_pcie_link_up(pci)) + return 0; + + val =3D dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); + val &=3D ~FAST_LINK_MODE; + dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); + + val =3D dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM); + FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64); + dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val); + + cap_exp =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + val =3D dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2); + FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT); + dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val); + + val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE); + FIELD_MODIFY(PORT_LINK_NUM_MASK, &val, 0); + dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val); + + val =3D dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2); + FIELD_MODIFY(PCI_EXP_DEVCTL2_COMP_TIMEOUT, &val, + ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS); + dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val); + + val =3D dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); + val &=3D ~(HOLD_PHY_RST | L1SUB_DISABLE); + dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); + + return 0; +} + +static void ultrarisc_pcie_pme_turn_off(struct dw_pcie_rp *pp) +{ + /* + * DP1000 does not support sending PME_Turn_Off from the RC. + * Keep this callback empty to skip the generic MSG TLP path. + */ +} + +static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops =3D { + .init =3D ultrarisc_pcie_host_init, + .pme_turn_off =3D ultrarisc_pcie_pme_turn_off, +}; + +static int ultrarisc_pcie_start_link(struct dw_pcie *pci) +{ + u32 val; + + val =3D dw_pcie_readl_dbi(pci, PCIE_CUS_CORE); + val |=3D LTSSM_ENABLE; + dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val); + + return 0; +} + +static const struct dw_pcie_ops dw_pcie_ops =3D { + .start_link =3D ultrarisc_pcie_start_link, +}; + +static int ultrarisc_pcie_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct dw_pcie_rp *pp; + struct dw_pcie *pci; + int ret; + + pci =3D devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); + if (!pci) + return -ENOMEM; + + pci->dev =3D dev; + pci->ops =3D &dw_pcie_ops; + + /* Set a default value suitable for at most 16 in and 16 out windows */ + pci->atu_size =3D SZ_8K; + + pp =3D &pci->pp; + + platform_set_drvdata(pdev, pci); + + pp->num_vectors =3D MAX_MSI_IRQS; + /* No L2/L3 Ready indication is available on this platform. */ + pp->skip_l23_ready =3D true; + pp->ops =3D &ultrarisc_pcie_host_ops; + + ret =3D dw_pcie_host_init(pp); + if (ret) { + dev_err(dev, "Failed to initialize host\n"); + return ret; + } + + return 0; +} + +static int ultrarisc_pcie_suspend_noirq(struct device *dev) +{ + struct dw_pcie *pci =3D dev_get_drvdata(dev); + + return dw_pcie_suspend_noirq(pci); +} + +static int ultrarisc_pcie_resume_noirq(struct device *dev) +{ + struct dw_pcie *pci =3D dev_get_drvdata(dev); + + return dw_pcie_resume_noirq(pci); +} + +static const struct dev_pm_ops ultrarisc_pcie_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(ultrarisc_pcie_suspend_noirq, + ultrarisc_pcie_resume_noirq) +}; + +static const struct of_device_id ultrarisc_pcie_of_match[] =3D { + { + .compatible =3D "ultrarisc,dp1000-pcie", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, ultrarisc_pcie_of_match); + +static struct platform_driver ultrarisc_pcie_driver =3D { + .driver =3D { + .name =3D "ultrarisc-pcie", + .of_match_table =3D ultrarisc_pcie_of_match, + .suppress_bind_attrs =3D true, + .pm =3D &ultrarisc_pcie_pm_ops, + }, + .probe =3D ultrarisc_pcie_probe, +}; +module_platform_driver(ultrarisc_pcie_driver); + +MODULE_DESCRIPTION("UltraRISC DP1000 DWC PCIe host controller"); +MODULE_LICENSE("GPL"); --=20 2.34.1