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This allows memory to be allocated based on the actual number of triggers during probe time, reducing memory footprint and improving scalability for platforms with varying trigger counts. Signed-off-by: Yingchao Deng Reviewed-by: Leo Yan --- drivers/hwtracing/coresight/coresight-cti-core.c | 59 +++++++++++++++++-= ---- .../hwtracing/coresight/coresight-cti-platform.c | 26 +++++++--- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 14 ++--- drivers/hwtracing/coresight/coresight-cti.h | 12 ++--- 4 files changed, 76 insertions(+), 35 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 2f4c9362709a..4e7d12bd2d3e 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -161,8 +161,8 @@ void cti_write_intack(struct device *dev, u32 ackval) /* DEVID[19:16] - number of CTM channels */ #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) =20 -static void cti_set_default_config(struct device *dev, - struct cti_drvdata *drvdata) +static int cti_set_default_config(struct device *dev, + struct cti_drvdata *drvdata) { struct cti_config *config =3D &drvdata->config; u32 devid; @@ -181,6 +181,26 @@ static void cti_set_default_config(struct device *dev, config->nr_trig_max =3D CTIINOUTEN_MAX; } =20 + config->trig_in_use =3D devm_bitmap_zalloc(dev, config->nr_trig_max, GFP_= KERNEL); + if (!config->trig_in_use) + return -ENOMEM; + + config->trig_out_use =3D devm_bitmap_zalloc(dev, config->nr_trig_max, GFP= _KERNEL); + if (!config->trig_out_use) + return -ENOMEM; + + config->trig_out_filter =3D devm_bitmap_zalloc(dev, config->nr_trig_max, = GFP_KERNEL); + if (!config->trig_out_filter) + return -ENOMEM; + + config->ctiinen =3D devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), G= FP_KERNEL); + if (!config->ctiinen) + return -ENOMEM; + + config->ctiouten =3D devm_kcalloc(dev, config->nr_trig_max, sizeof(u32), = GFP_KERNEL); + if (!config->ctiouten) + return -ENOMEM; + config->nr_ctm_channels =3D CTI_DEVID_CTMCHANNELS(devid); =20 /* Most regs default to 0 as zalloc'ed except...*/ @@ -189,6 +209,7 @@ static void cti_set_default_config(struct device *dev, config->enable_req_count =3D 0; =20 config->asicctl_impl =3D !!FIELD_GET(GENMASK(4, 0), devid); + return 0; } =20 /* @@ -219,8 +240,10 @@ int cti_add_connection_entry(struct device *dev, struc= t cti_drvdata *drvdata, cti_dev->nr_trig_con++; =20 /* add connection usage bit info to overall info */ - drvdata->config.trig_in_use |=3D tc->con_in->used_mask; - drvdata->config.trig_out_use |=3D tc->con_out->used_mask; + bitmap_or(drvdata->config.trig_in_use, drvdata->config.trig_in_use, + tc->con_in->used_mask, drvdata->config.nr_trig_max); + bitmap_or(drvdata->config.trig_out_use, drvdata->config.trig_out_use, + tc->con_out->used_mask, drvdata->config.nr_trig_max); =20 return 0; } @@ -231,6 +254,8 @@ struct cti_trig_con *cti_allocate_trig_con(struct devic= e *dev, int in_sigs, { struct cti_trig_con *tc =3D NULL; struct cti_trig_grp *in =3D NULL, *out =3D NULL; + struct cti_drvdata *drvdata =3D dev_get_drvdata(dev); + int n_trigs =3D drvdata->config.nr_trig_max; =20 tc =3D devm_kzalloc(dev, sizeof(struct cti_trig_con), GFP_KERNEL); if (!tc) @@ -242,12 +267,20 @@ struct cti_trig_con *cti_allocate_trig_con(struct dev= ice *dev, int in_sigs, if (!in) return NULL; =20 + in->used_mask =3D devm_bitmap_zalloc(dev, n_trigs, GFP_KERNEL); + if (!in->used_mask) + return NULL; + out =3D devm_kzalloc(dev, offsetof(struct cti_trig_grp, sig_types[out_sigs]), GFP_KERNEL); if (!out) return NULL; =20 + out->used_mask =3D devm_bitmap_zalloc(dev, n_trigs, GFP_KERNEL); + if (!out->used_mask) + return NULL; + tc->con_in =3D in; tc->con_out =3D out; tc->con_in->nr_sigs =3D in_sigs; @@ -263,7 +296,6 @@ int cti_add_default_connection(struct device *dev, stru= ct cti_drvdata *drvdata) { int ret =3D 0; int n_trigs =3D drvdata->config.nr_trig_max; - u32 n_trig_mask =3D GENMASK(n_trigs - 1, 0); struct cti_trig_con *tc =3D NULL; =20 /* @@ -274,8 +306,8 @@ int cti_add_default_connection(struct device *dev, stru= ct cti_drvdata *drvdata) if (!tc) return -ENOMEM; =20 - tc->con_in->used_mask =3D n_trig_mask; - tc->con_out->used_mask =3D n_trig_mask; + bitmap_fill(tc->con_in->used_mask, n_trigs); + bitmap_fill(tc->con_out->used_mask, n_trigs); ret =3D cti_add_connection_entry(dev, drvdata, tc, NULL, "default"); return ret; } @@ -288,7 +320,6 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, { struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *config =3D &drvdata->config; - u32 trig_bitmask; u32 chan_bitmask; u32 reg_value; int reg_offset; @@ -298,18 +329,16 @@ int cti_channel_trig_op(struct device *dev, enum cti_= chan_op op, (trigger_idx >=3D config->nr_trig_max)) return -EINVAL; =20 - trig_bitmask =3D BIT(trigger_idx); - /* ensure registered triggers and not out filtered */ if (direction =3D=3D CTI_TRIG_IN) { - if (!(trig_bitmask & config->trig_in_use)) + if (!(test_bit(trigger_idx, config->trig_in_use))) return -EINVAL; } else { - if (!(trig_bitmask & config->trig_out_use)) + if (!(test_bit(trigger_idx, config->trig_out_use))) return -EINVAL; =20 if ((config->trig_filter_enable) && - (config->trig_out_filter & trig_bitmask)) + test_bit(trigger_idx, config->trig_out_filter)) return -EINVAL; } =20 @@ -687,7 +716,9 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) raw_spin_lock_init(&drvdata->spinlock); =20 /* initialise CTI driver config values */ - cti_set_default_config(dev, drvdata); + ret =3D cti_set_default_config(dev, drvdata); + if (ret) + return ret; =20 pdata =3D coresight_cti_get_platform_data(dev); if (IS_ERR(pdata)) { diff --git a/drivers/hwtracing/coresight/coresight-cti-platform.c b/drivers= /hwtracing/coresight/coresight-cti-platform.c index 4eff96f48594..557debbc8ca4 100644 --- a/drivers/hwtracing/coresight/coresight-cti-platform.c +++ b/drivers/hwtracing/coresight/coresight-cti-platform.c @@ -136,8 +136,8 @@ static int cti_plat_create_v8_etm_connection(struct dev= ice *dev, goto create_v8_etm_out; =20 /* build connection data */ - tc->con_in->used_mask =3D 0xF0; /* sigs <4,5,6,7> */ - tc->con_out->used_mask =3D 0xF0; /* sigs <4,5,6,7> */ + bitmap_set(tc->con_in->used_mask, 4, 4); /* sigs <4,5,6,7> */ + bitmap_set(tc->con_out->used_mask, 4, 4); /* sigs <4,5,6,7> */ =20 /* * The EXTOUT type signals from the ETM are connected to a set of input @@ -194,10 +194,10 @@ static int cti_plat_create_v8_connections(struct devi= ce *dev, goto of_create_v8_out; =20 /* Set the v8 PE CTI connection data */ - tc->con_in->used_mask =3D 0x3; /* sigs <0 1> */ + bitmap_set(tc->con_in->used_mask, 0, 2); /* sigs <0 1> */ tc->con_in->sig_types[0] =3D PE_DBGTRIGGER; tc->con_in->sig_types[1] =3D PE_PMUIRQ; - tc->con_out->used_mask =3D 0x7; /* sigs <0 1 2 > */ + bitmap_set(tc->con_out->used_mask, 0, 3); /* sigs <0 1 2 > */ tc->con_out->sig_types[0] =3D PE_EDBGREQ; tc->con_out->sig_types[1] =3D PE_DBGRESTART; tc->con_out->sig_types[2] =3D PE_CTIIRQ; @@ -213,7 +213,7 @@ static int cti_plat_create_v8_connections(struct device= *dev, goto of_create_v8_out; =20 /* filter pe_edbgreq - PE trigout sig <0> */ - drvdata->config.trig_out_filter |=3D 0x1; + set_bit(0, drvdata->config.trig_out_filter); =20 of_create_v8_out: return ret; @@ -257,7 +257,7 @@ static int cti_plat_read_trig_group(struct cti_trig_grp= *tgrp, if (!err) { /* set the signal usage mask */ for (idx =3D 0; idx < tgrp->nr_sigs; idx++) - tgrp->used_mask |=3D BIT(values[idx]); + set_bit(values[idx], tgrp->used_mask); } =20 kfree(values); @@ -316,23 +316,33 @@ static int cti_plat_process_filter_sigs(struct cti_dr= vdata *drvdata, { struct cti_trig_grp *tg =3D NULL; int err =3D 0, nr_filter_sigs; + int nr_trigs =3D drvdata->config.nr_trig_max; =20 nr_filter_sigs =3D cti_plat_count_sig_elements(fwnode, CTI_DT_FILTER_OUT_SIGS); if (nr_filter_sigs =3D=3D 0) return 0; =20 - if (nr_filter_sigs > drvdata->config.nr_trig_max) + if (nr_filter_sigs > nr_trigs) return -EINVAL; =20 tg =3D kzalloc_obj(*tg); if (!tg) return -ENOMEM; =20 + tg->used_mask =3D bitmap_zalloc(nr_trigs, GFP_KERNEL); + if (!tg->used_mask) { + kfree(tg); + return -ENOMEM; + } + err =3D cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS); if (!err) - drvdata->config.trig_out_filter |=3D tg->used_mask; + bitmap_or(drvdata->config.trig_out_filter, + drvdata->config.trig_out_filter, + tg->used_mask, nr_trigs); =20 + bitmap_free(tg->used_mask); kfree(tg); return err; } diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 3fe2c916d228..2bbfa405cb6b 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -719,12 +719,12 @@ static ssize_t trigout_filtered_show(struct device *d= ev, struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; int nr_trig_max =3D cfg->nr_trig_max; - unsigned long mask =3D cfg->trig_out_filter; + unsigned long *mask =3D cfg->trig_out_filter; =20 - if (mask =3D=3D 0) + if (bitmap_empty(mask, nr_trig_max)) return 0; =20 - return sysfs_emit(buf, "%*pbl\n", nr_trig_max, &mask); + return sysfs_emit(buf, "%*pbl\n", nr_trig_max, mask); } static DEVICE_ATTR_RO(trigout_filtered); =20 @@ -931,9 +931,9 @@ static ssize_t trigin_sig_show(struct device *dev, struct cti_trig_con *con =3D (struct cti_trig_con *)ext_attr->var; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; - unsigned long mask =3D con->con_in->used_mask; + unsigned long *mask =3D con->con_in->used_mask; =20 - return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, &mask); + return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, mask); } =20 static ssize_t trigout_sig_show(struct device *dev, @@ -945,9 +945,9 @@ static ssize_t trigout_sig_show(struct device *dev, struct cti_trig_con *con =3D (struct cti_trig_con *)ext_attr->var; struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct cti_config *cfg =3D &drvdata->config; - unsigned long mask =3D con->con_out->used_mask; + unsigned long *mask =3D con->con_out->used_mask; =20 - return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, &mask); + return sysfs_emit(buf, "%*pbl\n", cfg->nr_trig_max, mask); } =20 /* convert a sig type id to a name */ diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index c5f9e79fabc6..ef079fc18b72 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -68,7 +68,7 @@ struct fwnode_handle; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b5fab208d4sm294960905ad.55.2026.04.26.02.45.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Apr 2026 02:45:07 -0700 (PDT) From: Yingchao Deng Date: Sun, 26 Apr 2026 17:44:39 +0800 Subject: [PATCH v8 2/4] coresight: cti: encode trigger register index in register offsets Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260426-extended-cti-v8-2-23b900a4902f@oss.qualcomm.com> References: <20260426-extended-cti-v8-0-23b900a4902f@oss.qualcomm.com> In-Reply-To: <20260426-extended-cti-v8-0-23b900a4902f@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_yingdeng@quicinc.com, Jinlong Mao , Tingwei Zhang , Jie Gan , Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777196695; l=6125; i=yingchao.deng@oss.qualcomm.com; s=20260426; h=from:subject:message-id; bh=RTsLaYVLZsWbbMOZumDU3n539t32lNjAo8QQqqvI4Zo=; b=pdxoK888+GzGQuMMx9eZ2XIJmH6NZuYJ19tPDe0spNNCZ2u7wlKxqg4BiVWFr//D+1IWqosX+ fSayxSODS08Ape0rthWit7LG6odGbNnSk2tQT6QRjDFoVSP4n/eWFSI X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=aufKZC4I8k2lqi+B/z87rB5kPPybOn8C3mLosbtw+no= X-Proofpoint-GUID: PCD_mMQdZeYvESfkdi223H7-FHVMMwyF X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI2MDEwMyBTYWx0ZWRfXwiFr1eYFco0m 3wUMQjarcyKFIVeGGKAY/4gYvh/v7JUmU9u2iQpHInVSzIIokUK3ouVuCfZLw7k5ZX16WgqjjrF CTgAdV9Y1Pk5RvRliA7SmcqZ85i/QIkTqrrtjleUQagj/9b8ElXBvoFDJ7lvgkA1OTzi66rLOdz 2EXsKTMV1n11nXzG3v4Byr/pR05nWy/yyswVDTiurd0pU1dqPFhv9vCvS+hcANJBQoOrW7KZJhd lPonsRS3SoG9bTj3/tpkratVXm3eAwCaqvgGELWdDZ5/z7cIS9V+rZlpzkxdnuHOfw9UiHFB3fB dobcC8mBz3cNnARuUXJ2MYvc7MFHD7y3U45GiZbGXeAMWavSAz5lPT//uWkujtMxXWxpfE7wgzc WPsk53+d1jMSEOEjhCrdBoLWZmT49x3M5AWUSteUuPxK6qJZvCbJ2Fzq9zYbulrAB/Ea7u6Ucnt rBu/DAZeIWiz2vNBdhA== X-Proofpoint-ORIG-GUID: PCD_mMQdZeYvESfkdi223H7-FHVMMwyF X-Authority-Analysis: v=2.4 cv=J/GaKgnS c=1 sm=1 tr=0 ts=69eddea4 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=JIbpoTx20AKeDh2nFAsA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-26_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 adultscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604260103 Introduce a small encoding to carry the register index together with the base offset in a single u32, and use a common helper to compute the final MMIO address. This refactors register access to be based on the encoded (reg, nr) pair, reducing duplicated arithmetic and making it easier to support variants that bank or relocate trigger-indexed registers. Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-core.c | 31 +++++++++++++++----= ---- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 4 +-- drivers/hwtracing/coresight/coresight-cti.h | 16 ++++++++++-- 3 files changed, 36 insertions(+), 15 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 4e7d12bd2d3e..c4cbeb64365b 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -42,6 +42,14 @@ static DEFINE_MUTEX(ect_mutex); #define csdev_to_cti_drvdata(csdev) \ dev_get_drvdata(csdev->dev.parent) =20 +static void __iomem *cti_reg_addr(struct cti_drvdata *drvdata, int reg) +{ + u32 offset =3D CTI_REG_CLR_NR(reg); + u32 nr =3D CTI_REG_GET_NR(reg); + + return drvdata->base + offset + sizeof(u32) * nr; +} + /* write set of regs to hardware - call with spinlock claimed */ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) { @@ -55,16 +63,17 @@ void cti_write_all_hw_regs(struct cti_drvdata *drvdata) =20 /* write the CTI trigger registers */ for (i =3D 0; i < config->nr_trig_max; i++) { - writel_relaxed(config->ctiinen[i], drvdata->base + CTIINEN(i)); + writel_relaxed(config->ctiinen[i], + cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIINEN, i))); writel_relaxed(config->ctiouten[i], - drvdata->base + CTIOUTEN(i)); + cti_reg_addr(drvdata, CTI_REG_SET_NR(CTIOUTEN, i))); } =20 /* other regs */ - writel_relaxed(config->ctigate, drvdata->base + CTIGATE); + writel_relaxed(config->ctigate, cti_reg_addr(drvdata, CTIGATE)); if (config->asicctl_impl) - writel_relaxed(config->asicctl, drvdata->base + ASICCTL); - writel_relaxed(config->ctiappset, drvdata->base + CTIAPPSET); + writel_relaxed(config->asicctl, cti_reg_addr(drvdata, ASICCTL)); + writel_relaxed(config->ctiappset, cti_reg_addr(drvdata, CTIAPPSET)); =20 /* re-enable CTI */ writel_relaxed(1, drvdata->base + CTICONTROL); @@ -127,7 +136,7 @@ u32 cti_read_single_reg(struct cti_drvdata *drvdata, in= t offset) int val; =20 CS_UNLOCK(drvdata->base); - val =3D readl_relaxed(drvdata->base + offset); + val =3D readl_relaxed(cti_reg_addr(drvdata, offset)); CS_LOCK(drvdata->base); =20 return val; @@ -136,7 +145,7 @@ u32 cti_read_single_reg(struct cti_drvdata *drvdata, in= t offset) void cti_write_single_reg(struct cti_drvdata *drvdata, int offset, u32 val= ue) { CS_UNLOCK(drvdata->base); - writel_relaxed(value, drvdata->base + offset); + writel_relaxed(value, cti_reg_addr(drvdata, offset)); CS_LOCK(drvdata->base); } =20 @@ -344,8 +353,7 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, =20 /* update the local register values */ chan_bitmask =3D BIT(channel_idx); - reg_offset =3D (direction =3D=3D CTI_TRIG_IN ? CTIINEN(trigger_idx) : - CTIOUTEN(trigger_idx)); + reg_offset =3D (direction =3D=3D CTI_TRIG_IN ? CTIINEN : CTIOUTEN); =20 guard(raw_spinlock_irqsave)(&drvdata->spinlock); =20 @@ -365,8 +373,9 @@ int cti_channel_trig_op(struct device *dev, enum cti_ch= an_op op, =20 /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, reg_offset, reg_value); - + cti_write_single_reg(drvdata, + CTI_REG_SET_NR(reg_offset, trigger_idx), + reg_value); return 0; } =20 diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 2bbfa405cb6b..8b70e7e38ea3 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -386,7 +386,7 @@ static ssize_t inen_store(struct device *dev, =20 /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIINEN(index), val); + cti_write_single_reg(drvdata, CTI_REG_SET_NR(CTIINEN, index), val); =20 return size; } @@ -427,7 +427,7 @@ static ssize_t outen_store(struct device *dev, =20 /* write through if enabled */ if (cti_is_active(config)) - cti_write_single_reg(drvdata, CTIOUTEN(index), val); + cti_write_single_reg(drvdata, CTI_REG_SET_NR(CTIOUTEN, index), val); =20 return size; } diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index ef079fc18b72..dd1ba44518c4 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -7,6 +7,7 @@ #ifndef _CORESIGHT_CORESIGHT_CTI_H #define _CORESIGHT_CORESIGHT_CTI_H =20 +#include #include #include #include @@ -30,8 +31,8 @@ struct fwnode_handle; #define CTIAPPSET 0x014 #define CTIAPPCLEAR 0x018 #define CTIAPPPULSE 0x01C -#define CTIINEN(n) (0x020 + (4 * n)) -#define CTIOUTEN(n) (0x0A0 + (4 * n)) +#define CTIINEN 0x020 +#define CTIOUTEN 0x0A0 #define CTITRIGINSTATUS 0x130 #define CTITRIGOUTSTATUS 0x134 #define CTICHINSTATUS 0x138 @@ -59,6 +60,17 @@ struct fwnode_handle; */ #define CTIINOUTEN_MAX 32 =20 +/* + * Encode CTI register offset and register index in one u32: + * - bits[0:11] : base register offset (0x000 to 0xFFF) + * - bits[24:31] : register index (nr) + */ +#define CTI_REG_NR_MASK GENMASK(31, 24) +#define CTI_REG_GET_NR(reg) FIELD_GET(CTI_REG_NR_MASK, (reg)) +#define CTI_REG_SET_NR_CONST(reg, nr) ((reg) | FIELD_PREP_CONST(CTI_REG_NR= _MASK, (nr))) +#define CTI_REG_SET_NR(reg, nr) ((reg) | FIELD_PREP(CTI_REG_NR_MASK, (nr)= )) +#define CTI_REG_CLR_NR(reg) ((reg) & (~CTI_REG_NR_MASK)) + /** * Group of related trigger signals * --=20 2.43.0 From nobody Fri Jun 19 08:18:11 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA02E3242A4 for ; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b5fab208d4sm294960905ad.55.2026.04.26.02.45.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Apr 2026 02:45:11 -0700 (PDT) From: Yingchao Deng Date: Sun, 26 Apr 2026 17:44:40 +0800 Subject: [PATCH v8 3/4] coresight: cti: add Qualcomm extended CTI identification and quirks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260426-extended-cti-v8-3-23b900a4902f@oss.qualcomm.com> References: <20260426-extended-cti-v8-0-23b900a4902f@oss.qualcomm.com> In-Reply-To: <20260426-extended-cti-v8-0-23b900a4902f@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_yingdeng@quicinc.com, Jinlong Mao , Tingwei Zhang , Jie Gan , Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777196695; l=7257; i=yingchao.deng@oss.qualcomm.com; s=20260426; h=from:subject:message-id; bh=TgA67GI/rOOg6PkPVy5qWtYz3zdEwycYChjFL+t3eBI=; b=e5CMm80B1+blKa2SGPTCtcX7w8sl3HpU3WvXqm0LVOeUfxtld1fsxn7ktNdkUuSFWqUfUTuZe RsKgzTKAlLEB8o4NhVYRRBfM0fp1lSM14Evk66+GYzX8/4E5V7y2fWr X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=aufKZC4I8k2lqi+B/z87rB5kPPybOn8C3mLosbtw+no= X-Proofpoint-GUID: xFcG9zRfk9ZWeyvjLcbhB1U3SJv0BgT6 X-Proofpoint-ORIG-GUID: xFcG9zRfk9ZWeyvjLcbhB1U3SJv0BgT6 X-Authority-Analysis: v=2.4 cv=Y+fIdBeN c=1 sm=1 tr=0 ts=69eddea8 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=yjDJaKUznl4u3GwUnvUA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI2MDEwMiBTYWx0ZWRfXxHl3Y8WgyTEL lhClelD6qZ2pX9lHpYibBCUktckhzXh4vPuDmdCdPuTIzgz63xZ84mz2t8Ru7w0nKzOuPrJdPxL GykfFi9u7ywXbrSF6Rwl8KKvpan4OB5a3OCvz5qBrm0YrMXQzwcgbRsv1MM4ynoDjBXFDS8BytJ DYzvb5yjZg6bwNnk1oFFqFJiVa+KQYOBJNrhVUPq+MU5uuq+BZMiVWM8QsFvSfz528GdkWtDr7Z NiON9zUS83p3C11ZBwYtauOTrm1SJXzyOpBaNLUah2c+bbJMZjOwGRchGK9MMiPimlCX986w6Zz RB4ZEmZuUUahjp5j5f5cKZGDLw/OGtFa9tF/E105guIyMsljnHUdGOIMacUPA0o/mw4fT8lLQF8 FJeMEq5qWp8F+WerGU1XPWmbMUt/VJE5Zem1Mbpolf6I/q0m+r7YyKBz25taYAWQe/BxhtT4OFk 2plJI634fCS4//i1P/Q== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-26_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604260102 Qualcomm implements an extended variant of the ARM CoreSight CTI with a different register layout and vendor-specific behavior. While the programming model remains largely compatible, the register offsets differ from the standard ARM CTI and require explicit handling. Detect Qualcomm CTIs via the DEVARCH register and record this in the CTI driver data. Introduce a small mapping layer to translate standard CTI register offsets to Qualcomm-specific offsets, allowing the rest of the driver to use a common register access path. Additionally, handle a Qualcomm-specific quirk where the CLAIMSET register is incorrectly initialized to a non-zero value, which can cause tools or drivers to assume the component is already claimed. Clear the register during probe to reflect the actual unclaimed state. No functional change is intended for standard ARM CTI devices. Co-developed-by: Jinlong Mao Signed-off-by: Jinlong Mao Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-core.c | 28 +++++++++- drivers/hwtracing/coresight/coresight-cti.h | 4 +- drivers/hwtracing/coresight/qcom-cti.h | 65 ++++++++++++++++++++= ++++ 3 files changed, 95 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index c4cbeb64365b..b1c69a3e9b99 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -21,6 +21,7 @@ =20 #include "coresight-priv.h" #include "coresight-cti.h" +#include "qcom-cti.h" =20 /* * CTI devices can be associated with a PE, or be connected to CoreSight @@ -47,6 +48,10 @@ static void __iomem *cti_reg_addr(struct cti_drvdata *dr= vdata, int reg) u32 offset =3D CTI_REG_CLR_NR(reg); u32 nr =3D CTI_REG_GET_NR(reg); =20 + /* convert to qcom specific offset */ + if (unlikely(drvdata->is_qcom_cti)) + offset =3D cti_qcom_reg_off(offset); + return drvdata->base + offset + sizeof(u32) * nr; } =20 @@ -170,6 +175,9 @@ void cti_write_intack(struct device *dev, u32 ackval) /* DEVID[19:16] - number of CTM channels */ #define CTI_DEVID_CTMCHANNELS(devid_val) ((int) BMVAL(devid_val, 16, 19)) =20 +/* DEVARCH[31:21] - ARCHITECT */ +#define CTI_DEVARCH_ARCHITECT(devarch_val) ((int)BMVAL(devarch_val, 21, 31= )) + static int cti_set_default_config(struct device *dev, struct cti_drvdata *drvdata) { @@ -700,6 +708,7 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) struct coresight_desc cti_desc; struct coresight_platform_data *pdata =3D NULL; struct resource *res =3D &adev->res; + u32 devarch; =20 /* driver data*/ drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); @@ -724,6 +733,22 @@ static int cti_probe(struct amba_device *adev, const s= truct amba_id *id) =20 raw_spin_lock_init(&drvdata->spinlock); =20 + devarch =3D readl_relaxed(drvdata->base + CORESIGHT_DEVARCH); + if (CTI_DEVARCH_ARCHITECT(devarch) =3D=3D ARCHITECT_QCOM) { + drvdata->is_qcom_cti =3D true; + /* + * QCOM CTI does not implement Claimtag functionality as + * per CoreSight specification, but its CLAIMSET register + * is incorrectly initialized to 0xF. This can mislead + * tools or drivers into thinking the component is claimed. + * + * Reset CLAIMSET to 0 to reflect that no claims are active. + */ + CS_UNLOCK(drvdata->base); + writel_relaxed(0, drvdata->base + CORESIGHT_CLAIMSET); + CS_LOCK(drvdata->base); + } + /* initialise CTI driver config values */ ret =3D cti_set_default_config(dev, drvdata); if (ret) @@ -780,7 +805,8 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) =20 /* all done - dec pm refcount */ pm_runtime_put(&adev->dev); - dev_info(&drvdata->csdev->dev, "CTI initialized\n"); + dev_info(&drvdata->csdev->dev, + "%sCTI initialized\n", drvdata->is_qcom_cti ? "QCOM " : ""); return 0; } =20 diff --git a/drivers/hwtracing/coresight/coresight-cti.h b/drivers/hwtracin= g/coresight/coresight-cti.h index dd1ba44518c4..2598601e7b93 100644 --- a/drivers/hwtracing/coresight/coresight-cti.h +++ b/drivers/hwtracing/coresight/coresight-cti.h @@ -55,10 +55,11 @@ struct fwnode_handle; /* * CTI CSSoc 600 has a max of 32 trigger signals per direction. * CTI CSSoc 400 has 8 IO triggers - other CTIs can be impl def. + * QCOM CTI supports up to 128 trigger signals per direction. * Max of in and out defined in the DEVID register. * - pick up actual number used from .dts parameters if present. */ -#define CTIINOUTEN_MAX 32 +#define CTIINOUTEN_MAX 128 =20 /* * Encode CTI register offset and register index in one u32: @@ -188,6 +189,7 @@ struct cti_drvdata { raw_spinlock_t spinlock; struct cti_config config; struct list_head node; + bool is_qcom_cti; }; =20 /* diff --git a/drivers/hwtracing/coresight/qcom-cti.h b/drivers/hwtracing/cor= esight/qcom-cti.h new file mode 100644 index 000000000000..fd1bf07d7cb4 --- /dev/null +++ b/drivers/hwtracing/coresight/qcom-cti.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef _CORESIGHT_QCOM_CTI_H +#define _CORESIGHT_QCOM_CTI_H + +#include "coresight-cti.h" + +#define ARCHITECT_QCOM 0x477 + +/* CTI programming registers */ +#define QCOM_CTIINTACK 0x020 +#define QCOM_CTIAPPSET 0x004 +#define QCOM_CTIAPPCLEAR 0x008 +#define QCOM_CTIAPPPULSE 0x00C +#define QCOM_CTIINEN 0x400 +#define QCOM_CTIOUTEN 0x800 +#define QCOM_CTITRIGINSTATUS 0x040 +#define QCOM_CTITRIGOUTSTATUS 0x060 +#define QCOM_CTICHINSTATUS 0x080 +#define QCOM_CTICHOUTSTATUS 0x084 +#define QCOM_CTIGATE 0x088 +#define QCOM_ASICCTL 0x08C +/* Integration test registers */ +#define QCOM_ITCHINACK 0xE70 +#define QCOM_ITTRIGINACK 0xE80 +#define QCOM_ITCHOUT 0xE74 +#define QCOM_ITTRIGOUT 0xEA0 +#define QCOM_ITCHOUTACK 0xE78 +#define QCOM_ITTRIGOUTACK 0xEC0 +#define QCOM_ITCHIN 0xE7C +#define QCOM_ITTRIGIN 0xEE0 + +static noinline u32 cti_qcom_reg_off(u32 offset) +{ + switch (offset) { + case CTIINTACK: return QCOM_CTIINTACK; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b5fab208d4sm294960905ad.55.2026.04.26.02.45.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Apr 2026 02:45:15 -0700 (PDT) From: Yingchao Deng Date: Sun, 26 Apr 2026 17:44:41 +0800 Subject: [PATCH v8 4/4] coresight: cti: expose banked sysfs registers for Qualcomm extended CTI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260426-extended-cti-v8-4-23b900a4902f@oss.qualcomm.com> References: <20260426-extended-cti-v8-0-23b900a4902f@oss.qualcomm.com> In-Reply-To: <20260426-extended-cti-v8-0-23b900a4902f@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_yingdeng@quicinc.com, Jinlong Mao , Tingwei Zhang , Jie Gan , Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777196695; l=4661; i=yingchao.deng@oss.qualcomm.com; s=20260426; h=from:subject:message-id; bh=OLSSErJr7xMEKOb+hZ/LbjI+CM4RcZpu2NN74Ss6L14=; b=rIBj4R3Di+1yR8dNdgF+nHpt5UGIVdG09pNVsdxHQm/RGUTcM0OuFsgMKvZA1tO2yFe0EVzWQ Jj75zoM14SzAWrvwKEdYSs3i2cWj0S7Yv0miEAYqQKslPdcqt9lS0Sr X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=aufKZC4I8k2lqi+B/z87rB5kPPybOn8C3mLosbtw+no= X-Proofpoint-GUID: sqT2alWo4nllfj_IgazEmKHhnuBAVGP- X-Proofpoint-ORIG-GUID: sqT2alWo4nllfj_IgazEmKHhnuBAVGP- X-Authority-Analysis: v=2.4 cv=Y+fIdBeN c=1 sm=1 tr=0 ts=69eddead cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=2umZ0bgHSShhNh9j1XYA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI2MDEwMiBTYWx0ZWRfXz1lS0qsCVpX6 UgxlQKpX1WFXL0GJQKYkFqQLrmOVPmhyv41HBRCrS5t0yDgHFFf6VQiYS6vE1OLH2aLj8Hn/FAu KXthryWFPDU/oLuyZjM519nFgwlHiKW+exJ6OiedNjRmhXs8sX1E3hZcv1UgAqVLTR5tHbpFx+E 8dMJDmnqpOx/vnuVwoqQLzLkq8z3ymGhh+Cl+vQgz2YRpn6MSKHweEapxAcKPKMCnRk40z5mHss QWQeiZPhN8Ws/tdLAAWZxKLsWfQTU7efLwJZA4TOm9rhiUind0ub6bEdk1Xz7p8qSkgMFP688vv GJph5k8SBk86QTPuVdT/773myYrp6ihAWrTGX4e6qS2DxsAn2tqAUq5onM57PAU0/M9EivSM0sA 5Nr89TsLdJBkuZoh9rKAmBH1VX0CLrxwT+HI1ikPToOVlcPumZT7NrkglbtrNtweiihpx7nwenQ M/O+QjCdw076VADtO/g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-26_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604260102 Qualcomm extended CTI implements banked trigger status and integration registers, where each bank covers 32 triggers. Multiple instances of these registers are required to expose the full trigger space. Add static sysfs entries for the banked CTI registers and control their visibility based on the underlying hardware configuration. Numbered sysfs nodes are hidden on standard ARM CTIs, preserving the existing ABI. On Qualcomm CTIs, only banked registers backed by hardware are exposed, with the number of visible banks derived from nr_trig_max. This ensures that userspace only sees registers that are actually implemented, while maintaining compatibility with existing CTI tooling. Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 58 +++++++++++++++++++= ++++ 1 file changed, 58 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hw= tracing/coresight/coresight-cti-sysfs.c index 8b70e7e38ea3..046757e4e9b6 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -512,18 +512,36 @@ static struct attribute *coresight_cti_regs_attrs[] = =3D { &dev_attr_appclear.attr, &dev_attr_apppulse.attr, coresight_cti_reg(triginstatus, CTITRIGINSTATUS), + coresight_cti_reg(triginstatus1, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 1)= ), + coresight_cti_reg(triginstatus2, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 2)= ), + coresight_cti_reg(triginstatus3, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 3)= ), coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS), + coresight_cti_reg(trigoutstatus1, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, = 1)), + coresight_cti_reg(trigoutstatus2, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, = 2)), + coresight_cti_reg(trigoutstatus3, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, = 3)), coresight_cti_reg(chinstatus, CTICHINSTATUS), coresight_cti_reg(choutstatus, CTICHOUTSTATUS), #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL), coresight_cti_reg(ittrigin, ITTRIGIN), + coresight_cti_reg(ittrigin1, CTI_REG_SET_NR_CONST(ITTRIGIN, 1)), + coresight_cti_reg(ittrigin2, CTI_REG_SET_NR_CONST(ITTRIGIN, 2)), + coresight_cti_reg(ittrigin3, CTI_REG_SET_NR_CONST(ITTRIGIN, 3)), coresight_cti_reg(itchin, ITCHIN), coresight_cti_reg_rw(ittrigout, ITTRIGOUT), + coresight_cti_reg_rw(ittrigout1, CTI_REG_SET_NR_CONST(ITTRIGOUT, 1)), + coresight_cti_reg_rw(ittrigout2, CTI_REG_SET_NR_CONST(ITTRIGOUT, 2)), + coresight_cti_reg_rw(ittrigout3, CTI_REG_SET_NR_CONST(ITTRIGOUT, 3)), coresight_cti_reg_rw(itchout, ITCHOUT), coresight_cti_reg(itchoutack, ITCHOUTACK), coresight_cti_reg(ittrigoutack, ITTRIGOUTACK), + coresight_cti_reg(ittrigoutack1, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 1)), + coresight_cti_reg(ittrigoutack2, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 2)), + coresight_cti_reg(ittrigoutack3, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 3)), coresight_cti_reg_wo(ittriginack, ITTRIGINACK), + coresight_cti_reg_wo(ittriginack1, CTI_REG_SET_NR_CONST(ITTRIGINACK, 1)), + coresight_cti_reg_wo(ittriginack2, CTI_REG_SET_NR_CONST(ITTRIGINACK, 2)), + coresight_cti_reg_wo(ittriginack3, CTI_REG_SET_NR_CONST(ITTRIGINACK, 3)), coresight_cti_reg_wo(itchinack, ITCHINACK), #endif NULL, @@ -534,10 +552,50 @@ static umode_t coresight_cti_regs_is_visible(struct k= object *kobj, { struct device *dev =3D kobj_to_dev(kobj); struct cti_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + static const char * const qcom_suffix_registers[] =3D { + "triginstatus", + "trigoutstatus", +#ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS + "ittrigin", + "ittrigout", + "ittriginack", + "ittrigoutack", +#endif + }; + int i, nr, max_bank; + size_t len; =20 if (attr =3D=3D &dev_attr_asicctl.attr && !drvdata->config.asicctl_impl) return 0; =20 + /* + * Banked regs are exposed as (nr =3D 1..3). + * - Hide them on standard CTIs. + * - On QCOM CTIs, hide suffixes beyond the number of banks implied + * by nr_trig_max (32 triggers per bank). + */ + for (i =3D 0; i < ARRAY_SIZE(qcom_suffix_registers); i++) { + len =3D strlen(qcom_suffix_registers[i]); + + if (strncmp(attr->name, qcom_suffix_registers[i], len)) + continue; + + if (kstrtoint(attr->name + len, 10, &nr)) + continue; + + if (!drvdata->is_qcom_cti) + return 0; + + if (nr < 1 || nr > 3) + return 0; + + max_bank =3D DIV_ROUND_UP(drvdata->config.nr_trig_max, 32) - 1; + if (nr > max_bank) + return 0; + + break; + } + return attr->mode; } =20 --=20 2.43.0