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charset="utf-8" Add the compatible string for the Agilex 5 PCIe Hard IP root port controller. Co-developed-by: Matthew Gerlach Signed-off-by: Matthew Gerlach Co-developed-by: Peter Colberg Signed-off-by: Peter Colberg Signed-off-by: Mahesh Vaidya --- .../bindings/pci/altr,pcie-root-port.yaml | 37 ++++++++++--------- 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml= b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml index f516db47ab20..f9c2089bad34 100644 --- a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml @@ -8,16 +8,17 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Altera PCIe Root Port =20 maintainers: - - Matthew Gerlach + - Mahesh Vaidya =20 properties: compatible: description: Each family of socfpga has its own implementation of the PCI controller. The altr,pcie-root-port-1.0 is used for the Cyclone5 family of chips. The Stratix10 family of chips is supported by the - altr,pcie-root-port-2.0. The Agilex family of chips has three, + altr,pcie-root-port-2.0. The Agilex7 family of chips has three, non-register compatible, variants of PCIe Hard IP referred to as the F-Tile, P-Tile, and R-Tile, depending on the specific chip instance. + The altr,pcie-root-port-4.0 is used for the Agilex5 family of chips. =20 enum: - altr,pcie-root-port-1.0 @@ -25,20 +26,15 @@ properties: - altr,pcie-root-port-3.0-f-tile - altr,pcie-root-port-3.0-p-tile - altr,pcie-root-port-3.0-r-tile + - altr,pcie-root-port-4.0 =20 reg: - items: - - description: TX slave port region - - description: Control register access region - - description: Hard IP region minItems: 2 + maxItems: 3 =20 reg-names: - items: - - const: Txs - - const: Cra - - const: Hip minItems: 2 + maxItems: 3 =20 interrupts: maxItems: 1 @@ -80,18 +76,25 @@ allOf: then: properties: reg: - maxItems: 2 - + items: + - description: TX slave port region + - description: Control register access region reg-names: - maxItems: 2 - + items: + - const: Txs + - const: Cra else: properties: reg: - minItems: 3 - + items: + - description: TX slave port region + - description: Control register access region + - description: Hard IP region reg-names: - minItems: 3 + items: + - const: Txs + - const: Cra + - const: Hip =20 unevaluatedProperties: false =20 --=20 2.34.1 From nobody Fri Jun 19 16:05:42 2026 Received: from DM1PR04CU001.outbound.protection.outlook.com (mail-centralusazon11010034.outbound.protection.outlook.com [52.101.61.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EC663090C6; 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Received: from SA1PR03MB6498.namprd03.prod.outlook.com (2603:10b6:806:1c5::7) by DM4PR03MB5982.namprd03.prod.outlook.com (2603:10b6:5:389::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.21; Fri, 24 Apr 2026 09:49:42 +0000 Received: from SA1PR03MB6498.namprd03.prod.outlook.com ([fe80::feea:da58:faeb:9ebc]) by SA1PR03MB6498.namprd03.prod.outlook.com ([fe80::feea:da58:faeb:9ebc%4]) with mapi id 15.20.9846.021; Fri, 24 Apr 2026 09:49:42 +0000 From: Mahesh Vaidya To: joyce.ooi@intel.com, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, subhransu.sekhar.prusty@altera.com, dinguyen@kernel.org, Mahesh Vaidya Subject: [PATCH 2/3] PCI: altera: fix resource leaks on probe failure Date: Fri, 24 Apr 2026 02:49:12 -0700 Message-Id: <20260424094913.522123-3-mahesh.vaidya@altera.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260424094913.522123-1-mahesh.vaidya@altera.com> References: <20260424094913.522123-1-mahesh.vaidya@altera.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SI2PR02CA0014.apcprd02.prod.outlook.com (2603:1096:4:194::19) To SA1PR03MB6498.namprd03.prod.outlook.com (2603:10b6:806:1c5::7) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA1PR03MB6498:EE_|DM4PR03MB5982:EE_ X-MS-Office365-Filtering-Correlation-Id: 7695c205-8be5-463a-6110-08dea1e6cf12 X-MS-Exchange-AtpMessageProperties: SA X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|366016|1800799024|55112099003|56012099003|18002099003|22082099003; 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charset="utf-8" The chained IRQ handler is installed in altera_pcie_parse_dt() but never unregistered on probe failure. If any subsequent step in altera_pcie_probe() fails, devm frees the pcie struct while the handler still references it. A subsequent interrupt would trigger a use-after-free. The INTx IRQ domain created in altera_pcie_init_irq_domain() is similarly leaked on probe failure, since the existing cleanup via altera_pcie_irq_teardown() is only invoked from the remove path. Move the handler installation from altera_pcie_parse_dt() into altera_pcie_probe() after the IRQ domain is created, and add a goto-based error path so altera_pcie_irq_teardown() is called on any failure after handler installation. Fixes: 60f2ee5f1472 ("PCI: altera: Add Agilex support") Signed-off-by: Mahesh Vaidya --- drivers/pci/controller/pcie-altera.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/= pcie-altera.c index 3dbb7adc421c..025ba74d1ee2 100644 --- a/drivers/pci/controller/pcie-altera.c +++ b/drivers/pci/controller/pcie-altera.c @@ -891,7 +891,6 @@ static int altera_pcie_parse_dt(struct altera_pcie *pci= e) if (pcie->irq < 0) return pcie->irq; =20 - irq_set_chained_handler_and_data(pcie->irq, pcie->pcie_data->ops->rp_isr,= pcie); return 0; } =20 @@ -1020,6 +1019,11 @@ static int altera_pcie_probe(struct platform_device = *pdev) return ret; } =20 + /* Install chained handler after domain is ready */ + irq_set_chained_handler_and_data(pcie->irq, + pcie->pcie_data->ops->rp_isr, + pcie); + if (pcie->pcie_data->version =3D=3D ALTERA_PCIE_V1 || pcie->pcie_data->version =3D=3D ALTERA_PCIE_V2) { /* clear all interrupts */ @@ -1037,7 +1041,16 @@ static int altera_pcie_probe(struct platform_device = *pdev) bridge->busnr =3D pcie->root_bus_nr; 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charset="utf-8" Add PCIe root port controller support for the Agilex 5 (V4) family of SoC FPGAs. The Agilex 5 PCIe Hard IP reuses the same config-space access path as Agilex 7 (V3). Root port and endpoint configuration reads/writes use direct MMIO to the HIP and CRA regions. The difference is in the HIP port-level registers (IRQ status and IRQ enable). On V3 these are directly mapped through the HIP MMIO window. On V4 these registers are only reachable through an indirect access mailbox (CFG REG IA CTRL) in the PCIe Subsystem AXI-Lite interface, documented in the GTS AXI Streaming IP for PCIe User Guide. This adds: - ALTERA_PCIE_V4 version and platform data - Indirect register read/write helpers using readl_poll_timeout_atomic - Chained IRQ handler (aglx5_isr) for the V4 interrupt path - OF match for "altr,pcie-root-port-4.0" Co-developed-by: Matthew Gerlach Signed-off-by: Matthew Gerlach Co-developed-by: Peter Colberg Signed-off-by: Peter Colberg Signed-off-by: Mahesh Vaidya --- drivers/pci/controller/pcie-altera.c | 156 ++++++++++++++++++++++++++- 1 file changed, 155 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/= pcie-altera.c index 025ba74d1ee2..db8149d84c96 100644 --- a/drivers/pci/controller/pcie-altera.c +++ b/drivers/pci/controller/pcie-altera.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include #include #include #include @@ -93,16 +95,36 @@ #define AGLX_CFG_TARGET_LOCAL_2000 2 #define AGLX_CFG_TARGET_LOCAL_3000 3 =20 +/* PCIe subsystem indirect register access */ +#define PCIE_SS_IA_CTL 0xc8 /* control register */ +#define PCIE_SS_IA_FN_NUM 0xcc /* function number */ +#define PCIE_SS_IA_FN_WRDATA 0xd0 /* write data */ +#define PCIE_SS_IA_FN_RDDATA 0xd4 /* read data */ + +/* PCIE_SS_IA_CTL bitfields */ +#define PCIE_SS_IA_CTL_INITIATE BIT(0) +#define PCIE_SS_IA_CTL_WRITE BIT(1) +#define PCIE_SS_IA_CTL_BYTE_EN GENMASK(5, 2) +#define PCIE_SS_IA_CTL_ADDR GENMASK(31, 6) + +/* PCIE_SS_IA_FN_NUM function types */ +#define PCIE_SS_IA_FN_TYPE_HIP 2 + +#define AGLX5_INDIRECT_SLEEP_US 1 +#define AGLX5_INDIRECT_TIMEOUT_US 1000 + enum altera_pcie_version { ALTERA_PCIE_V1 =3D 0, ALTERA_PCIE_V2, ALTERA_PCIE_V3, + ALTERA_PCIE_V4, }; =20 struct altera_pcie { struct platform_device *pdev; void __iomem *cra_base; void __iomem *hip_base; + void __iomem *controller_base; int irq; u8 root_bus_nr; struct irq_domain *irq_domain; @@ -849,6 +871,98 @@ static void aglx_isr(struct irq_desc *desc) chained_irq_exit(chip, desc); } =20 +/* + * Indirect register access to HIP registers via the PCIe Subsystem + * AXI-Lite mailbox, documented in the GTS AXI Streaming IP for PCIe + * User Guide. Called from chained IRQ handler (hardirq) and probe + * (before handler is installed), so no locking is required. + */ +static int aglx5_indirect_readl(const struct altera_pcie *pcie, + unsigned int addr, unsigned int *val) +{ + unsigned int ctl; + int ret; + + writel(PCIE_SS_IA_FN_TYPE_HIP, + pcie->controller_base + PCIE_SS_IA_FN_NUM); + + ctl =3D FIELD_PREP(PCIE_SS_IA_CTL_ADDR, addr >> 2) | + PCIE_SS_IA_CTL_BYTE_EN | PCIE_SS_IA_CTL_INITIATE; + writel(ctl, (pcie->controller_base + PCIE_SS_IA_CTL)); + + ret =3D readl_poll_timeout_atomic(pcie->controller_base + PCIE_SS_IA_CTL, + ctl, !(ctl & PCIE_SS_IA_CTL_INITIATE), + AGLX5_INDIRECT_SLEEP_US, + AGLX5_INDIRECT_TIMEOUT_US); + if (ret) + return ret; + + *val =3D readl(pcie->controller_base + PCIE_SS_IA_FN_RDDATA); + + return 0; +} + +static int aglx5_indirect_writel(const struct altera_pcie *pcie, + unsigned int addr, unsigned int val) +{ + unsigned int ctl; + int ret; + + writel(PCIE_SS_IA_FN_TYPE_HIP, + pcie->controller_base + PCIE_SS_IA_FN_NUM); + writel(val, pcie->controller_base + PCIE_SS_IA_FN_WRDATA); + + ctl =3D FIELD_PREP(PCIE_SS_IA_CTL_ADDR, addr >> 2) | + PCIE_SS_IA_CTL_BYTE_EN | PCIE_SS_IA_CTL_WRITE | + PCIE_SS_IA_CTL_INITIATE; + writel(ctl, pcie->controller_base + PCIE_SS_IA_CTL); + + ret =3D readl_poll_timeout_atomic(pcie->controller_base + PCIE_SS_IA_CTL, + ctl, !(ctl & PCIE_SS_IA_CTL_INITIATE), + AGLX5_INDIRECT_SLEEP_US, + AGLX5_INDIRECT_TIMEOUT_US); + + return ret; +} + +static void aglx5_isr(struct irq_desc *desc) +{ + struct irq_chip *chip =3D irq_desc_get_chip(desc); + struct altera_pcie *pcie; + struct device *dev; + u32 status =3D 0; + int ret; + + chained_irq_enter(chip, desc); + pcie =3D irq_desc_get_handler_data(desc); + dev =3D &pcie->pdev->dev; + + ret =3D aglx5_indirect_readl(pcie, pcie->pcie_data->port_irq_status_offse= t, &status); + if (ret) { + dev_err(dev, "timeout reading IRQ status, masking IRQ\n"); + disable_irq_nosync(pcie->irq); + goto out; + } + + if (status & CFG_AER) { + ret =3D generic_handle_domain_irq(pcie->irq_domain, 0); + if (ret) + dev_err_ratelimited(dev, "unexpected IRQ\n"); + + /* W1C: clear the handled bit */ + ret =3D aglx5_indirect_writel(pcie, + pcie->pcie_data->port_irq_status_offset, + CFG_AER); + if (ret) { + dev_err(dev, "timeout clearing IRQ status, masking IRQ\n"); + disable_irq_nosync(pcie->irq); + } + } + +out: + chained_irq_exit(chip, desc); +} + static int altera_pcie_init_irq_domain(struct altera_pcie *pcie) { struct device *dev =3D &pcie->pdev->dev; @@ -880,12 +994,19 @@ static int altera_pcie_parse_dt(struct altera_pcie *p= cie) return PTR_ERR(pcie->cra_base); =20 if (pcie->pcie_data->version =3D=3D ALTERA_PCIE_V2 || - pcie->pcie_data->version =3D=3D ALTERA_PCIE_V3) { + pcie->pcie_data->version =3D=3D ALTERA_PCIE_V3 || + pcie->pcie_data->version =3D=3D ALTERA_PCIE_V4) { pcie->hip_base =3D devm_platform_ioremap_resource_byname(pdev, "Hip"); if (IS_ERR(pcie->hip_base)) return PTR_ERR(pcie->hip_base); } =20 + if (pcie->pcie_data->version =3D=3D ALTERA_PCIE_V4) { + pcie->controller_base =3D devm_platform_ioremap_resource_byname(pdev, "T= xs"); + if (IS_ERR(pcie->controller_base)) + return PTR_ERR(pcie->controller_base); + } + /* setup IRQ */ pcie->irq =3D platform_get_irq(pdev, 0); if (pcie->irq < 0) @@ -924,6 +1045,15 @@ static const struct altera_pcie_ops altera_pcie_ops_3= _0 =3D { .rp_isr =3D aglx_isr, }; =20 +static const struct altera_pcie_ops altera_pcie_ops_4_0 =3D { + .rp_read_cfg =3D aglx_rp_read_cfg, + .rp_write_cfg =3D aglx_rp_write_cfg, + .get_link_status =3D aglx_altera_pcie_link_up, + .ep_read_cfg =3D aglx_ep_read_cfg, + .ep_write_cfg =3D aglx_ep_write_cfg, + .rp_isr =3D aglx5_isr, +}; + static const struct altera_pcie_data altera_pcie_1_0_data =3D { .ops =3D &altera_pcie_ops_1_0, .cap_offset =3D 0x80, @@ -971,6 +1101,20 @@ static const struct altera_pcie_data altera_pcie_3_0_= r_tile_data =3D { .port_irq_enable_offset =3D 0x4, }; =20 +static const struct altera_pcie_data altera_pcie_4_0_data =3D { + .ops =3D &altera_pcie_ops_4_0, + .version =3D ALTERA_PCIE_V4, + .cap_offset =3D 0x70, + .port_conf_offset =3D 0x14000, + /* + * Unlike V3 where IRQ offsets are relative to port_conf_offset, + * V4 IRQ offsets are absolute addresses in the HIP indirect access + * space documented in the GTS AXI Streaming IP for PCIe User Guide. + */ + .port_irq_status_offset =3D 0x1414c, + .port_irq_enable_offset =3D 0x14150, +}; + static const struct of_device_id altera_pcie_of_match[] =3D { {.compatible =3D "altr,pcie-root-port-1.0", .data =3D &altera_pcie_1_0_data }, @@ -982,6 +1126,8 @@ static const struct of_device_id altera_pcie_of_match[= ] =3D { .data =3D &altera_pcie_3_0_p_tile_data }, {.compatible =3D "altr,pcie-root-port-3.0-r-tile", .data =3D &altera_pcie_3_0_r_tile_data }, + {.compatible =3D "altr,pcie-root-port-4.0", + .data =3D &altera_pcie_4_0_data }, {}, }; =20 @@ -1035,6 +1181,14 @@ static int altera_pcie_probe(struct platform_device = *pdev) writel(CFG_AER, pcie->hip_base + pcie->pcie_data->port_conf_offset + pcie->pcie_data->port_irq_enable_offset); + } else if (pcie->pcie_data->version =3D=3D ALTERA_PCIE_V4) { + ret =3D aglx5_indirect_writel(pcie, + pcie->pcie_data->port_irq_enable_offset, + CFG_AER); + if (ret) { + dev_err(dev, "Failed to enable AER IRQ\n"); + goto err_teardown_irq; + } } =20 bridge->sysdata =3D pcie; --=20 2.34.1