From nobody Mon Jun 15 15:13:00 2026 Received: from MA0PR01CU012.outbound.protection.outlook.com (mail-southindiaazon11021095.outbound.protection.outlook.com [40.107.57.95]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BABE41A267; Fri, 24 Apr 2026 09:26:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.57.95 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777022797; cv=fail; b=klbZpzC4xhbZ8ywLZZrbgRRfrWTGoNE+9FujvuITfUIWKaggHtKBQ3201qjouIoe9ZeRbpWX+WNd+rIFprYB3k1qk01E9ce9H1/pOQxUMY0LzxBSdDPqTXYxsUuy0/MnlZB53LDVAVOjmnz/xRtH9VdGI1WThpAVMDDety0urCs= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777022797; c=relaxed/simple; bh=xUhgcL9GQeAsyXfJdkttEugkSdwJJiEGBTECb8Y+ifI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=jSc4Msdgp8tcRKP+Uif6RIlqdBfkqk59oW4+Si1uywbVnRsa5wbPRig3I6amUqfxO0A8WW1Tgao5fOaqpWRsKtWKfA38Suhcgg9c9TwzcznOf3OjOXCmOoY6wttQdW8ibpgevEuk81oh+HPg5mwhJBLX6yj7wAJHkCYrQqRqD9k= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=siliconsignals.io; spf=pass smtp.mailfrom=siliconsignals.io; dkim=pass (2048-bit key) header.d=siliconsignals.io header.i=@siliconsignals.io header.b=GLSMrP1U; arc=fail smtp.client-ip=40.107.57.95 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=siliconsignals.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=siliconsignals.io Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siliconsignals.io header.i=@siliconsignals.io header.b="GLSMrP1U" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=owE9i+Ge3ZZl88S+rzff8sXP0DR/liLBxdnMWzII7sHTZftG96C/fJ2MYytOPAJ3z5P100Lw8tHZ1qkRYRc1yInwdUjF6cEW1cJWUPXkf1mC94R2OkfHp02pG8KcErPXXG23/vxFFeNFboMC9ERm7ThePycwWN7CFyTaYySw8gyKY+jm0Mdxw0pkRHBgRaQ2HQvRwProbPcvT+bjkuDZpnqZ/zmx094LXCKPi4sQMf9NWp37OzR2vRXH/oHr447zSbzojTavxAQ2BFwQINzEvAgcaX+eKk5o/mjl4WXrOkDmGD1Pnfo91frZ8rjcxr1Cj2W1rslr1TgfM4qMQWsXyQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3Jbstpi9fnWAVVcQZbYWxb3oxpjJbkCTp8h7+rvdlPQ=; b=J5dx7zUxCYwurt38hMR+2eX3jccsMZCmaQRlo0D1Hd8lDyZ2Q9NK+DX9vA/TRqt2T/dJclpF9Bz5rGItvxPmYvk2j7VUmUF8L1SMVycanDrX7+Dvdo0v02kwVyFHowArXfuwqbFdg4xP3XbP+GClJgVY+Zmk20WkFCvznCh/4AaThn2BECvFw/FosQzY353z2aTt5AsGgIskjSnJ+gcdo9SshGC59FjIEYDb98Sw1Now6o/VY1miQ8SFv73MU0TcT525DZjnnIsUN9im8dhFxmI3KrS8wolLZPSGuK5GECcnhUtdSjGWjx/eFnMAlhUBEn+rjIoll91nhY6vgZE+7w== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=siliconsignals.io; dmarc=pass action=none header.from=siliconsignals.io; dkim=pass header.d=siliconsignals.io; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=siliconsignals.io; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3Jbstpi9fnWAVVcQZbYWxb3oxpjJbkCTp8h7+rvdlPQ=; b=GLSMrP1Ug4pogUCv7CLzWN1gliaXoEO6HJSeSYIf2SWVnhCSQ9mfEpdZ+2N3TkW0kTIEDmWmMBANXVkDBpaHOZOsl3GuMLehlePJQLFdZ0TDUbMfosZYUPUNWBOgd6pwjWpmgrc7ot1Pk5RzlyveJRuWElfg4GWzGwEDWS3YVzF67jwSpvVcXB14qoNPKyM7vsOYUkZjWnXTh66fWiiH8g7EWt1YAPpSLfdjxojnMPmuqbGOfqcNCvcjd9VkGECxOem0xREJdl96dv8AoNK2Vsc5XnaIDmYmBzUrsSNLqxUWc1QSF4XJJa8edbwNq48M6HkQ8/0CLP7Kdy5oKyXMvg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=siliconsignals.io; Received: from MA0P287MB2178.INDP287.PROD.OUTLOOK.COM (2603:1096:a01:11e::14) by MA5P287MB5221.INDP287.PROD.OUTLOOK.COM (2603:1096:a01:1c5::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.22; Fri, 24 Apr 2026 09:26:31 +0000 Received: from MA0P287MB2178.INDP287.PROD.OUTLOOK.COM ([fe80::f8da:c075:cde1:e167]) by MA0P287MB2178.INDP287.PROD.OUTLOOK.COM ([fe80::f8da:c075:cde1:e167%3]) with mapi id 15.20.9846.021; Fri, 24 Apr 2026 09:26:31 +0000 From: Elgin Perumbilly To: sakari.ailus@linux.intel.com, laurent.pinchart@ideasonboard.com Cc: Elgin Perumbilly , Tarang Raval , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hans Verkuil , Hans de Goede , Vladimir Zapolskiy , Mehdi Djait , Sylvain Petinot , Benjamin Mugnier , Svyatoslav Ryhel , Hardevsinh Palaniya , Himanshu Bhavani , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/3] dt-bindings: media: i2c: Add os02g10 sensor Date: Fri, 24 Apr 2026 14:55:45 +0530 Message-Id: <20260424092554.26130-2-elgin.perumbilly@siliconsignals.io> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260424092554.26130-1-elgin.perumbilly@siliconsignals.io> References: <20260424092554.26130-1-elgin.perumbilly@siliconsignals.io> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BM1PR01CA0154.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:68::24) To MA0P287MB2178.INDP287.PROD.OUTLOOK.COM (2603:1096:a01:11e::14) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MA0P287MB2178:EE_|MA5P287MB5221:EE_ X-MS-Office365-Filtering-Correlation-Id: f7b04f90-da14-4cf5-2eaa-08dea1e39213 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|7416014|52116014|22082099003|18002099003|38350700014|56012099003; X-Microsoft-Antispam-Message-Info: oCUA5CM1KnDi34fDAJspA6hT5/61+kcoV2W2EwoPsb30TQcBZKszEAmxXtTK9pgj/E9H8V2WlmTND3IztcHc3gSpWLxjlH28IWwmrjrKUM3cJXU6bJxOTGg5mEJHIM4eFT+fO83p+EQ1RHrwrpAFYiAR3483IHsbY/KjoLD+FYeKHT2S0lYB6KkT/6g8htIS58XtFiV/caY34j22gxQrQgv9I9u0k1I2ZrcyFv1UhaWMrG8ddUUkxw/0SRvT9pmMz66Bii7H1cEtpC9eVUjGhcBd5q028rpNUYBBFvZn5NhQvycGnT7utx/UTsVK5Gc1eW0bP2KeKrVDDEA4xJ5ypfUK0vPSYfjaH19rZyX7+7LMout+Wb0NubdsQlaSUZYw8wyU1bN6oCFieWWg2HHiNuljeXAJMHXYPzb6+YizSWSv+1+ub21+0Dj7u1swBDTXfIUAc/oYGXby9B9zL59ka0wyO6PcajUxzyK8JPVC/24D4IpKqXbEDTacwyfmKutNQk0ftNdokdsMz/NbcI8v2NRAU2lvoBi8fe+RW/60e3tf3Kfy1dx9rvl1QWxhxJFw7swCZLH+2Xds3604+1wBaCrw6rYfAYVaptN+gkpZhtTwhaE7skL4J0gVk85fR9WUj7seaIDA4N1/VJbimScCB6UsF2k2lz3rcQlLsYmXTa8rqpqbhbw/OdzsR6xX1Z9VcLGbq8no7qPZYUT52+PAlGGwLqZiFp4fUJVIoSxoXOA= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MA0P287MB2178.INDP287.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(13230040)(366016)(1800799024)(376014)(7416014)(52116014)(22082099003)(18002099003)(38350700014)(56012099003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?o67gMnDj2brVg68xzDaCjL2JtTsWUIE4m6etEHd7zpyhhbAXi8BhGCdT+faf?= =?us-ascii?Q?1g/kO//BhNHSP1Ov7OeKKr7v0yS3W10uCGiAOB8Txss3ko/nAJJlp+p8RVWi?= =?us-ascii?Q?idib7skP8dtvWCR/q/7vszHWtQzbEG4K474pq51GpuiXInrVtfUL8upyyjkY?= =?us-ascii?Q?7B9OEUVrM8Y3kYpVMt2GqQK1tX/ZLlX4G7xxSMqLs55+icTkAs6VhqkSc7ud?= =?us-ascii?Q?xVZ7JyL8ybi1c4TcKum46Kyi9PYCTQGv+j/6guIQ11ai+3AEAePl92pTsYYl?= =?us-ascii?Q?e4jlbnWiZglQFJFhAaEWgijPHFEwAjobuT0bAteXXzpU/sbpn/okByq1VrYJ?= =?us-ascii?Q?PZLOGbkjw4glf45seS7jZJHrJwnGHQqS0i4Bdb94YRL6tUlEUA0H3/BPx3bl?= =?us-ascii?Q?TITZXPFmzDRE7r68Qu2L4gYIpneqoAGFU+BLlmoJWIdUKMdFYnRfg5WJQKgu?= =?us-ascii?Q?abV+dlOeoDTMXGUX18II98yzRHf50QSFGjNUEE96GJXXBDwrOaJLTrYL/tXd?= =?us-ascii?Q?7YwpJlX565O0z4kk6yKkoSQdx6aSQ7GKLhSZvS+5OXar7OUsnKD+eYPI1402?= =?us-ascii?Q?Cf0ZXNX1TLkusfezwBSszBrs8iu9rR7E5WDY2XF5QITOXFnFJpIHD1ZNwmFD?= =?us-ascii?Q?oUYb9YkB9IhkjmQm1sif/J6M0t/y2g0bpwlpxq2vWqcM7c6KKd1XBt1eISEK?= =?us-ascii?Q?5w4G9mqAIwY/mef3CJAuQd7gPrYKUSGBxPXC2DR0TmD70htaKq7YywrxOpHT?= =?us-ascii?Q?xTTpeH5+DR5Swys4+uzTkw4THhGB6aHeoZ0QeeTEsNGMXbZvOeP4tQ17+mTu?= =?us-ascii?Q?pli9f7SgsnCPabrsjl7BaXj1rOt4c7sEsGoT07Uo6MI4jlfv2Hiapof8lhyb?= =?us-ascii?Q?Ou0mtQZ2cLp1nz4MOAH7eZDr7zRFjdfmRs7guzGonrsn6ivrI4WBqeuePmNr?= =?us-ascii?Q?MxmT6hSWPexYOBGNTCUSUNmLfFsf+AuuHcE6AYcStZm05bB4DKZkNxOKJw0I?= =?us-ascii?Q?nuTY/3P2vBo5v9bt81wnwRXYJmXxFNh9xFSZpcqiTuSr3QT/BH7iHtJu/HSo?= =?us-ascii?Q?qaylBQALiixnExoWBUpo/sN3s851fSZ+Efd2oo/BRZ40PV6hZaFhcB5KMNTQ?= =?us-ascii?Q?UkabIWDH5APddOVJuCwVkCukHGjV30rNyldkfnJwhQR9q97W25eBzo1+Qcnx?= =?us-ascii?Q?f254XNerp8eLBhy24cJYHBwnXu1dP8aY1TYLv5Gb91jJoTb5nGHo/7AWG/GV?= =?us-ascii?Q?y4At4pw9e4aWblBp87IzzwgfAMX4B3SgTd8OPuBnPuI6WLw9q56S337jjbF4?= =?us-ascii?Q?zPo16hwwlpAhTlIMVzVJr7apATcBzoqGMWbOVZ59W3NDd2txiInBvKWx+a4r?= =?us-ascii?Q?cph/wSPu0OGLP2Wvx/fdlpUQFoCSxAW7YNIkvArBuZGeSQo0SzJapmCJmljG?= =?us-ascii?Q?ewc7kj10tolAoZYQpRgOWtAypuxt1Uk9JmM5TFt/jgd5cX23MctLMl1YjUjL?= =?us-ascii?Q?9waby4g0OtbSoQ1LfoK4ktOvKNxUprP45G63xfLNLCBiMvYRjFmk5ymNnXjm?= =?us-ascii?Q?seDCqUcZpENKBiQP/kUDUY46RAsE2WklNkB30K6VmaeyP4IdiOX4eRq5s8PW?= =?us-ascii?Q?4pSmh+SUYTzEp6jps+s2DpSvHfJVJVvUUjQq3HyiPRH1OT+nNQefYKkBYzpe?= =?us-ascii?Q?1Ake6aw72NLeS45/Q96ByIQ1G58wutxJWyyQiXu8Dn2XOR4EOMPn+CkaR3QJ?= =?us-ascii?Q?5v/siwyYHBtQe4vzsx8JxLW+OkbYjrx1/C8kNu2eSBUqm4zX70nL?= X-OriginatorOrg: siliconsignals.io X-MS-Exchange-CrossTenant-Network-Message-Id: f7b04f90-da14-4cf5-2eaa-08dea1e39213 X-MS-Exchange-CrossTenant-AuthSource: MA0P287MB2178.INDP287.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2026 09:26:31.4568 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 7ec5089e-a433-4bd1-a638-82ee62e21d37 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9vTCJxO502CQEUcGOJwbJgWLNKU5exE9VssBrKl6OC8igdrk5zUKLOrvWQalihnNnbDpJxXbS9BcZ6k+WOaLxdEjh7jVg+V4+TryIJGbi5EaN8HJAaYDr+sngrxs8nli X-MS-Exchange-Transport-CrossTenantHeadersStamped: MA5P287MB5221 Content-Type: text/plain; charset="utf-8" Add bindings for Omnivision OS02G10 sensor. Signed-off-by: Elgin Perumbilly Reviewed-by: Krzysztof Kozlowski Reviewed-by: Vladimir Zapolskiy --- .../bindings/media/i2c/ovti,os02g10.yaml | 91 +++++++++++++++++++ MAINTAINERS | 7 ++ 2 files changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/ovti,os02g1= 0.yaml diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,os02g10.yaml = b/Documentation/devicetree/bindings/media/i2c/ovti,os02g10.yaml new file mode 100644 index 000000000000..252059459390 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ovti,os02g10.yaml @@ -0,0 +1,91 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,os02g10.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OS02G10 Image Sensor + +maintainers: + - Tarang Raval + +description: + The OmniVision OS02G10 is a 2MP (1920x1080) color CMOS image sensor cont= rolled + through an I2C-compatible SCCB bus. It outputs RAW10 format data and sup= ports + a 2-lane MIPI interface. + +properties: + compatible: + const: ovti,os02g10 + + reg: + maxItems: 1 + + clocks: + items: + - description: XCLK clock + + avdd-supply: + description: Analog Domain Power Supply (2.8v) + + dovdd-supply: + description: I/O Domain Power Supply (1.8v) + + dvdd-supply: + description: Digital core Power Supply (1.5v) + + reset-gpios: + maxItems: 1 + description: Reset Pin GPIO Control (active low) + + port: + description: MIPI CSI-2 transmitter port + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + required: + - link-frequencies + +required: + - compatible + - reg + - clocks + - avdd-supply + - dovdd-supply + - dvdd-supply + - port + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + camera-sensor@3c { + compatible =3D "ovti,os02g10"; + reg =3D <0x3c>; + clocks =3D <&os02g10_clk>; + reset-gpios =3D <&gpio1 7 GPIO_ACTIVE_LOW>; + + avdd-supply =3D <&os02g10_avdd_2v8>; + dvdd-supply =3D <&os02g10_dvdd_1v2>; + dovdd-supply =3D <&os2gb10_dovdd_1v8>; + + port { + cam_out: endpoint { + remote-endpoint =3D <&mipi_in_cam>; + data-lanes =3D <1 2>; + link-frequencies =3D /bits/ 64 <720000000>; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 900fc00b73e6..8a0a55073c30 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19443,6 +19443,13 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml F: drivers/media/i2c/og0ve1b.c +OMNIVISION OS02G10 SENSOR DRIVER +M: Tarang Raval +M: Elgin Perumbilly +L: linux-media@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/media/i2c/ovti,os02g10.yaml + OMNIVISION OS05B10 SENSOR DRIVER M: Himanshu Bhavani M: Elgin Perumbilly -- 2.34.1 From nobody Mon Jun 15 15:13:00 2026 Received: from MA0PR01CU012.outbound.protection.outlook.com (mail-southindiaazon11021139.outbound.protection.outlook.com [40.107.57.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B1EFF1A267; Fri, 24 Apr 2026 09:26:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.57.139 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777022807; cv=fail; b=mmiSFRVChk1klwcA9fVpWFBv5AUgncOPKAmEwIHIpWtciRwAW3n+ceGZ+i85Y6NwLOe2R7DJ5Nx9IfEJJR0H1VGBn2XpVNfZRsNWjKg2LWThqqUHybPt5c4PV0YrLTy128r9kZapJdjXSOQ4oD5t+cVLZc9iQ1JGHGwJLBgvAY8= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777022807; c=relaxed/simple; bh=WuuaruhaT7C/wGlqkY1oQnov/1f+CR4FaemcE9NfdEQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=qJZduBjwKZPmbNW0nq/3JbW0z7MquFA0qINFo6SjCTcdIT8sNw5c8nGsgbe+rw0g7L7xiMmLeVitvJ5t9epRhbJy9Ftk3E3/ww1iIXkBsxroMQCOvEc1+DnaMuk73k9bmcDh6gvlHRXDZx10YDlU5nQ0V+GAIVf9jWBR4W79NfE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=siliconsignals.io; spf=pass smtp.mailfrom=siliconsignals.io; dkim=pass (2048-bit key) header.d=siliconsignals.io header.i=@siliconsignals.io header.b=e1to7J7u; arc=fail smtp.client-ip=40.107.57.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=siliconsignals.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=siliconsignals.io Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siliconsignals.io header.i=@siliconsignals.io header.b="e1to7J7u" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=NJvtD4hVgMmzflswKG5aKZTJXgCvxAbbhUi/595t93sx4ChSzxZ0LCl/WwelU4/Gl1HT+ppSMLZCdySUU6l33B1n9/RZ7kEPfiBC49Bni3bcpshXJ4kJQ6vy1KY7Ani1G1jLDRXUiPZLU19OxV9kP7VYcb7kQ06E5iYeWA78xUkdTCPrkGZgHpuqEMI6hNsNfrepa2Aun6X2JVuzh47hTRJXXpO1X/DhU42k+ZhkRmkk++ry64gMhli3oKybr9XiJGd4g2wEdVkS8xKER0jZpVNRHmQW3ciDjv1bu97+DplZqYPj1/4IJKo+SFafNiAojHrFulWDK/lMJbcELWqB9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=OeUu3xngiyQHxj6JlAlxQGkbEVMYYsK/KTWZvRWaYKQ=; b=tJbJakunkqQgUxzZFzU4/zHSX+MC4FKSVYFBwT1qgPxMLq8a8XGF5zjsnzSTWyO2lIUWdeP2DsrWtu/vZIeL69q3ekrXRj322JgF3Ruc7tgiVz7j5ouepgpMnZT3AEscVJ++sp4GKPPF2ZU3hdKlnDR3f/bP569IxmSsPW7Q4vFvEfr1UEd+Nd/XRItbAwvqVkcvpOq5SbHWC4nyFLqawGCwh7qoby9sZrx/HLre4kI/pDGwm/56WuaHujHevDcc7/9Te5hBgIOgHHetfW3BUq7NaM+0cAyG2hoqxNEsfmia9udFFBzHWP3IGg/Kc1M02mo3spr3rm5ENW5HvJUuSw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=siliconsignals.io; dmarc=pass action=none header.from=siliconsignals.io; dkim=pass header.d=siliconsignals.io; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=siliconsignals.io; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=OeUu3xngiyQHxj6JlAlxQGkbEVMYYsK/KTWZvRWaYKQ=; b=e1to7J7ubnx3y/cFirlAW5GOwiVjyaoGbfGK7i2hHRsseApeGlz+WKU5D3Eu3Igsur8JVEiL3l2K03TwKzCdtOi4S34g++ozQzN+PqulfgbhqK4wzti8lZf5OzrlTwQ6ncqwvpc3DygIPJxH0K7BT9doLIbrUrBsaWjrK93Y7Rl+RmYw5cnuQ03EiSqFOEDCcaZNyPva1nRMQi39T+uaXnq5VhRXST7x3bxTTl4YE6Qv/niXPyt15pj9tqPEvCy02byU4GX0d1qfoV2yL0ipLvnHnkWEjZfaidOwCo8L4zDnGMwPoSTxmggAqH9hgploAd6C4agrBeNx7sF2m45JuA== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=siliconsignals.io; Received: from MA0P287MB2178.INDP287.PROD.OUTLOOK.COM (2603:1096:a01:11e::14) by MA5P287MB5221.INDP287.PROD.OUTLOOK.COM (2603:1096:a01:1c5::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.22; Fri, 24 Apr 2026 09:26:41 +0000 Received: from MA0P287MB2178.INDP287.PROD.OUTLOOK.COM ([fe80::f8da:c075:cde1:e167]) by MA0P287MB2178.INDP287.PROD.OUTLOOK.COM ([fe80::f8da:c075:cde1:e167%3]) with mapi id 15.20.9846.021; Fri, 24 Apr 2026 09:26:41 +0000 From: Elgin Perumbilly To: sakari.ailus@linux.intel.com, laurent.pinchart@ideasonboard.com Cc: Elgin Perumbilly , Tarang Raval , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hans Verkuil , Hans de Goede , Vladimir Zapolskiy , Mehdi Djait , Sylvain Petinot , Benjamin Mugnier , "Bryan O'Donoghue" , Himanshu Bhavani , Heimir Thor Sverrisson , Jingjing Xiong , Svyatoslav Ryhel , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/3] media: i2c: add os02g10 image sensor driver Date: Fri, 24 Apr 2026 14:55:46 +0530 Message-Id: <20260424092554.26130-3-elgin.perumbilly@siliconsignals.io> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260424092554.26130-1-elgin.perumbilly@siliconsignals.io> References: <20260424092554.26130-1-elgin.perumbilly@siliconsignals.io> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BM1PR01CA0154.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:68::24) To MA0P287MB2178.INDP287.PROD.OUTLOOK.COM (2603:1096:a01:11e::14) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MA0P287MB2178:EE_|MA5P287MB5221:EE_ X-MS-Office365-Filtering-Correlation-Id: aa3fba07-b0a9-4036-99f5-08dea1e3980b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|7416014|52116014|22082099003|18002099003|38350700014|56012099003; X-Microsoft-Antispam-Message-Info: idIQqNeFQY+1ChfA4PTReMvq7UYpOhcQanZUnwBi0cnkwGzRQ5NtgIeLWfbw8HcOk3bpPCEuFRks51HQ3oPMVEg7OK759nTqwR4gRTpffht0iGKOL+PDAaZzi+xLxPWAwNzyIC8js3qL0ZPB6X1CLNY+TxXBl5JgmzrEqjvd9cGAXWWE+S02mjPkEvmM7hFFY0TqwROfRjOneYJE3FFj3aG1H+KhpAwW2DyCuoWU/Vv3DFbkiUdy4DxiN6CibnNWn8ZfqdlQvdDjtTYVSduk+unUK/HfykMj5y1PyJLeMjtLp2M496YKECizpfoW0YRUNv3yfsZPPsif0fFuAStf47CJrUzJvS8BMPhCytoR4IrprYEcnnpxw/80yG4yTeYPvcysdCKNckXx0jZTRj1Q35hTHeNkfA217SvByK/adDCk+Ve0gJj91WoS9aLylL9EQkkwXu6LI1Plzgzclo8XSBBX9IoURCQN+DYcRmskSOWSkVi75HP99U3EQ9H/hx1+Ewq9SDUS8DywkP6axJM5MB2H9PvOtKvXUUZKaPGKzDE+EL4wMW0AlCZMnuCVTwSs755XrUVjn2z6tlalsbAb5Deja6hdWo/Jru2dJxHQTwOLeO4wVYDvB1u27M+0d68HVe4L/kd+TUEKWXwZrWtQV21fG9uRXbIs240S94610DDsZEy5bKG075xLnlbZQoQxmuJ0bPVrpq0pzVpMkjgY6KtFxugfNBOVYAOrWjcbUVADtSDsFemAW24zM4YT+iHFheQjB2nyYy45kD1ofg97laSQOc8AM/NgOGZmghTSAvk= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MA0P287MB2178.INDP287.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(13230040)(366016)(1800799024)(376014)(7416014)(52116014)(22082099003)(18002099003)(38350700014)(56012099003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?4eP6aMo+/Jt6qTyC85BKLViSYq7bHswjQbL2VbvlyFnGsFI3Jmtb2FMcnAqb?= =?us-ascii?Q?uWJAo0b/KGKjd7SDsVNT9CtNjtACB23tJDQIPSioQ/yBLwxWEDzSUac0CIn0?= =?us-ascii?Q?pqWymSQNwOw2aFhmgIqkpQ/3dTZcmIB7udNwphwXN+NTKTubejwfavd+7LDI?= =?us-ascii?Q?wXMW+BhT1NPSGAnW2wMhSaD/D0Y1Xg2YDe5a0O7ofwAzVHYpk3qwZKWlGL1m?= =?us-ascii?Q?UrgFYw6NuQTC14EHeN1ZRtLi5mlQ7HomNKzm53BCyI5io/oKUMq5j4bO0D15?= =?us-ascii?Q?d4FX+GrrYdFlEs0Ap4T/t206M04YKeYqKveHpdA/bztR/YxmAm7OsNLqRAF3?= =?us-ascii?Q?HAW3vlaoki2gG3JRGL3TaNcIogiCPANPJyHwxqYTGq0og6HMC5GEJoCplIBc?= =?us-ascii?Q?9LFZEbEGx1DRiVbNurxeC/25PARORrR0bxViEfEwcIgyocATvM/j9psbCMWw?= =?us-ascii?Q?dXP7SNbxEYEAVXXSzcjoc85Wrqkno5UEYq+j6tLJ1tFpTTnFji5PjIdTFkBU?= =?us-ascii?Q?aXe0jqkP62cTeAQ7Mib/UedLd+Q38hkuiikZOOpCmE1fc87EDhgLYVmaa4f+?= =?us-ascii?Q?fRCvV9kENYYonnsac9F6imCD9pwUwmZuXxYpBNQJo/FUhAINmJF8XwTw9fWX?= =?us-ascii?Q?Rd0QLDOJ8lqdafpJHfhV/jkNzDgXMvaKQmL8+23JK5ODo1D02ihqNIFldoxA?= =?us-ascii?Q?qqZhz3tf/AvTw0bkGFHGxY6CWOwHsBxFLCy5a0qLKNEeNVciMIVbGO2mz1Db?= =?us-ascii?Q?KhROTgQBGIeoCSEDZ5q7OHVumI4LZ7C878W5PVfkzLlbieW4zUdb7E2RaEip?= =?us-ascii?Q?cDIoMENumZPRbVPjLap0Zq2PQTt7Rte53T7BHe9PxmvlYzzkqQzzaCa23YAc?= =?us-ascii?Q?jmJAQkXzF91bfqnBoIZZmmcXYuiTxIhTtbOjZegop28JBWRDp3/2vFClKE7P?= =?us-ascii?Q?yaJKzH21jld4MR4eTkz3tGKu4PMHBb+aYKV/6gFGoo5nUs2fCfa3OiilRKS3?= =?us-ascii?Q?+rmhaP4sS/NiJL3GErrFDuBR4xnTHVEpZjS6s1X87FWP/0knPr4xmFbOUN81?= =?us-ascii?Q?IqK0WkXCFB45VqNDwp8ECRlagWIAZBQltpLyX0kPKV0Ef97dNl3nn9NGnOHM?= =?us-ascii?Q?GQh+NtE/kFgPcqMSIsa2uf0edNw2tvmxTg1JYKiTtQbSwt5XtuGNSt5QETit?= =?us-ascii?Q?/d9i20SN925jiV3W7r78r27hD4oYSrcar+Qk1wBQ/jXRC237bUVnwZW3ss5K?= =?us-ascii?Q?9bLXBFJg4lCrVgmpK6tz+9+Mjt3UWzymPdZBqhZ5aSmgS7U5RtWFNdzu4DL2?= =?us-ascii?Q?mh3gg2ERRSEAfuC2z29NU/gBmkrkzN7R1WKZMUMBCE6xqV2GQjwATuWi19hh?= =?us-ascii?Q?+JcQtYh2Jm62csKI05UAhzGq001+icvEukpzmKerS75NZkH1euwo5lq3PLUs?= =?us-ascii?Q?AwV9ueo46pPK4dlkogvuvUZd6rTzvbFD4RcaeGeRAp8fedLmD6F+rAzUSAVy?= =?us-ascii?Q?OG7e3ERVj3OkF9ZJnURneJMdMG4A3nq3CJphnMonVgfmSDHFCW0HvnCCdFoS?= =?us-ascii?Q?zzP6cYAFTJxgL3K7plxrmRaGQIjHkcM2vzpUaiKYWEoOhjeMYzNR+9/RSaQo?= =?us-ascii?Q?JqUCmcAolCwdyxY7UjFwYR1/08qpNUEi1ECXIvfXTevWuxc/Zz7M5fCRtXZf?= =?us-ascii?Q?Qt5L/i+xaGxHHHvte97C+j7T6itEq5O7/+QbXW5PpGnQjpkpyXIEaV6Je510?= =?us-ascii?Q?+I8kCFY+j/wOr9pZ7F+mnCqG4WKpOG8XUeDALRb0czxM8SbWPXfH?= X-OriginatorOrg: siliconsignals.io X-MS-Exchange-CrossTenant-Network-Message-Id: aa3fba07-b0a9-4036-99f5-08dea1e3980b X-MS-Exchange-CrossTenant-AuthSource: MA0P287MB2178.INDP287.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2026 09:26:41.5370 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 7ec5089e-a433-4bd1-a638-82ee62e21d37 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Kw0Niuc04HVivTuzbPIgWBMBDg8bpYVs3GuxPv06Kiop5KeyihoZe+RubD23864XuNVyPEVzhNXd0YYaMxKELJwooxYc03Okv2T6tma+p4DudyUTpwF02cgus35nVRyW X-MS-Exchange-Transport-CrossTenantHeadersStamped: MA5P287MB5221 Content-Type: text/plain; charset="utf-8" Add a v4l2 subdevice driver for the Omnivision os02g10 sensor. The Omnivision os02g10 is a CMOS image sensor with an active array size of 1920 x 1080. The following features are supported: - Manual exposure an gain control support - vblank/hblank control support - vflip/hflip control support - Test pattern control support - Supported resolution: 1920 x 1080 @ 30fps (SBGGR10) Signed-off-by: Elgin Perumbilly Reviewed-by: Tarang Raval --- MAINTAINERS | 1 + drivers/media/i2c/Kconfig | 10 + drivers/media/i2c/Makefile | 1 + drivers/media/i2c/os02g10.c | 949 ++++++++++++++++++++++++++++++++++++ 4 files changed, 961 insertions(+) create mode 100644 drivers/media/i2c/os02g10.c diff --git a/MAINTAINERS b/MAINTAINERS index 8a0a55073c30..693e71b51926 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19449,6 +19449,7 @@ M: Elgin Perumbilly L: linux-media@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/media/i2c/ovti,os02g10.yaml +F: drivers/media/i2c/os02g10.c =20 OMNIVISION OS05B10 SENSOR DRIVER M: Himanshu Bhavani diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 5eb1e0e0a87a..dd6e9562acf6 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -372,6 +372,16 @@ config VIDEO_OG0VE1B To compile this driver as a module, choose M here: the module will be called og0ve1b. =20 +config VIDEO_OS02G10 + tristate "OmniVision OS02G10 sensor support" + select V4L2_CCI_I2C + help + This is a Video4Linux2 sensor driver for Omnivision + OS02G10 camera sensor. + + To compile this driver as a module, choose M here: the + module will be called os02g10. + config VIDEO_OS05B10 tristate "OmniVision OS05B10 sensor support" select V4L2_CCI_I2C diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index a3a6396df3c4..a7554d2eb140 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -84,6 +84,7 @@ obj-$(CONFIG_VIDEO_MT9V032) +=3D mt9v032.o obj-$(CONFIG_VIDEO_MT9V111) +=3D mt9v111.o obj-$(CONFIG_VIDEO_OG01A1B) +=3D og01a1b.o obj-$(CONFIG_VIDEO_OG0VE1B) +=3D og0ve1b.o +obj-$(CONFIG_VIDEO_OS02G10) +=3D os02g10.o obj-$(CONFIG_VIDEO_OS05B10) +=3D os05b10.o obj-$(CONFIG_VIDEO_OV01A10) +=3D ov01a10.o obj-$(CONFIG_VIDEO_OV02A10) +=3D ov02a10.o diff --git a/drivers/media/i2c/os02g10.c b/drivers/media/i2c/os02g10.c new file mode 100644 index 000000000000..fad2dd0ad7aa --- /dev/null +++ b/drivers/media/i2c/os02g10.c @@ -0,0 +1,949 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * V4L2 Support for the OS02G10 + * + * Copyright (C) 2026 Silicon Signals Pvt. Ltd. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#define OS02G10_XCLK_FREQ (24 * HZ_PER_MHZ) + +/* Page 0 */ +#define OS02G10_REG_CHIPID CCI_REG24(0x002) +#define OS02G10_CHIPID 0x560247 + +#define OS02G10_REG_PLL_DIV_CTRL CCI_REG8(0x030) +#define OS02G10_REG_PLL_DCTL_BIAS_CTRL CCI_REG8(0x035) +#define OS02G10_REG_GATE_EN_CTRL CCI_REG8(0x038) +#define OS02G10_REG_DPLL_NC CCI_REG8(0x041) +#define OS02G10_REG_MP_PHASE_CTRL CCI_REG8(0x044) + +/* Page 1 */ +#define OS02G10_REG_STREAM_CTRL CCI_REG8(0x1b1) +#define OS02G10_STREAM_CTRL_ON 0x03 +#define OS02G10_STREAM_CTRL_OFF 0x00 + +#define OS02G10_REG_FRAME_SYNC CCI_REG8(0x101) + +#define OS02G10_REG_FRAME_LENGTH CCI_REG16(0x10e) +#define OS02G10_FRAME_LENGTH_MAX 0xffff +#define OS02G10_REG_HBLANK CCI_REG16(0x109) + +#define OS02G10_REG_FRAME_TEST_CTRL CCI_REG8(0x10d) +#define OS02G10_FRAME_EXP_SEPERATE_EN BIT(4) +#define OS02G10_TEST_PATTERN_ENABLE BIT(0) + +#define OS02G10_REG_ULP_PWD_DUMMY_CTRL CCI_REG8(0x13c) +#define OS02G10_REG_DC_LEVEL_LIMIT_EN CCI_REG8(0x146) +#define OS02G10_REG_DC_LEVEL_LIMIT_L CCI_REG8(0x147) +#define OS02G10_REG_BLC_DATA_LIMIT_L CCI_REG8(0x148) +#define OS02G10_REG_DC_BLC_LIMIT_H CCI_REG8(0x149) + +#define OS02G10_REG_HS_LP_CTRL CCI_REG8(0x192) +#define OS02G10_REG_HS_LEVEL CCI_REG8(0x19d) +#define OS02G10_REG_HS_DRV CCI_REG8(0x19e) + +#define OS02G10_REG_GB_SUBOFFSET CCI_REG8(0x1f0) +#define OS02G10_REG_BLUE_SUBOFFSET CCI_REG8(0x1f1) +#define OS02G10_REG_RED_SUBOFFSET CCI_REG8(0x1f2) +#define OS02G10_REG_GR_SUBOFFSET CCI_REG8(0x1f3) + +#define OS02G10_REG_ABL_TRIGGER CCI_REG8(0x1fa) +#define OS02G10_REG_ABL CCI_REG8(0x1fb) + +#define OS02G10_REG_H_SIZE_MIPI CCI_REG16(0x18e) +#define OS02G10_REG_V_SIZE_MIPI CCI_REG16(0x190) +#define OS02G10_REG_MIPI_TX_SPEED_CTRL CCI_REG8(0x1a1) + +#define OS02G10_REG_LONG_EXPOSURE CCI_REG16(0x103) +#define OS02G10_EXPOSURE_MIN 4 +#define OS02G10_EXPOSURE_STEP 1 +#define OS02G10_EXPOSURE_MARGIN 9 + +#define OS02G10_REG_ANALOG_GAIN CCI_REG8(0x124) +#define OS02G10_ANALOG_GAIN_MIN 0x10 +#define OS02G10_ANALOG_GAIN_MAX 0xf8 +#define OS02G10_ANALOG_GAIN_STEP 1 +#define OS02G10_ANALOG_GAIN_DEFAULT 0x10 + +#define OS02G10_REG_DIGITAL_GAIN_H CCI_REG8(0x137) +#define OS02G10_REG_DIGITAL_GAIN_L CCI_REG8(0x139) +#define OS02G10_DIGITAL_GAIN_MIN 0x40 +#define OS02G10_DIGITAL_GAIN_MAX 0x800 +#define OS02G10_DIGITAL_GAIN_STEP 64 +#define OS02G10_DIGITAL_GAIN_DEFAULT 0x40 + +#define OS02G10_REG_FLIP_MIRROR CCI_REG8(0x13f) +#define OS02G10_FLIP BIT(1) +#define OS02G10_MIRROR BIT(0) + +/* Page 2 */ +#define OS02G10_REG_V_START CCI_REG16(0x2a0) +#define OS02G10_REG_V_SIZE CCI_REG16(0x2a2) +#define OS02G10_REG_H_START CCI_REG16(0x2a4) +#define OS02G10_REG_H_SIZE CCI_REG16(0x2a6) + +#define OS02G10_REG_SIF_CTRL CCI_REG8(0x25e) +#define OS02G10_ORIENTATION_BAYER_FIX 0x32 + +#define OS02G10_LINK_FREQ_720MHZ (720 * HZ_PER_MHZ) + +/* OS02G10 native and active pixel array size */ +static const struct v4l2_rect os02g10_native_area =3D { + .top =3D 0, + .left =3D 0, + .width =3D 1928, + .height =3D 1088, +}; + +static const struct v4l2_rect os02g10_active_area =3D { + .top =3D 4, + .left =3D 4, + .width =3D 1920, + .height =3D 1080, +}; + +static const char * const os02g10_supply_name[] =3D { + "avdd", /* Analog power */ + "dovdd", /* Digital I/O power */ + "dvdd", /* Digital core power */ +}; + +struct os02g10 { + struct device *dev; + struct regmap *cci; + struct v4l2_subdev sd; + struct media_pad pad; + struct clk *xclk; + struct gpio_desc *reset_gpio; + struct regulator_bulk_data supplies[ARRAY_SIZE(os02g10_supply_name)]; + + /* V4L2 Controls */ + struct v4l2_ctrl_handler handler; + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *exposure; + struct v4l2_ctrl *vflip; + struct v4l2_ctrl *hflip; +}; + +struct os02g10_mode { + u32 width; + u32 height; + u32 vts_def; + u32 exp_def; + u32 x_start; + u32 y_start; +}; + +static const struct cci_reg_sequence os02g10_common_regs[] =3D { + { OS02G10_REG_PLL_DIV_CTRL, 0x0a}, + { OS02G10_REG_PLL_DCTL_BIAS_CTRL, 0x04}, + { OS02G10_REG_GATE_EN_CTRL, 0x11}, + { OS02G10_REG_DPLL_NC, 0x06}, + { OS02G10_REG_MP_PHASE_CTRL, 0x20}, + { CCI_REG8(0x119), 0x50}, + { CCI_REG8(0x11a), 0x0c}, + { CCI_REG8(0x11b), 0x0d}, + { CCI_REG8(0x11c), 0x00}, + { CCI_REG8(0x11d), 0x75}, + { CCI_REG8(0x11e), 0x52}, + { CCI_REG8(0x122), 0x14}, + { CCI_REG8(0x125), 0x44}, + { CCI_REG8(0x126), 0x0f}, + { OS02G10_REG_ULP_PWD_DUMMY_CTRL, 0xca}, + { CCI_REG8(0x13d), 0x4a}, + { CCI_REG8(0x140), 0x0f}, + { CCI_REG8(0x143), 0x38}, + { OS02G10_REG_DC_LEVEL_LIMIT_EN, 0x01}, + { OS02G10_REG_DC_LEVEL_LIMIT_L, 0x00}, + { OS02G10_REG_DC_BLC_LIMIT_H, 0x32}, + { CCI_REG8(0x150), 0x01}, + { CCI_REG8(0x151), 0x28}, + { CCI_REG8(0x152), 0x20}, + { CCI_REG8(0x153), 0x03}, + { CCI_REG8(0x157), 0x16}, + { CCI_REG8(0x159), 0x01}, + { CCI_REG8(0x15a), 0x01}, + { CCI_REG8(0x15d), 0x04}, + { CCI_REG8(0x16a), 0x04}, + { CCI_REG8(0x16b), 0x03}, + { CCI_REG8(0x16e), 0x28}, + { CCI_REG8(0x171), 0xc2}, + { CCI_REG8(0x172), 0x04}, + { CCI_REG8(0x173), 0x38}, + { CCI_REG8(0x174), 0x04}, + { CCI_REG8(0x179), 0x00}, + { CCI_REG8(0x17a), 0xb2}, + { CCI_REG8(0x17b), 0x10}, + { OS02G10_REG_HS_LP_CTRL, 0x02}, + { OS02G10_REG_HS_LEVEL, 0x03}, + { OS02G10_REG_HS_DRV, 0x55}, + { CCI_REG8(0x1b8), 0x70}, + { CCI_REG8(0x1b9), 0x70}, + { CCI_REG8(0x1ba), 0x70}, + { CCI_REG8(0x1bb), 0x70}, + { CCI_REG8(0x1bc), 0x00}, + { CCI_REG8(0x1c4), 0x6d}, + { CCI_REG8(0x1c5), 0x6d}, + { CCI_REG8(0x1c6), 0x6d}, + { CCI_REG8(0x1c7), 0x6d}, + { CCI_REG8(0x1cc), 0x11}, + { CCI_REG8(0x1cd), 0xe0}, + { CCI_REG8(0x1d0), 0x1b}, + { CCI_REG8(0x1d2), 0x76}, + { CCI_REG8(0x1d3), 0x68}, + { CCI_REG8(0x1d4), 0x68}, + { CCI_REG8(0x1d5), 0x73}, + { CCI_REG8(0x1d6), 0x73}, + { CCI_REG8(0x1e8), 0x55}, + { OS02G10_REG_GB_SUBOFFSET, 0x40}, + { OS02G10_REG_BLUE_SUBOFFSET, 0x40}, + { OS02G10_REG_RED_SUBOFFSET, 0x40}, + { OS02G10_REG_GR_SUBOFFSET, 0x40}, + { OS02G10_REG_ABL_TRIGGER, 0x1c}, + { OS02G10_REG_ABL, 0x33}, + { CCI_REG8(0x1fc), 0x80}, + { CCI_REG8(0x1fe), 0x80}, + { CCI_REG8(0x303), 0x67}, + { CCI_REG8(0x300), 0x59}, + { CCI_REG8(0x304), 0x11}, + { CCI_REG8(0x305), 0x04}, + { CCI_REG8(0x306), 0x0c}, + { CCI_REG8(0x307), 0x08}, + { CCI_REG8(0x308), 0x08}, + { CCI_REG8(0x309), 0x4f}, + { CCI_REG8(0x30b), 0x08}, + { CCI_REG8(0x30d), 0x26}, + { CCI_REG8(0x30f), 0x00}, + { CCI_REG8(0x234), 0xfe}, + { OS02G10_REG_MIPI_TX_SPEED_CTRL, 0x05}, +}; + +static const struct os02g10_mode supported_modes[] =3D { + { + .width =3D 1920, + .height =3D 1080, + .vts_def =3D 1246, + .exp_def =3D 1100, + .x_start =3D 2, + .y_start =3D 6, + }, +}; + +static const s64 link_freq_menu_items[] =3D { + OS02G10_LINK_FREQ_720MHZ, +}; + +static const char * const os02g10_test_pattern_menu[] =3D { + "Disabled", + "Colorbar", +}; + +static inline struct os02g10 *to_os02g10(struct v4l2_subdev *sd) +{ + return container_of_const(sd, struct os02g10, sd); +} + +static u32 os02g10_get_format_code(struct os02g10 *os02g10) +{ + static const u32 codes[2][2] =3D { + { MEDIA_BUS_FMT_SBGGR10_1X10, MEDIA_BUS_FMT_SGBRG10_1X10, }, + { MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SRGGB10_1X10, }, + }; + u32 code =3D codes[os02g10->vflip->val][os02g10->hflip->val]; + + return code; +} + +static int os02g10_set_ctrl(struct v4l2_ctrl *ctrl) +{ + struct os02g10 *os02g10 =3D container_of_const(ctrl->handler, + struct os02g10, handler); + struct v4l2_subdev_state *state; + struct v4l2_mbus_framefmt *fmt; + int ret =3D 0; + + state =3D v4l2_subdev_get_locked_active_state(&os02g10->sd); + fmt =3D v4l2_subdev_state_get_format(state, 0); + + if (ctrl->id =3D=3D V4L2_CID_VBLANK) { + /* Honour the VBLANK limits when setting exposure */ + s64 max =3D fmt->height + ctrl->val - OS02G10_EXPOSURE_MARGIN; + + ret =3D __v4l2_ctrl_modify_range(os02g10->exposure, + os02g10->exposure->minimum, max, + os02g10->exposure->step, + os02g10->exposure->default_value); + if (ret) + return ret; + } + + if (pm_runtime_get_if_active(os02g10->dev) =3D=3D 0) + return 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE: + cci_write(os02g10->cci, OS02G10_REG_LONG_EXPOSURE, + ctrl->val, &ret); + break; + case V4L2_CID_ANALOGUE_GAIN: + cci_write(os02g10->cci, OS02G10_REG_ANALOG_GAIN, + ctrl->val, &ret); + break; + case V4L2_CID_DIGITAL_GAIN: + cci_write(os02g10->cci, OS02G10_REG_DIGITAL_GAIN_L, + (ctrl->val & 0xff), &ret); + cci_write(os02g10->cci, OS02G10_REG_DIGITAL_GAIN_H, + ((ctrl->val >> 8) & 0x7), &ret); + break; + case V4L2_CID_VBLANK: + u64 vts =3D ctrl->val + fmt->height; + + cci_update_bits(os02g10->cci, OS02G10_REG_FRAME_TEST_CTRL, + OS02G10_FRAME_EXP_SEPERATE_EN, + OS02G10_FRAME_EXP_SEPERATE_EN, &ret); + cci_write(os02g10->cci, OS02G10_REG_FRAME_LENGTH, vts, &ret); + break; + case V4L2_CID_HFLIP: + case V4L2_CID_VFLIP: + cci_write(os02g10->cci, OS02G10_REG_FLIP_MIRROR, + os02g10->hflip->val | os02g10->vflip->val << 1, + &ret); + cci_write(os02g10->cci, OS02G10_REG_SIF_CTRL, + OS02G10_ORIENTATION_BAYER_FIX, &ret); + break; + case V4L2_CID_TEST_PATTERN: + cci_update_bits(os02g10->cci, + OS02G10_REG_FRAME_TEST_CTRL, + OS02G10_TEST_PATTERN_ENABLE, + ctrl->val ? OS02G10_TEST_PATTERN_ENABLE : 0, + &ret); + break; + default: + ret =3D -EINVAL; + break; + } + cci_write(os02g10->cci, OS02G10_REG_FRAME_SYNC, 0x01, &ret); + + pm_runtime_put(os02g10->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops os02g10_ctrl_ops =3D { + .s_ctrl =3D os02g10_set_ctrl, +}; + +static int os02g10_init_controls(struct os02g10 *os02g10) +{ + const struct os02g10_mode *mode =3D &supported_modes[0]; + struct v4l2_fwnode_device_properties props; + u64 vblank_def, exp_max, pixel_rate; + struct v4l2_ctrl_handler *ctrl_hdlr; + int ret; + + ctrl_hdlr =3D &os02g10->handler; + v4l2_ctrl_handler_init(ctrl_hdlr, 11); + + /* pixel_rate =3D link_freq * 2 * nr_of_lanes / bits_per_sample */ + pixel_rate =3D div_u64(OS02G10_LINK_FREQ_720MHZ * 2 * 2, 10); + v4l2_ctrl_new_std(ctrl_hdlr, &os02g10_ctrl_ops, V4L2_CID_PIXEL_RATE, 0, + pixel_rate, 1, pixel_rate); + + os02g10->link_freq =3D + v4l2_ctrl_new_int_menu(ctrl_hdlr, &os02g10_ctrl_ops, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(link_freq_menu_items) - 1, + 0, link_freq_menu_items); + if (os02g10->link_freq) + os02g10->link_freq->flags |=3D V4L2_CTRL_FLAG_READ_ONLY; + + vblank_def =3D mode->vts_def - mode->height; + os02g10->vblank =3D v4l2_ctrl_new_std(ctrl_hdlr, &os02g10_ctrl_ops, + V4L2_CID_VBLANK, vblank_def, + OS02G10_FRAME_LENGTH_MAX - mode->height, + 1, vblank_def); + + exp_max =3D mode->vts_def - OS02G10_EXPOSURE_MARGIN; + os02g10->exposure =3D + v4l2_ctrl_new_std(ctrl_hdlr, &os02g10_ctrl_ops, + V4L2_CID_EXPOSURE, + OS02G10_EXPOSURE_MIN, exp_max, + OS02G10_EXPOSURE_STEP, mode->exp_def); + + v4l2_ctrl_new_std(ctrl_hdlr, &os02g10_ctrl_ops, + V4L2_CID_ANALOGUE_GAIN, OS02G10_ANALOG_GAIN_MIN, + OS02G10_ANALOG_GAIN_MAX, OS02G10_ANALOG_GAIN_STEP, + OS02G10_ANALOG_GAIN_DEFAULT); + + v4l2_ctrl_new_std(ctrl_hdlr, &os02g10_ctrl_ops, + V4L2_CID_DIGITAL_GAIN, OS02G10_DIGITAL_GAIN_MIN, + OS02G10_DIGITAL_GAIN_MAX, OS02G10_DIGITAL_GAIN_STEP, + OS02G10_DIGITAL_GAIN_DEFAULT); + + os02g10->hflip =3D v4l2_ctrl_new_std(ctrl_hdlr, &os02g10_ctrl_ops, + V4L2_CID_HFLIP, 0, 1, 1, 0); + if (os02g10->hflip) + os02g10->hflip->flags |=3D V4L2_CTRL_FLAG_MODIFY_LAYOUT; + + os02g10->vflip =3D v4l2_ctrl_new_std(ctrl_hdlr, &os02g10_ctrl_ops, + V4L2_CID_VFLIP, 0, 1, 1, 0); + if (os02g10->vflip) + os02g10->vflip->flags |=3D V4L2_CTRL_FLAG_MODIFY_LAYOUT; + + v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &os02g10_ctrl_ops, + V4L2_CID_TEST_PATTERN, + ARRAY_SIZE(os02g10_test_pattern_menu) - 1, + 0, 0, os02g10_test_pattern_menu); + + ret =3D v4l2_fwnode_device_parse(os02g10->dev, &props); + if (ret) + goto err_handler_free; + + ret =3D v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, + &os02g10_ctrl_ops, &props); + if (ret) + goto err_handler_free; + + os02g10->sd.ctrl_handler =3D ctrl_hdlr; + + return 0; + +err_handler_free: + v4l2_ctrl_handler_free(ctrl_hdlr); + + return ret; +} + +static int os02g10_set_framefmt(struct os02g10 *os02g10, + struct v4l2_subdev_state *state) +{ + const struct v4l2_mbus_framefmt *format; + const struct os02g10_mode *mode; + int ret =3D 0; + + format =3D v4l2_subdev_state_get_format(state, 0); + mode =3D v4l2_find_nearest_size(supported_modes, + ARRAY_SIZE(supported_modes), width, + height, format->width, format->height); + + cci_write(os02g10->cci, OS02G10_REG_V_START, mode->y_start, &ret); + cci_write(os02g10->cci, OS02G10_REG_V_SIZE, mode->height, &ret); + cci_write(os02g10->cci, OS02G10_REG_V_SIZE_MIPI, mode->height, &ret); + cci_write(os02g10->cci, OS02G10_REG_H_START, mode->x_start, &ret); + cci_write(os02g10->cci, OS02G10_REG_H_SIZE, mode->width, &ret); + cci_write(os02g10->cci, OS02G10_REG_H_SIZE_MIPI, mode->width, &ret); + + return ret; +} + +static int os02g10_enable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct os02g10 *os02g10 =3D to_os02g10(sd); + int ret; + + ret =3D pm_runtime_resume_and_get(os02g10->dev); + if (ret < 0) + return ret; + + ret =3D cci_multi_reg_write(os02g10->cci, os02g10_common_regs, + ARRAY_SIZE(os02g10_common_regs), NULL); + if (ret) { + dev_err(os02g10->dev, "failed to write common registers\n"); + goto err_rpm_put; + } + + ret =3D os02g10_set_framefmt(os02g10, state); + if (ret) { + dev_err(os02g10->dev, "failed to set frame foramt\n"); + goto err_rpm_put; + } + + /* Apply customized values from user */ + ret =3D __v4l2_ctrl_handler_setup(os02g10->sd.ctrl_handler); + if (ret) + goto err_rpm_put; + + ret =3D cci_write(os02g10->cci, OS02G10_REG_STREAM_CTRL, + OS02G10_STREAM_CTRL_ON, NULL); + if (ret) + goto err_rpm_put; + + /* vflip and hflip cannot change during streaming */ + __v4l2_ctrl_grab(os02g10->vflip, true); + __v4l2_ctrl_grab(os02g10->hflip, true); + + return 0; + +err_rpm_put: + pm_runtime_put(os02g10->dev); + return ret; +} + +static int os02g10_disable_streams(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, u32 pad, + u64 streams_mask) +{ + struct os02g10 *os02g10 =3D to_os02g10(sd); + int ret; + + ret =3D cci_write(os02g10->cci, OS02G10_REG_STREAM_CTRL, + OS02G10_STREAM_CTRL_OFF, NULL); + if (ret) + dev_err(os02g10->dev, "Failed to stop stream\n"); + + __v4l2_ctrl_grab(os02g10->vflip, false); + __v4l2_ctrl_grab(os02g10->hflip, false); + + pm_runtime_put(os02g10->dev); + + return ret; +} + +static int os02g10_get_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_selection *sel) +{ + switch (sel->target) { + case V4L2_SEL_TGT_CROP_BOUNDS: + case V4L2_SEL_TGT_NATIVE_SIZE: + sel->r =3D os02g10_native_area; + return 0; + case V4L2_SEL_TGT_CROP: + case V4L2_SEL_TGT_CROP_DEFAULT: + sel->r =3D os02g10_active_area; + return 0; + default: + return -EINVAL; + } +} + +static int os02g10_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct os02g10 *os02g10 =3D to_os02g10(sd); + + if (code->index) + return -EINVAL; + + code->code =3D os02g10_get_format_code(os02g10); + + return 0; +} + +static int os02g10_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct os02g10 *os02g10 =3D to_os02g10(sd); + + if (fse->index >=3D ARRAY_SIZE(supported_modes)) + return -EINVAL; + + if (fse->code !=3D os02g10_get_format_code(os02g10)) + return -EINVAL; + + fse->min_width =3D supported_modes[fse->index].width; + fse->max_width =3D fse->min_width; + fse->min_height =3D supported_modes[fse->index].height; + fse->max_height =3D fse->min_height; + + return 0; +} + +static int os02g10_set_pad_format(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_format *fmt) +{ + struct os02g10 *os02g10 =3D to_os02g10(sd); + struct v4l2_mbus_framefmt *format; + const struct os02g10_mode *mode; + + format =3D v4l2_subdev_state_get_format(sd_state, 0); + + mode =3D v4l2_find_nearest_size(supported_modes, + ARRAY_SIZE(supported_modes), + width, height, + fmt->format.width, fmt->format.height); + + fmt->format.code =3D os02g10_get_format_code(os02g10); + fmt->format.width =3D mode->width; + fmt->format.height =3D mode->height; + fmt->format.field =3D V4L2_FIELD_NONE; + fmt->format.colorspace =3D V4L2_COLORSPACE_RAW; + fmt->format.quantization =3D V4L2_QUANTIZATION_FULL_RANGE; + fmt->format.xfer_func =3D V4L2_XFER_FUNC_NONE; + + *format =3D fmt->format; + + if (fmt->which =3D=3D V4L2_SUBDEV_FORMAT_ACTIVE) { + u32 vblank_def =3D mode->vts_def - mode->height; + + int ret =3D __v4l2_ctrl_modify_range(os02g10->vblank, vblank_def, + OS02G10_FRAME_LENGTH_MAX - + mode->height, 1, vblank_def); + if (ret) + return ret; + } + + return 0; +} + +static int os02g10_init_state(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state) +{ + struct os02g10 *os02g10 =3D to_os02g10(sd); + struct v4l2_subdev_format fmt =3D { + .which =3D V4L2_SUBDEV_FORMAT_TRY, + .format =3D { + .code =3D os02g10_get_format_code(os02g10), + .width =3D supported_modes[0].width, + .height =3D supported_modes[0].height, + }, + }; + + os02g10_set_pad_format(sd, state, &fmt); + + return 0; +} + +static const struct v4l2_subdev_video_ops os02g10_video_ops =3D { + .s_stream =3D v4l2_subdev_s_stream_helper, +}; + +static const struct v4l2_subdev_pad_ops os02g10_pad_ops =3D { + .enum_mbus_code =3D os02g10_enum_mbus_code, + .get_fmt =3D v4l2_subdev_get_fmt, + .set_fmt =3D os02g10_set_pad_format, + .get_selection =3D os02g10_get_selection, + .enum_frame_size =3D os02g10_enum_frame_size, + .enable_streams =3D os02g10_enable_streams, + .disable_streams =3D os02g10_disable_streams, +}; + +static const struct v4l2_subdev_ops os02g10_subdev_ops =3D { + .video =3D &os02g10_video_ops, + .pad =3D &os02g10_pad_ops, +}; + +static const struct v4l2_subdev_internal_ops os02g10_internal_ops =3D { + .init_state =3D os02g10_init_state, +}; + +static int os02g10_power_on(struct device *dev) +{ + struct v4l2_subdev *sd =3D dev_get_drvdata(dev); + struct os02g10 *os02g10 =3D to_os02g10(sd); + int ret; + + ret =3D regulator_bulk_enable(ARRAY_SIZE(os02g10_supply_name), + os02g10->supplies); + if (ret) { + dev_err(os02g10->dev, "failed to enable regulators\n"); + return ret; + } + + /* T4: delay from DOVDD stable to MCLK on */ + fsleep(5 * USEC_PER_MSEC); + + ret =3D clk_prepare_enable(os02g10->xclk); + if (ret) { + dev_err(os02g10->dev, "failed to enable clock\n"); + goto err_regulator_off; + } + + /* T3: delay from DVDD stable to sensor power up stable */ + fsleep(5 * USEC_PER_MSEC); + + gpiod_set_value_cansleep(os02g10->reset_gpio, 0); + + /* T5: delay from sensor power up stable to SCCB initialization */ + fsleep(5 * USEC_PER_MSEC); + + return 0; + +err_regulator_off: + regulator_bulk_disable(ARRAY_SIZE(os02g10_supply_name), os02g10->supplies= ); + return ret; +} + +static int os02g10_power_off(struct device *dev) +{ + struct v4l2_subdev *sd =3D dev_get_drvdata(dev); + struct os02g10 *os02g10 =3D to_os02g10(sd); + + clk_disable_unprepare(os02g10->xclk); + gpiod_set_value_cansleep(os02g10->reset_gpio, 1); + regulator_bulk_disable(ARRAY_SIZE(os02g10_supply_name), os02g10->supplies= ); + + return 0; +} + +static int os02g10_identify_module(struct os02g10 *os02g10) +{ + u64 chip_id; + int ret; + + ret =3D cci_read(os02g10->cci, OS02G10_REG_CHIPID, &chip_id, NULL); + if (ret) + return dev_err_probe(os02g10->dev, ret, + "failed to read chip id %x\n", + OS02G10_CHIPID); + + if (chip_id !=3D OS02G10_CHIPID) + return dev_err_probe(os02g10->dev, -EIO, + "chip id mismatch: %x!=3D%llx\n", + OS02G10_CHIPID, chip_id); + + return 0; +} + +static int os02g10_parse_endpoint(struct os02g10 *os02g10) +{ + struct v4l2_fwnode_endpoint bus_cfg =3D { + .bus_type =3D V4L2_MBUS_CSI2_DPHY, + }; + unsigned long link_freq_bitmap; + struct fwnode_handle *ep; + int ret; + + ep =3D fwnode_graph_get_next_endpoint(dev_fwnode(os02g10->dev), NULL); + ret =3D v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg); + fwnode_handle_put(ep); + if (ret) + return ret; + + if (bus_cfg.bus.mipi_csi2.num_data_lanes !=3D 2) { + ret =3D dev_err_probe(os02g10->dev, -EINVAL, + "only 2 data lanes are supported\n"); + goto error_out; + } + + ret =3D v4l2_link_freq_to_bitmap(os02g10->dev, bus_cfg.link_frequencies, + bus_cfg.nr_of_link_frequencies, + link_freq_menu_items, + ARRAY_SIZE(link_freq_menu_items), + &link_freq_bitmap); + if (ret) { + ret =3D dev_err_probe(os02g10->dev, -EINVAL, + "only 720MHz frequency is available\n"); + goto error_out; + } + +error_out: + v4l2_fwnode_endpoint_free(&bus_cfg); + + return ret; +}; + +static const struct regmap_range_cfg os02g10_ranges[] =3D { + { + .range_min =3D 0x0000, + .range_max =3D 0x03ff, + .selector_reg =3D 0xfd, + .selector_mask =3D 0x03, + .selector_shift =3D 0, + .window_start =3D 0x00, + .window_len =3D 0x100, + }, +}; + +static const struct regmap_config os02g10_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + .reg_format_endian =3D REGMAP_ENDIAN_BIG, + .max_register =3D 0x3ff, + .ranges =3D os02g10_ranges, + .num_ranges =3D ARRAY_SIZE(os02g10_ranges), + .disable_locking =3D true, +}; + +static int os02g10_probe(struct i2c_client *client) +{ + struct os02g10 *os02g10; + unsigned int xclk_freq; + int ret; + + os02g10 =3D devm_kzalloc(&client->dev, sizeof(*os02g10), GFP_KERNEL); + if (!os02g10) + return -ENOMEM; + + os02g10->dev =3D &client->dev; + + v4l2_i2c_subdev_init(&os02g10->sd, client, &os02g10_subdev_ops); + os02g10->sd.internal_ops =3D &os02g10_internal_ops; + + /* + * This is not using devm_cci_regmap_init_i2c(), because the driver + * makes use of regmap's pagination feature. The chosen settings are + * compatible with the CCI helpers. + */ + os02g10->cci =3D devm_regmap_init_i2c(client, &os02g10_regmap_config); + if (IS_ERR(os02g10->cci)) + return dev_err_probe(os02g10->dev, PTR_ERR(os02g10->cci), + "failed to initialize CCI\n"); + + ret =3D os02g10_parse_endpoint(os02g10); + if (ret) + return dev_err_probe(os02g10->dev, ret, + "failed to parse endpoint configuration\n"); + + /* Get system clock (xvclk) */ + os02g10->xclk =3D devm_v4l2_sensor_clk_get(os02g10->dev, NULL); + if (IS_ERR(os02g10->xclk)) + return dev_err_probe(os02g10->dev, PTR_ERR(os02g10->xclk), + "failed to get xclk\n"); + + xclk_freq =3D clk_get_rate(os02g10->xclk); + if (xclk_freq !=3D OS02G10_XCLK_FREQ) + return dev_err_probe(os02g10->dev, -EINVAL, + "xclk frequency not supported: %u Hz\n", + xclk_freq); + + for (unsigned int i =3D 0; i < ARRAY_SIZE(os02g10_supply_name); i++) + os02g10->supplies[i].supply =3D os02g10_supply_name[i]; + + ret =3D devm_regulator_bulk_get(os02g10->dev, + ARRAY_SIZE(os02g10_supply_name), + os02g10->supplies); + if (ret) + return dev_err_probe(os02g10->dev, ret, + "failed to get regulators\n"); + + os02g10->reset_gpio =3D devm_gpiod_get_optional(os02g10->dev, + "reset", GPIOD_OUT_HIGH); + if (IS_ERR(os02g10->reset_gpio)) + return dev_err_probe(os02g10->dev, PTR_ERR(os02g10->reset_gpio), + "failed to get reset GPIO\n"); + + ret =3D os02g10_power_on(os02g10->dev); + if (ret) + return ret; + + ret =3D os02g10_identify_module(os02g10); + if (ret) + goto error_power_off; + + ret =3D os02g10_init_controls(os02g10); + if (ret) + goto error_power_off; + + /* Initialize subdev */ + os02g10->sd.flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE; + os02g10->sd.entity.function =3D MEDIA_ENT_F_CAM_SENSOR; + os02g10->pad.flags =3D MEDIA_PAD_FL_SOURCE; + + ret =3D media_entity_pads_init(&os02g10->sd.entity, 1, &os02g10->pad); + if (ret) { + dev_err_probe(os02g10->dev, ret, "failed to init entity pads\n"); + goto error_handler_free; + } + + os02g10->sd.state_lock =3D os02g10->handler.lock; + ret =3D v4l2_subdev_init_finalize(&os02g10->sd); + if (ret) { + dev_err_probe(os02g10->dev, ret, "subdev init error\n"); + goto error_media_entity; + } + + pm_runtime_set_active(os02g10->dev); + pm_runtime_enable(os02g10->dev); + + ret =3D v4l2_async_register_subdev_sensor(&os02g10->sd); + if (ret) { + dev_err_probe(os02g10->dev, ret, + "failed to register os02g10 sub-device\n"); + goto error_subdev_cleanup; + } + + pm_runtime_idle(os02g10->dev); + + return 0; + +error_subdev_cleanup: + v4l2_subdev_cleanup(&os02g10->sd); + pm_runtime_disable(os02g10->dev); + pm_runtime_set_suspended(os02g10->dev); + +error_media_entity: + media_entity_cleanup(&os02g10->sd.entity); + +error_handler_free: + v4l2_ctrl_handler_free(os02g10->sd.ctrl_handler); + +error_power_off: + os02g10_power_off(os02g10->dev); + + return ret; +} + +static void os02g10_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd =3D i2c_get_clientdata(client); + struct os02g10 *os02g10 =3D to_os02g10(sd); + + v4l2_async_unregister_subdev(sd); + v4l2_subdev_cleanup(&os02g10->sd); + media_entity_cleanup(&sd->entity); + v4l2_ctrl_handler_free(os02g10->sd.ctrl_handler); + + pm_runtime_disable(&client->dev); + if (!pm_runtime_status_suspended(&client->dev)) { + os02g10_power_off(&client->dev); + pm_runtime_set_suspended(&client->dev); + } +} + +static DEFINE_RUNTIME_DEV_PM_OPS(os02g10_pm_ops, + os02g10_power_off, os02g10_power_on, NULL); + +static const struct of_device_id os02g10_id[] =3D { + { .compatible =3D "ovti,os02g10" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, os02g10_id); + +static struct i2c_driver os02g10_driver =3D { + .driver =3D { + .name =3D "os02g10", + .pm =3D pm_ptr(&os02g10_pm_ops), + .of_match_table =3D os02g10_id, + }, + .probe =3D os02g10_probe, + .remove =3D os02g10_remove, +}; +module_i2c_driver(os02g10_driver); + +MODULE_DESCRIPTION("OS02G10 Camera Sensor Driver"); +MODULE_AUTHOR("Tarang Raval "); +MODULE_AUTHOR("Elgin Perumbilly "); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Mon Jun 15 15:13:00 2026 Received: from MA0PR01CU012.outbound.protection.outlook.com (mail-southindiaazon11021102.outbound.protection.outlook.com [40.107.57.102]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEB9937F8A1; Fri, 24 Apr 2026 09:27:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.57.102 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777022822; cv=fail; b=rQyyyOR3c/tuHA7vRnNUco/P/4rrEDvuUFwDcYKMZMlpNJ4kFNhlEXUZTUAfX2q9HxrNwOBMmV3I50TwCpmroapi+knfKMIyEdDXAVUeBpKUB2loh0wzDkwjaDN7eR2e37UF1NUdepJDEOyN6hpwb9FBrpoTr4H9enGrYr+uMLQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777022822; c=relaxed/simple; bh=vH7uLCJuHQGCr5fpyfxt4GnB3K4jFMcK0xKl2cGKpxM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: Content-Type:MIME-Version; b=qNiUH9KUk3ibwLa+UnWljYUzILV3f1DeJIGEJbYProHJx4e5CqLuI2hI3qfRe+fFlD7Xhqe0ltqceaBFJ4P4q+7ydeyjccQFDBu5BJEPEamrGpuQK9/7vj8I8owCBzCvSdYN+jLl1lGsN0b3GnAz6TOp2/w9AbTR4dnstTptcXc= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=siliconsignals.io; spf=pass smtp.mailfrom=siliconsignals.io; dkim=pass (2048-bit key) header.d=siliconsignals.io header.i=@siliconsignals.io header.b=bktPUrzT; arc=fail smtp.client-ip=40.107.57.102 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=siliconsignals.io Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=siliconsignals.io Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siliconsignals.io header.i=@siliconsignals.io header.b="bktPUrzT" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Qfegl43Ncch7wqsd/7yjCWn8Vf0nnuRi6B3LLo1bY1YYUg+GC4AdrgCIhqsgCPyUYkn6GKcJSnQJaJ5RoNp1bTe2kylzalU+v45GwErIettCdaLdewdkdaTmDipJSA/lGhTdT1M3fSQWXkUq6k+qTX1nf9AOQqIPhbxZic2PHyN5hKTY7KvJzNEaS1taflPUw9cu939l0cNAh0fbpBiEAYe84sXTDVWI1xbhvbLDrBxkNIq9EeZB+ZbuPsLvLbC7ynW83ktGQRdtg+Ka9Yem9NqCY/R6OOmlEL3bnsJU+7dBHelZOKW8dOY1sna5ML8vxZJPwMRCLd6BNdX6ZBLk9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=I1Qu/wUrVKW3FAqXWxiWByaI3VROVzUpSxXXeVqkmVg=; b=KVkrDpaF9mM8GBBu8icr+kETRGWYzq3K5aNZnX9MHtZacVO1vDxGBcXiPwToMcPuLCw9wantl7iNGfSPP2zjWzv7GkBb+7oj1OX4Hw3QuiAq0b1n7ewn3FqVDlT3MlZYrSDfIIBITfErrC7/2Xc2baHSqVydAzN1QrEUQ17g/Z9HWnjD7izTCXY8nn1RuVlEj/ATY/z1Gao5VOBMdFvnQvsvyD2JHVSFcXHAxdcbExXFEpkDXIaXuJGR2ihaKDt7j0euVAHGDgL/4sE5DbpmJnhGXJSgUFxMRDdfPqhYjDSCzo2cNedVzZXMqQOWfwt+o631l4BhO2JKmZbb6U6tQw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=siliconsignals.io; dmarc=pass action=none header.from=siliconsignals.io; dkim=pass header.d=siliconsignals.io; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=siliconsignals.io; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=I1Qu/wUrVKW3FAqXWxiWByaI3VROVzUpSxXXeVqkmVg=; b=bktPUrzTYSlW41gUU4zC8Bqsgy+pON9LLv7q8r3xjB2Zto7bNPcaFqfoh0kH3WcfzncI3DevyJEFsDi2x30AkQsmYH3Ozt0VD8q2WWniAdqLeBJFwvn363+IPGrlLnkfNoWxugcYMUJVs1+HLyXduqaBiBQDaDS/EyeEraZkbdFfZ5YY/voWWppJ+TRaFXgySz/VVyhgPgx8KlOqDXQpWlmI0GSw0JCEOkY8jRiSqmN9V8z97KU6XmmiAZ0quIT1pzYLcFigvf35+1Taem0yMAulY5vPQGpdC/axgejBO5R/VJMNrLstY2nKJqKW2NPPfvJACHHIR7SytCNdV/vSZw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=siliconsignals.io; Received: from MA0P287MB2178.INDP287.PROD.OUTLOOK.COM (2603:1096:a01:11e::14) by MA5P287MB5221.INDP287.PROD.OUTLOOK.COM (2603:1096:a01:1c5::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.22; Fri, 24 Apr 2026 09:26:58 +0000 Received: from MA0P287MB2178.INDP287.PROD.OUTLOOK.COM ([fe80::f8da:c075:cde1:e167]) by MA0P287MB2178.INDP287.PROD.OUTLOOK.COM ([fe80::f8da:c075:cde1:e167%3]) with mapi id 15.20.9846.021; Fri, 24 Apr 2026 09:26:58 +0000 From: Elgin Perumbilly To: sakari.ailus@linux.intel.com, laurent.pinchart@ideasonboard.com Cc: Tarang Raval , Elgin Perumbilly , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hans Verkuil , Hans de Goede , Vladimir Zapolskiy , Mehdi Djait , Sylvain Petinot , Benjamin Mugnier , "Bryan O'Donoghue" , Heimir Thor Sverrisson , Hardevsinh Palaniya , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/3] media: i2c: os02g10: implement crop handling with set_selection Date: Fri, 24 Apr 2026 14:55:47 +0530 Message-Id: <20260424092554.26130-4-elgin.perumbilly@siliconsignals.io> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260424092554.26130-1-elgin.perumbilly@siliconsignals.io> References: <20260424092554.26130-1-elgin.perumbilly@siliconsignals.io> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BM1PR01CA0154.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:68::24) To MA0P287MB2178.INDP287.PROD.OUTLOOK.COM (2603:1096:a01:11e::14) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MA0P287MB2178:EE_|MA5P287MB5221:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c6cdb5b-7d6a-4e71-ac5f-08dea1e3a1e6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|7416014|52116014|22082099003|18002099003|38350700014|56012099003; X-Microsoft-Antispam-Message-Info: uybzRO6x5disxonNzFEaeREaebHAtVN2lA4TC7HwqoMVdVAx9L+Zhzk220lm4ORVoFsFwR5Gm219bs5XGT7BrY0vQnV2kNnJphX1aWKjXHmlkRl7IkWSvqJVsRUJZdFA49B+NsCWhB2oWs7Jb53XEjd8fkTUNHPQHYfn1diwJIoGapFQ/2hGqqdo/ZlTD0AbEb7zEYX7Ebazg4PJ+OrEw773WA675eC9Wi8Tj1KVqcEVv0gcw2E59oJSYw5TSVeTet1xZyMM54/S/AHpmPqVqOWHuYf1T4MmF77yCYZAo0kTgkrjSd/qD2O/Jp0e8a3qXfKoVJvd7DsxmayIkGmB+9iRi7of7yXCOTBbP9bdlIiptg02AbYmPFTReeeoeAmSCOyLBOFAHRFQn5PfJaxYo0n7E3cOV1pnPGo7BjQcpiOGNcmGpvMqX/X5Mo/o5yyMPPQFtWo0FXWJSqYuHWD6/ZeytkCW+nirQX4Gnmy1f3vIBRe/Ve8wfN4jKinQQvsSRQB/YWCD3tTTT6WMLG/QzEnKw2EFqKcKAWNFkm7RkCNHMOjsjK+CJt+awryTFkHy+tDCRhfbvAjWnK39IyQcSjgO+QfMJAzxZh2mX9fPLqaRl70/FMYTm4dDfmSHmBsrPXkH/GqJG3Q4iBdz1o6LcyOb9TV8w/27EFEvoyhpXKVHkJTKis5Wsrg2WMQhfp5Z7lE7f4UIWcgoLgVLvit5uNJEMhrm2YGaym3d3uOJgMoadZLf1GdfqXoi/4srVqSgtVnJ+dWsG3sGOJFamgP7im3WcjpcdTApxkihdkN0ulc= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:MA0P287MB2178.INDP287.PROD.OUTLOOK.COM;PTR:;CAT:NONE;SFS:(13230040)(366016)(1800799024)(376014)(7416014)(52116014)(22082099003)(18002099003)(38350700014)(56012099003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?ym/dIhTBgGtUXgoyKwr3CHsw6sGE++cYgh1R5FFvSFlsG+MBn1EEtII95gmn?= =?us-ascii?Q?r4UQlsmR0MdlVEFMQIGgjFCh6+TYgmhERpla9PojsQWNnq+RcHn2oyK0sREI?= =?us-ascii?Q?W54jmj2v/LXv8vK5En5t+7xrw5NZngCTaSUgslPcb4pnSk/5G4VxnnOcitrB?= =?us-ascii?Q?70BTHAU45ueAF+7uT4kugjPGaTq+N4tHtN/Sm/ku4fbGtcDdhLA32b607k1S?= =?us-ascii?Q?m6LGRan9MxXRrSqvTFL1NUh61DMovn8crch5rdgEU0JUf9jNXyaHFfd0WJwN?= =?us-ascii?Q?ZRCDB5sJH4UUnkL5TWOf4UnUU5bj0rWBTB58CSnlQuXS78GpYNmDGdYMAAFW?= =?us-ascii?Q?3dMlG6dxgC6R51wCl7Ns0waAiwwbBJZjvkfl7ePbau8upLNLPqqPvONd9PiE?= =?us-ascii?Q?z/2Jg33sUSUv38cpBeiP3q+VRqHcYHLi7OWXb5+YL9d8Z4gEfxZiodUMTIM/?= =?us-ascii?Q?SpFNu9nQADhN1mH4rpK6uAVu7iaaoR2CHTVFjZGpyBd+omgX+YBz8PpAZSsY?= =?us-ascii?Q?uJgo+y4u98UDwNIJS6FGWIHHM4Vhe3QMQy0cxrJ4Ymb4xCGbkmk0wanzp9l7?= =?us-ascii?Q?lj12zvCvE7LKDz8Pf1k4dq4NIfcJBlQnfhBoF9CR6r2SqoWniYUTrIJRnEWE?= =?us-ascii?Q?UISXt2T0NExawRa/stXrMXY+D1b6KNWMYj9lQN3h06tan99Vldbq3S9MKkIj?= =?us-ascii?Q?NGbXQkSPsdEZSm4dxoL67ofM1Bp+ZL15FVUrPEPJvvxhsHFvkIRv3XrYPLZI?= =?us-ascii?Q?w6dFFVHMIW57osyp0KPblkmzX1iRr3oV09dU3Xdl4M0AR/cr8pjaCs57GofH?= =?us-ascii?Q?o9oa719lH4seHuSB7dFr7GPiWQR6Y62WjzgzU+SEUN7XhVF0NX4uLgFBxOa6?= =?us-ascii?Q?n5Ww6SlfPGIewErbUqhmHYMs/IR8fonHgIKxWJJYmGipezpJ0x5rvG4i1q4R?= =?us-ascii?Q?WHlnJ8yQ4ttFkoUPcSPpQIpnY6RUtWenF+87wVw4unwfwhG+bFEpgYo2ck8j?= =?us-ascii?Q?w4UiJcye1ji1a4ZKt8U6xIzgAP0Gw7uneS2TCYtjsCbRWhNHjzFPYb0d40ha?= =?us-ascii?Q?z7vaYQYUET5KZaVLxm+qk+LnLEf0r+72En63imUuPU2I32VrPMRLxOlUjPti?= =?us-ascii?Q?68Rhw+AVzHidUomYUm5VHrg+mdo/k59NqYHMe6pADhA6JdD/hsFvpqE1TRh7?= =?us-ascii?Q?2ykKtqjjF5bmr6S+AKkSGMZ677sD8tMyf+rCATimfuOYmCrZ5dE6yJfT06Wh?= =?us-ascii?Q?vF0zg10zOxThxOMFXYhhzZznroJNv+Q1OiIOgD9O7pQHMJmyXiMXzg1sVKWk?= =?us-ascii?Q?MUayOJHNQLKtd7jx6OJ7xKKa9uS4+zv2Q2Qh8HT0nAuO9CdxO7uk2m6A6OiX?= =?us-ascii?Q?DqDuS3fETechXVEATt6QVmjLpwc9kjN+v+DI5gFQdTVFC0aU5AAZjugnc7Nw?= =?us-ascii?Q?DsbXu6tjEr8GlYWMlyv1uppg83FOuW8lf03ypMEyt+It5t66meVibNw2Hhf6?= =?us-ascii?Q?QVjw0wdyFAI2xLxbbO87Ayp3ImDX2+Gxn/zehorluG4YMzw+7/6x43cYTCcd?= =?us-ascii?Q?s/er9TJc1PpJXlVLZ2UMznu91HnJu0NoERF0e/2gRlfdwRjHZv3xIdZvBHXe?= =?us-ascii?Q?dQ0rPkRFcPsKUH5ymSUuEwyGj+LHEEnPX7/Xr9SYHNgxIKRoBrotnsUsW4kQ?= =?us-ascii?Q?TyhkUOfRmp/WDutmhqgBhuLXRyULrMTJDmcGOHj25rVALztP0dTDCXQLuRxJ?= =?us-ascii?Q?dcyjonS1ApPtIacYhrBieabZQTOFqSjky3xxGP3eNaASCCsRGf1l?= X-OriginatorOrg: siliconsignals.io X-MS-Exchange-CrossTenant-Network-Message-Id: 1c6cdb5b-7d6a-4e71-ac5f-08dea1e3a1e6 X-MS-Exchange-CrossTenant-AuthSource: MA0P287MB2178.INDP287.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2026 09:26:57.9894 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 7ec5089e-a433-4bd1-a638-82ee62e21d37 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: v+lYBaadYLEEeu1WH4Wh/VcdVZ0LlijPORj1oeZzWHClSKqAk4OXuNU6bzxYf8k8TAV77Gt3xRitOvhKZa5bLGRdT08laQx/CNMBP6fQrZOeMsqjG4z8yG7T4k6zY3BD X-MS-Exchange-Transport-CrossTenantHeadersStamped: MA5P287MB5221 Content-Type: text/plain; charset="utf-8" From: Tarang Raval Add crop support to os02g10 by implementing .set_selection() and storing the crop rectangle in subdev state. Initialize the default crop to the active area, make set_fmt() use the current crop, and update the output format when the crop size changes. Also program the sensor window from the active crop/format state instead of using the fixed supported_modes entry. This allows userspace to configure the sensor crop window explicitly. Signed-off-by: Tarang Raval Signed-off-by: Elgin Perumbilly --- drivers/media/i2c/os02g10.c | 166 ++++++++++++++++++++++-------------- 1 file changed, 103 insertions(+), 63 deletions(-) diff --git a/drivers/media/i2c/os02g10.c b/drivers/media/i2c/os02g10.c index fad2dd0ad7aa..9bf8f5d1caea 100644 --- a/drivers/media/i2c/os02g10.c +++ b/drivers/media/i2c/os02g10.c @@ -112,6 +112,11 @@ #define OS02G10_ORIENTATION_BAYER_FIX 0x32 =20 #define OS02G10_LINK_FREQ_720MHZ (720 * HZ_PER_MHZ) +#define OS02G10_WINDOW_WIDTH_MIN 2 +#define OS02G10_WINDOW_HEIGHT_MIN 2 +#define OS02G10_VBLANK_DEF 166 +#define OS02G10_VBLANK_MIN 25 +#define OS02G10_EXPOSURE_DEF 1100 =20 /* OS02G10 native and active pixel array size */ static const struct v4l2_rect os02g10_native_area =3D { @@ -152,15 +157,6 @@ struct os02g10 { struct v4l2_ctrl *hflip; }; =20 -struct os02g10_mode { - u32 width; - u32 height; - u32 vts_def; - u32 exp_def; - u32 x_start; - u32 y_start; -}; - static const struct cci_reg_sequence os02g10_common_regs[] =3D { { OS02G10_REG_PLL_DIV_CTRL, 0x0a}, { OS02G10_REG_PLL_DCTL_BIAS_CTRL, 0x04}, @@ -245,17 +241,6 @@ static const struct cci_reg_sequence os02g10_common_re= gs[] =3D { { OS02G10_REG_MIPI_TX_SPEED_CTRL, 0x05}, }; =20 -static const struct os02g10_mode supported_modes[] =3D { - { - .width =3D 1920, - .height =3D 1080, - .vts_def =3D 1246, - .exp_def =3D 1100, - .x_start =3D 2, - .y_start =3D 6, - }, -}; - static const s64 link_freq_menu_items[] =3D { OS02G10_LINK_FREQ_720MHZ, }; @@ -295,11 +280,12 @@ static int os02g10_set_ctrl(struct v4l2_ctrl *ctrl) if (ctrl->id =3D=3D V4L2_CID_VBLANK) { /* Honour the VBLANK limits when setting exposure */ s64 max =3D fmt->height + ctrl->val - OS02G10_EXPOSURE_MARGIN; + s64 def =3D (max < OS02G10_EXPOSURE_DEF) ? max + : OS02G10_EXPOSURE_DEF; =20 ret =3D __v4l2_ctrl_modify_range(os02g10->exposure, os02g10->exposure->minimum, max, - os02g10->exposure->step, - os02g10->exposure->default_value); + os02g10->exposure->step, def); if (ret) return ret; } @@ -362,10 +348,9 @@ static const struct v4l2_ctrl_ops os02g10_ctrl_ops =3D= { =20 static int os02g10_init_controls(struct os02g10 *os02g10) { - const struct os02g10_mode *mode =3D &supported_modes[0]; struct v4l2_fwnode_device_properties props; - u64 vblank_def, exp_max, pixel_rate; struct v4l2_ctrl_handler *ctrl_hdlr; + u64 exp_max, pixel_rate; int ret; =20 ctrl_hdlr =3D &os02g10->handler; @@ -384,18 +369,19 @@ static int os02g10_init_controls(struct os02g10 *os02= g10) if (os02g10->link_freq) os02g10->link_freq->flags |=3D V4L2_CTRL_FLAG_READ_ONLY; =20 - vblank_def =3D mode->vts_def - mode->height; os02g10->vblank =3D v4l2_ctrl_new_std(ctrl_hdlr, &os02g10_ctrl_ops, - V4L2_CID_VBLANK, vblank_def, - OS02G10_FRAME_LENGTH_MAX - mode->height, - 1, vblank_def); + V4L2_CID_VBLANK, OS02G10_VBLANK_MIN, + OS02G10_FRAME_LENGTH_MAX - + os02g10_active_area.height, + 1, OS02G10_VBLANK_DEF); =20 - exp_max =3D mode->vts_def - OS02G10_EXPOSURE_MARGIN; + exp_max =3D OS02G10_VBLANK_DEF + os02g10_active_area.height + - OS02G10_EXPOSURE_MARGIN; os02g10->exposure =3D v4l2_ctrl_new_std(ctrl_hdlr, &os02g10_ctrl_ops, V4L2_CID_EXPOSURE, OS02G10_EXPOSURE_MIN, exp_max, - OS02G10_EXPOSURE_STEP, mode->exp_def); + OS02G10_EXPOSURE_STEP, OS02G10_EXPOSURE_DEF); =20 v4l2_ctrl_new_std(ctrl_hdlr, &os02g10_ctrl_ops, V4L2_CID_ANALOGUE_GAIN, OS02G10_ANALOG_GAIN_MIN, @@ -445,20 +431,18 @@ static int os02g10_set_framefmt(struct os02g10 *os02g= 10, struct v4l2_subdev_state *state) { const struct v4l2_mbus_framefmt *format; - const struct os02g10_mode *mode; + const struct v4l2_rect *crop; int ret =3D 0; =20 + crop =3D v4l2_subdev_state_get_crop(state, 0); format =3D v4l2_subdev_state_get_format(state, 0); - mode =3D v4l2_find_nearest_size(supported_modes, - ARRAY_SIZE(supported_modes), width, - height, format->width, format->height); =20 - cci_write(os02g10->cci, OS02G10_REG_V_START, mode->y_start, &ret); - cci_write(os02g10->cci, OS02G10_REG_V_SIZE, mode->height, &ret); - cci_write(os02g10->cci, OS02G10_REG_V_SIZE_MIPI, mode->height, &ret); - cci_write(os02g10->cci, OS02G10_REG_H_START, mode->x_start, &ret); - cci_write(os02g10->cci, OS02G10_REG_H_SIZE, mode->width, &ret); - cci_write(os02g10->cci, OS02G10_REG_H_SIZE_MIPI, mode->width, &ret); + cci_write(os02g10->cci, OS02G10_REG_V_START, crop->top, &ret); + cci_write(os02g10->cci, OS02G10_REG_V_SIZE, crop->height, &ret); + cci_write(os02g10->cci, OS02G10_REG_V_SIZE_MIPI, format->height, &ret); + cci_write(os02g10->cci, OS02G10_REG_H_START, crop->left, &ret); + cci_write(os02g10->cci, OS02G10_REG_H_SIZE, crop->width, &ret); + cci_write(os02g10->cci, OS02G10_REG_H_SIZE_MIPI, format->width, &ret); =20 return ret; } @@ -528,16 +512,67 @@ static int os02g10_disable_streams(struct v4l2_subdev= *sd, return ret; } =20 +static int os02g10_set_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_selection *sel) +{ + struct v4l2_mbus_framefmt *format; + struct v4l2_rect *crop; + struct v4l2_rect rect; + + if (sel->target !=3D V4L2_SEL_TGT_CROP) + return -EINVAL; + + rect.left =3D clamp_t(unsigned int, ALIGN(sel->r.left, 2), + os02g10_active_area.left, + os02g10_active_area.left + + os02g10_active_area.width - + OS02G10_WINDOW_WIDTH_MIN); + rect.top =3D clamp_t(unsigned int, ALIGN(sel->r.top, 2), + os02g10_active_area.top, + os02g10_active_area.top + + os02g10_active_area.height - + OS02G10_WINDOW_HEIGHT_MIN); + rect.width =3D clamp_t(unsigned int, ALIGN(sel->r.width, 2), + OS02G10_WINDOW_WIDTH_MIN, + os02g10_active_area.width); + rect.height =3D clamp_t(unsigned int, ALIGN(sel->r.height, 2), + OS02G10_WINDOW_HEIGHT_MIN, + os02g10_active_area.height); + + rect.width =3D min_t(unsigned int, rect.width, + os02g10_active_area.left + + os02g10_active_area.width - rect.left); + rect.height =3D min_t(unsigned int, rect.height, + os02g10_active_area.top + + os02g10_active_area.height - rect.top); + + crop =3D v4l2_subdev_state_get_crop(sd_state, sel->pad); + + if (rect.width !=3D crop->width || rect.height !=3D crop->height) { + format =3D v4l2_subdev_state_get_format(sd_state, sel->pad); + format->width =3D rect.width; + format->height =3D rect.height; + } + + *crop =3D rect; + sel->r =3D rect; + + return 0; +} + static int os02g10_get_selection(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_selection *sel) { switch (sel->target) { + case V4L2_SEL_TGT_CROP: + sel->r =3D *v4l2_subdev_state_get_crop(sd_state, sel->pad); + return 0; case V4L2_SEL_TGT_CROP_BOUNDS: case V4L2_SEL_TGT_NATIVE_SIZE: sel->r =3D os02g10_native_area; return 0; - case V4L2_SEL_TGT_CROP: case V4L2_SEL_TGT_CROP_DEFAULT: sel->r =3D os02g10_active_area; return 0; @@ -566,16 +601,16 @@ static int os02g10_enum_frame_size(struct v4l2_subdev= *sd, { struct os02g10 *os02g10 =3D to_os02g10(sd); =20 - if (fse->index >=3D ARRAY_SIZE(supported_modes)) + if (fse->index) return -EINVAL; =20 if (fse->code !=3D os02g10_get_format_code(os02g10)) return -EINVAL; =20 - fse->min_width =3D supported_modes[fse->index].width; - fse->max_width =3D fse->min_width; - fse->min_height =3D supported_modes[fse->index].height; - fse->max_height =3D fse->min_height; + fse->min_width =3D OS02G10_WINDOW_WIDTH_MIN; + fse->max_width =3D os02g10_active_area.width; + fse->min_height =3D OS02G10_WINDOW_HEIGHT_MIN; + fse->max_height =3D os02g10_active_area.height; =20 return 0; } @@ -586,18 +621,14 @@ static int os02g10_set_pad_format(struct v4l2_subdev = *sd, { struct os02g10 *os02g10 =3D to_os02g10(sd); struct v4l2_mbus_framefmt *format; - const struct os02g10_mode *mode; + struct v4l2_rect *crop; =20 + crop =3D v4l2_subdev_state_get_crop(sd_state, 0); format =3D v4l2_subdev_state_get_format(sd_state, 0); =20 - mode =3D v4l2_find_nearest_size(supported_modes, - ARRAY_SIZE(supported_modes), - width, height, - fmt->format.width, fmt->format.height); - fmt->format.code =3D os02g10_get_format_code(os02g10); - fmt->format.width =3D mode->width; - fmt->format.height =3D mode->height; + fmt->format.width =3D crop->width; + fmt->format.height =3D crop->height; fmt->format.field =3D V4L2_FIELD_NONE; fmt->format.colorspace =3D V4L2_COLORSPACE_RAW; fmt->format.quantization =3D V4L2_QUANTIZATION_FULL_RANGE; @@ -606,11 +637,19 @@ static int os02g10_set_pad_format(struct v4l2_subdev = *sd, *format =3D fmt->format; =20 if (fmt->which =3D=3D V4L2_SUBDEV_FORMAT_ACTIVE) { - u32 vblank_def =3D mode->vts_def - mode->height; + int ret, vblank; =20 - int ret =3D __v4l2_ctrl_modify_range(os02g10->vblank, vblank_def, - OS02G10_FRAME_LENGTH_MAX - - mode->height, 1, vblank_def); + ret =3D __v4l2_ctrl_modify_range(os02g10->vblank, OS02G10_VBLANK_MIN, + OS02G10_FRAME_LENGTH_MAX - + fmt->format.height, 1, + OS02G10_VBLANK_DEF); + if (ret) + return ret; + + /* Set VBLANK to maintain 30 fps for the selected format. */ + vblank =3D os02g10_active_area.height - fmt->format.height + + OS02G10_VBLANK_DEF; + ret =3D __v4l2_ctrl_s_ctrl(os02g10->vblank, vblank); if (ret) return ret; } @@ -626,14 +665,14 @@ static int os02g10_init_state(struct v4l2_subdev *sd, .which =3D V4L2_SUBDEV_FORMAT_TRY, .format =3D { .code =3D os02g10_get_format_code(os02g10), - .width =3D supported_modes[0].width, - .height =3D supported_modes[0].height, + .width =3D os02g10_active_area.width, + .height =3D os02g10_active_area.height, }, }; + struct v4l2_rect *crop =3D v4l2_subdev_state_get_crop(state, 0); + *crop =3D os02g10_active_area; =20 - os02g10_set_pad_format(sd, state, &fmt); - - return 0; + return os02g10_set_pad_format(sd, state, &fmt); } =20 static const struct v4l2_subdev_video_ops os02g10_video_ops =3D { @@ -645,6 +684,7 @@ static const struct v4l2_subdev_pad_ops os02g10_pad_ops= =3D { .get_fmt =3D v4l2_subdev_get_fmt, .set_fmt =3D os02g10_set_pad_format, .get_selection =3D os02g10_get_selection, + .set_selection =3D os02g10_set_selection, .enum_frame_size =3D os02g10_enum_frame_size, .enable_streams =3D os02g10_enable_streams, .disable_streams =3D os02g10_disable_streams, --=20 2.34.1