From nobody Tue Jun 16 19:33:18 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012062.outbound.protection.outlook.com [52.101.43.62]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95D4638758E for ; Fri, 24 Apr 2026 09:22:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.62 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777022558; cv=fail; b=YcTYVcaZK88z3VU96pqchU/r1FtL1fLS72yY7Y/v2aLXfL5PaUefjodJT3X8I1KxpnQ5w3n0Skc+9NtwTqDKmImeECsTVct6Ib/Kj+OtNcVkNMAtY/QF8AevCBuDFqL8iG5UeB0IbRl2w+m0YlzDls9TVV3uoE9DxToW1Jq7cVQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777022558; c=relaxed/simple; bh=+r+Tm1/KbXETD5mSdYWAZ32sbDQOrd1NFKSxRfYhOvQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=oxt+vx4SgbPlhpZuQ/GoaMi8RAQm0tijsYoycD9ffFWCmRWAhVgtZ7hrHxnuElTuqbyiR349AM4GLbNRwoztnZwmyFdirmfu4g9SWJAZGlyJLeQJT8I4t8GG6CcCIacSg+mq7j3MGpmFO2QMUNqTyM4JBidAd9Bg77TWNSeCgiw= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=jg6KZJ8x; arc=fail smtp.client-ip=52.101.43.62 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="jg6KZJ8x" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=fe/A++MjZHP4vMr2CrUY52yUCO+1M3tVH90y4x3Lu39jiXr6ZKnB2l/uRk2vsmfac0u4TDkKGmEW8st94KZJkpH+my7ARQdAgZiNuStGl3KMkaF0sgCjt6kFNU5ItxPKM0X+Nr1mzv8HQBUBaPa/nrhQcjoILv9nafvaLTZ24+kDZLoHO5nh3oxCsdX+YWXTBnlLEClerGq0fPv7l99bfCRe+76xurBKWO6rHr1k8d6U7zh7mKDQnLWrRJ971HtxPK741O4uDlNXQBZdkcLEW03bze/LYyXDrTXaJ+NhGkaIKw6GeHbtkGzGPRtTpOarS/WT8oA70HJWBnJiwNZnIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=lZTjZF+x0WUc1Mwuii6WsteW2lRfCrI+wxIKJzE9ZeY=; b=NeH6LkFIT0UO0rAW2rEpzx6b2ggsqN3nl90K4H7rVTBW+1TG9SiyUNR76ry8KvXWSH9xrfTbrDcWjkRriM/1IejNpb5wO3CgaYvCrbrLMmj5l48umhok//kv0k/mv5ZnwZ/a2JeOm/KNlqay1+ye5ks0izAZRFrCH7FhMEp0oiM312ScTEd2cbDEFfnQBQqwfhQbPezAVFM/gZZMtOUgfMpXQ5DmIKYusUMdcZS5n+cS868TOO/gDrp2nrW6hfh+e1zy81f9RYfiubIdTWaP6xbtt6/Js8pR33WcFnwvHXr2q65Yojn7h31CbpYAeiLTCbSTTEWHbT3yzB+dePHi0g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=lZTjZF+x0WUc1Mwuii6WsteW2lRfCrI+wxIKJzE9ZeY=; b=jg6KZJ8xzkss1mS/zGY56Cma7bucb4CyLXeqZ2DKr83n+Ql4YVkWmaNQ/IplwiNvqcYKUxgKLOnJv3AWAwutzhl1snIfam+G7Gcy7KwXqNa7cXUwpHPu2TAJs1iXpyoO2rpyaTGPrf03O1sqT8VUfjnIGWrfVus6nMNbL4zGx90= Received: from CY5P221CA0123.NAMP221.PROD.OUTLOOK.COM (2603:10b6:930:1f::18) by MW3PR12MB4442.namprd12.prod.outlook.com (2603:10b6:303:55::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.22; Fri, 24 Apr 2026 09:22:34 +0000 Received: from CH2PEPF00000099.namprd02.prod.outlook.com (2603:10b6:930:1f:cafe::c5) by CY5P221CA0123.outlook.office365.com (2603:10b6:930:1f::18) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9846.22 via Frontend Transport; Fri, 24 Apr 2026 09:22:33 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CH2PEPF00000099.mail.protection.outlook.com (10.167.244.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.18 via Frontend Transport; Fri, 24 Apr 2026 09:22:33 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 24 Apr 2026 04:22:30 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 1/4] iommu/amd: Drop unused global exclusion range fields and init Date: Fri, 24 Apr 2026 09:22:10 +0000 Message-ID: <20260424092213.16976-2-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260424092213.16976-1-suravee.suthikulpanit@amd.com> References: <20260424092213.16976-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000099:EE_|MW3PR12MB4442:EE_ X-MS-Office365-Filtering-Correlation-Id: 3300fca7-dd9d-4b57-014d-08dea1e3045f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700016|18002099003|22082099003|56012099003; X-Microsoft-Antispam-Message-Info: iQLi7a5YXfq0qiodz2Qwy+qmpTzSnyN+b6hKi/D4AL7wDRq9n16fP7p8mMUfrnPL9iH6SdTaP6vqprEn/WUya5ToxdYICroYkodN9VwnY3IDybpk3c5s3Pw2qfLQmF4ZlL91lg++JAebhUp7qkf1LIo20yUqf+SeH7Q/CcHbqfG+rMx6plJ2PkUYl7Js5Xs4Khz+mJMw4CN17jS0wID8mvH3n4YUsR+eRrCSsJQYhdTlXjWEumP6t1K6a5H3zBxt8Nql+7aeuVoJVqxzWfsQ1QlPZNckKRAodyAB9m089bvC/y3EZnYhqoegflQvNUhuF29scXTgZ1R+mra2PpPzBh+PZkfO59gdG8E/ZFGVHtI0Cr2t403B3CHQeR+ZidLnz+TTcPpbq3QRy/orE/jlREFJocxU5tDqxba7Aj3LpoVEf7mm9Aja4zToaL+TScUSXkCoOE9ZNaSaiRr8JmCaJLxlFcJ2VDv6AcPZxZgQ6KeKsRVHKJQ3RIh/oWyRRDAXDPVNluMlvPg9eMqfdktTXhR5aY52mt/1kWjh4IQrl7U3Mbh7h48PTRET4Q1oS7R95nxeo78zttqzLZwGGigRiw6woDw3969TX2DYclbem3N0VCssUMkeVnnAq9t3F2JtatYqAkY0XKO6/q1fH1cYCUMslHOAviGeZmuKJITgrAMwz4lRW1jZs41bknLjMAnfjdhmhmIerstsEplTPVPcEoSq8IpHXPGbMjdN9kGmN4nfsRfsbSmIXkpaHehBSUunRkaLRZ58VnPATkp19BT6jg== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(82310400026)(36860700016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Kba726Tib4wisN3tfWTzPxraVHJY489H33Od2hg4x6vpZ71beGjIRKWTY8KoCzV6UBjxp3nvSDTl7k3qP5FUHdIP0NVwjmKOwbSBzKSGG3EmoKnhrfuhGwQrLPpLzb/UNqywh3U2cahY9X6E2Hsmh9HdIUIY6ew+dDtYNkB7PKN0sOjIqh1f1gmkEGs/NXxWKogMt/JhqPFNVuat6YrIY4VYuhH6v2fiUITWf8Hqi/32UUpcmBv3mcQk6W1tKqMC1PzNjbwWgtXQFkuhnW4Dq0GZhYcW7RaeNRm3832DuM8AGPKAZfx970CdbLWd84hWTZDJTrNGfA6RS/2KYHXKRG9notrLYy5moKlwoxDOJLlGR9pVW1+h2pvPuLmTwWnqZ6YOto6qSxkcawCpO8C9rnQ6usVXmgu0yQVOv5uRUcv6CHRbF9E7/K4KrwYgk9VW X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2026 09:22:33.5620 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3300fca7-dd9d-4b57-014d-08dea1e3045f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000099.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4442 Content-Type: text/plain; charset="utf-8" Remove unused struct amd_iommu.exclusion_start/exclusion_length, the MMIO_EXCL_* flag masks, and iommu_set_exclusion_range(). These struct amd_iommu fields were never assigned, so early_enable_iommu() never programmed the hardware exclusion registers through this path. Please note that the exclusion range registers have been repurposed to SNP completion-wait store base / limit registers. So, rename MMIO_EXCL_BASE/LIMIT via to MMIO_COMPL_STORE_BASE/LIMIT instead. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 4 ++-- drivers/iommu/amd/init.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index a481d8cbd053..6b0f1b05aa47 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -55,8 +55,8 @@ #define MMIO_CMD_BUF_OFFSET 0x0008 #define MMIO_EVT_BUF_OFFSET 0x0010 #define MMIO_CONTROL_OFFSET 0x0018 -#define MMIO_EXCL_BASE_OFFSET 0x0020 -#define MMIO_EXCL_LIMIT_OFFSET 0x0028 +#define MMIO_COMPL_STORE_BASE_OFFSET 0x0020 +#define MMIO_COMPL_STORE_LIMIT_OFFSET 0x0028 #define MMIO_EXT_FEATURES 0x0030 #define MMIO_PPR_LOG_OFFSET 0x0038 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index a33bf3f5ed8a..866249d3673e 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -364,14 +364,14 @@ static void iommu_set_cwwb_range(struct amd_iommu *io= mmu) * Re-purpose Exclusion base/limit registers for Completion wait * write-back base/limit. */ - memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, + memcpy_toio(iommu->mmio_base + MMIO_COMPL_STORE_BASE_OFFSET, &entry, sizeof(entry)); =20 /* Note: * Default to 4 Kbytes, which can be specified by setting base * address equal to the limit address. */ - memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, + memcpy_toio(iommu->mmio_base + MMIO_COMPL_STORE_LIMIT_OFFSET, &entry, sizeof(entry)); } =20 @@ -991,7 +991,7 @@ static int __init remap_or_alloc_cwwb_sem(struct amd_io= mmu *iommu) * completion wait buffer (CWB) address. Read and re-use it. */ pr_info_once("Re-using CWB buffers from the previous kernel\n"); - paddr =3D readq(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET) & PM_ADDR_MASK; + paddr =3D readq(iommu->mmio_base + MMIO_COMPL_STORE_BASE_OFFSET) & PM_AD= DR_MASK; iommu->cmd_sem =3D iommu_memremap(paddr, PAGE_SIZE); if (!iommu->cmd_sem) return -ENOMEM; --=20 2.34.1 From nobody Tue Jun 16 19:33:18 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011020.outbound.protection.outlook.com [40.107.208.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07BEA3890F3 for ; Fri, 24 Apr 2026 09:22:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.20 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777022562; cv=fail; b=s7W6gG6Kf+wKnGm7EN4n3rCT8ukjScW6ESWqM4art2g+7tMtUuknsoGfCIAD7KNGub8M5B4lICIaAH2ZERIwIW2BIGsqFCRMd7ljzLoXE0WAvZERKeqR1fO/yVKAIkojj1QvNxmBflCNhaJ1MX8pZmmlqBO85unTpMyp7dCQzyg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777022562; c=relaxed/simple; bh=nkd5OYF/QkQBhwi3MeYWTrFetKxKFMmnZ0VJU1vR3+c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Fb0ol8vMoGEKA9FSHAb+f8SEeFqjI05POCDvR9IxqTePAoqvDaVURDVoFQAgk9326U6ATOPVlOg1W7r051EZmVXaTW5IoPRCP/PbJIymoALS88kPHDizDIZSfvo+8XIyF2+aTLP79Luadrjbad1g/hC1E+R8G6VzVW04uFbo/Bs= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=sbsa74i5; arc=fail smtp.client-ip=40.107.208.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="sbsa74i5" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=tNNdkoHm8OzVLAUUPDc0RMUxaV0qpRtwsoWrvwwSBQc5Pj8/dg/wuVFubsX6yd1zF9Ekz9RmHvyF/Uwto2Z7VAw3f6UfvN9MyQX34V1etuoxWFRavapyKetjA9WMj4SAxJoRfPaJGm2o0RaveuusUVulQfx4J2pH5v6TT7TvcSvpLM2r3d6edezWy9L4JWKIfNuTJWSMT3rkYrFIzP7yTQzYVny9wwbfE74hWOdTun4rAY4A7XYOs9lMINllT+mAV5P+aO0Y4V3WGg1Q5MHooC1H+Om0xNb+XeZ+1WtHpcMpuJyKaz6xJ2pHncvHj04RQA0AqA0wkyEIz2ZHtWAZsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=grtqdo6j2oEGUG6Ox9hRhExlOz9WmP8G/ErkHCBabds=; b=mhvYRCTXAJwJMOM7tUS2gDxbefQvrLkWnP86waEBfvmJvqV8Ptt4X2LHnPBMVGxBTxwy5pfrAiZ3AP7xtNrnxZ1qCXKNwzYyG8dmADvQaV+LjJEEFz6FEIQO+omYNhKeJJon1zyboVUDm93+8sPMEMu5pP7+iz0HGWpqavX63CJpYtFs0cJVWOgx3H+IzwwkyIWKjy33dfWugofiernDA9GOOvM9QkvzcKj66ybNRZmMmegjVborAKdzSse7lChUzAesMTWoTFpuqRf8xRC7KUE2BdUVM5OwNX//WVVhhDvrVNUVlEw1Zry6PmfAhhAwadvurVBFH2zHudYbv8HNxQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=grtqdo6j2oEGUG6Ox9hRhExlOz9WmP8G/ErkHCBabds=; b=sbsa74i5udDGM3PrYpx+sEvcIa4PdIFvwCRA1N7ye6b780Fvjb8Kb1p3Y//7xY1DLBSx+84GB/JgrhV2bfFZ6QpWN7FQHrvk+paEN9+qGYSaVYVICTFLfqf1yfLuCVRNx3uOddVc4fBMzLpBvxP0TcXWo8CH8AMYZuT2frI4FDY= Received: from CH0PR03CA0097.namprd03.prod.outlook.com (2603:10b6:610:cd::12) by SJ2PR12MB7894.namprd12.prod.outlook.com (2603:10b6:a03:4c6::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.22; Fri, 24 Apr 2026 09:22:37 +0000 Received: from CH2PEPF0000009E.namprd02.prod.outlook.com (2603:10b6:610:cd:cafe::dd) by CH0PR03CA0097.outlook.office365.com (2603:10b6:610:cd::12) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9846.23 via Frontend Transport; Fri, 24 Apr 2026 09:22:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CH2PEPF0000009E.mail.protection.outlook.com (10.167.244.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.18 via Frontend Transport; Fri, 24 Apr 2026 09:22:36 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 24 Apr 2026 04:22:33 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , Suravee Suthikulpanit , Baoquan He , Adrian Huang , Jerry Snitselaar Subject: [PATCH v2 2/4] iommu/amd: Do not convert IVMD exclusion range to unity range Date: Fri, 24 Apr 2026 09:22:11 +0000 Message-ID: <20260424092213.16976-3-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260424092213.16976-1-suravee.suthikulpanit@amd.com> References: <20260424092213.16976-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009E:EE_|SJ2PR12MB7894:EE_ X-MS-Office365-Filtering-Correlation-Id: 0d7c354f-38c0-437b-fa62-08dea1e30660 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|22082099003|18002099003|56012099003; X-Microsoft-Antispam-Message-Info: W3NZfA1PXMUKnLs3YhLD6KO5zj8gsSw2/BPIATVwjV7v58gDeRoIa/1M+WGdv42+zsPqmnCH6wATL4c/wrsQcalEiP3leuO3JG+ZHkdoWSRCajWGE4iWke+uhECT2JKUvKI+ntdHtGQFtxpajXQV/IfXlJW6etvJmbPANZ/QCReJIHZZ2+q8t3gnozIHmGFKLCMsThcJVWZ+Kjk6IXmrXRz58pJqBmpeKQm5oDVPf4TGW22ZRlUjbVNbwEjI23LHtoVGtKpkhtV1HaTSqU9Up7S3C95XaKZoDuPPo1AOQ+VQ7ZSxpW7Zo1yOuM/GsLQFAh74PazdiLrV/P6XHmUHJ07QzgSqQYhnXWM6RwLxaDwMJ1PCFuh9+Y2J+BIhIsSFIDsxIwfgyMi9LCBxdHFGgdj8+WxH4iLA/haYN2/giAsVFqcKQjpWpxcBGALw/WEwukctqs07+R5UaEjXhqpmlC9kW+gBbNjx+0qiJrrMcv6+02yUBO9K363ZN+p/TOIyRbgcqisypTdOsaRPyMIbm6fsKWyJtE41PV6ZI5+oD1n2dPqLISKgGpN/6wf/eeUbf02LeV70bd9kGJYdBPOl/i8nNr0vTt1qBcWloYUmSNxSNpHGll9W4wb1aEVCEx8Rn2fe1baxSvgAiTPnwoeRIQ3elFC6mkoUtWD2K/ah4lRGUGZ808WIZdAJ0nWCYPfJbZhyhnpsQA16pub506E1Msi8TnFdKVElMYH3wcVAAt0fMxoll9OnV/sQKY5zonXUjrZbmk7faM5e6e4MivvTWA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 6+BcF3gg8fUd/xWhXLWOKG7nYRS2zwabN0mtsI/DrEuwLp+yPSqg/MmWC1cU9o8zPsj7Fk7t7MgWcPJwr2yrkSt26iX9Wd2kRlAto9keRM7/nan7MGNjotgLB14ZCT+DB0awfVmCTYOFYIBMFnofdZWkY2ob0DUsymHsnRgZi2YHOCr5yHBCKW0LQgGD5OWvgOGhbMM2IX0HwjRfRqfa4qMP9sYLC9vqcn94S99VkDQ1YGyeCS5oPDQ0EicBYIrzROoChKySPY+hl3PVuInhtf+fYBbEYj+QxpGsCvWxkOtpGuMLyoPtFbHs75y0DonNAxOSORBRHxKS5ABtmnSfWtMeec+YzHqhT13WeqFO2pGG6QpNsnzSexOohMrQZEO7Ian9W3/DRfXDc0wGrsOen/Nx3X4WWZbCEyAmjSvHFm61HDK5kv67bSiBwbP+p1SD X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2026 09:22:36.9549 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0d7c354f-38c0-437b-fa62-08dea1e30660 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB7894 Content-Type: text/plain; charset="utf-8" Original problem was there could be multiple IVMD exclusion entries conflicting over a single exclusion range supported in older Linux kernel. The fix was first introduced in commit 387caf0b759a ("iommu/amd: Treat per-device exclusion ranges as r/w unity-mapped regions") and in commit 0bbe4ced53e3 ("iommu/amd: Fix the overwritten field in IVMD header") , where IVMD exclusions are converted to separate unity_map_entry objects in pci_seg->unity_map so amd_iommu_get_resv_regions() treated every such entry as IOMMU_RESV_DIRECT with R/W. Since the AMD IOMMU driver no longer support the Exclusion Range base/limit registers and rely on Linux kernel to exclude the specified IOVA ranges from being mapped this logic is no longer needed. Remove the special case that forced e->prot to RW-UNITY mapping (i.e. IVMD_FLAG_IW | IVMD_FLAG_IR | IVMD_FLAG_UNITY) whenever IVMD_FLAG_EXCL_RANGE was set. Fixes: 0bbe4ced53e3 ("iommu/amd: Fix the overwritten field in IVMD header") Cc: Baoquan He Cc: Adrian Huang Cc: Jerry Snitselaar Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/init.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 866249d3673e..2e854f4639a7 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -2644,16 +2644,6 @@ static int __init init_unity_map_range(struct ivmd_h= eader *m, e->address_end =3D e->address_start + PAGE_ALIGN(m->range_length); e->prot =3D m->flags >> 1; =20 - /* - * Treat per-device exclusion ranges as r/w unity-mapped regions - * since some buggy BIOSes might lead to the overwritten exclusion - * range (exclusion_start and exclusion_length members). This - * happens when there are multiple exclusion ranges (IVMD entries) - * defined in ACPI table. - */ - if (m->flags & IVMD_FLAG_EXCL_RANGE) - e->prot =3D (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1; - DUMP_printk("%s devid_start: %04x:%02x:%02x.%x devid_end: " "%04x:%02x:%02x.%x range_start: %016llx range_end: %016llx" " flags: %x\n", s, m->pci_seg, --=20 2.34.1 From nobody Tue Jun 16 19:33:18 2026 Received: from SJ2PR03CU001.outbound.protection.outlook.com (mail-westusazon11012041.outbound.protection.outlook.com [52.101.43.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E2AB386C24 for ; Fri, 24 Apr 2026 09:22:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.43.41 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777022567; cv=fail; b=Ky7Js69Q9wk9nbXn6i6s7TsxdmWocmvKtqcfcu32QcXf1I95mqUjll4WGAqod2j0iXxj+SJZXy2byuOJjgjC3bfTPjNP3lkobDJmyaly2yXV6vTs0NaBYaX9jLYjyeoiQjZUrCycjmIn8AUsiyWQB6IiVLD545BqmAwyGYYo5WQ= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777022567; c=relaxed/simple; bh=746XmB8CmIZ++YebW02kQX5o6zMQtXIkr90UD+aFeas=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=AOrWZGriuCj/jAL0vNXRCxgwG41U6cNKvcmAMKeLC477s8AHLyVhNV25+zTK7K8F3MxnJ5Kj2crYnVKYc60r9tMfFcZgiP/lVEAdlTAh6dmyan9EjEx4YI9xGB1hGhQYJS840pQT2YJD+OZR4lFrxzEkDAJf29JSArOP3SOOS+I= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=au8/AOU5; arc=fail smtp.client-ip=52.101.43.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="au8/AOU5" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=I378fvGiIDF+fx1HtRW1u57nOTtrW07npXVs5IDIOY/ixRzi7f2RlQ3YE/orwCVj7nsz8zkt2T+biuRGxaGJg6RXJyPbdNLlGNIf89CZZeD8b6d9sXs0G2ZLVmGYH16nXuXclvS4wdrQ7Sj9W4SpBzOIiCYmNt7Zbbzk5NOP8XR5KNrqHBOOasfn7UlofK5PIS2YIV25fmoV4pPYU4kTO5fAw9RAv+QuJ4DRgT5kz6roUCqD5Im8JZSvESeHQOhiTTCdpuDsb8arWtXQ+GdUCT05V+hF6xGelWNa32rGAvhfr6DZiB+4ZJbX5ro+Rf1tAqEESFOJ8c6qocz6ug2Hgg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=A/UNKhfy7w6O9rv1E3a+qsyCXt4GvTPBuLnJB0w6UDM=; b=OYZ/VOfgmCGh73mOoc2d2olOj8rp9N0tDNjILhGelChK0FEftRFgF+UVXSSW2QBmdMtBpBZq29wnavZD7dX88gKL3b4VQ6y7F1n+2tbO2N86VL0I53qRrLeNrVUcbeifV+UE+qSsMCpesykNSuc4zDYwPchzaYa8OsAYapYWD+CkPK2FpxxA29vqyYMp1zU5eLlkaXlzeVykakBzP3iN+BNFtqKkDnxQ6VjWUkE6Fqy7Ehlb63L4D0WPjIToRHdmsswGiC8Di1HrWjCG/7FcSna9SRWFBjHExUcqnBEJpsC8WjteMVO2tmayGd3qHuj57ne5j01tCZPNp1LnLTkzWQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=A/UNKhfy7w6O9rv1E3a+qsyCXt4GvTPBuLnJB0w6UDM=; b=au8/AOU5zQ9qj+vVh/kCZ6wpxC3LcpEA8LZQeC8i/+gvTFrhHCen/X+8MpMyOMGYgNsBuErNfS/42GpXQoB3kkbBYVrEYmMYmBStQz4vlXvUmHFdZXPYEsUONi0A5wtHnylUaDrVEim7wGL0DUlVOh/SL91k8GhgBDvQYzXxpo0= Received: from CH0PR03CA0432.namprd03.prod.outlook.com (2603:10b6:610:10e::20) by SJ0PR12MB5664.namprd12.prod.outlook.com (2603:10b6:a03:42b::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.21; Fri, 24 Apr 2026 09:22:41 +0000 Received: from CH2PEPF0000009C.namprd02.prod.outlook.com (2603:10b6:610:10e:cafe::be) by CH0PR03CA0432.outlook.office365.com (2603:10b6:610:10e::20) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9846.22 via Frontend Transport; Fri, 24 Apr 2026 09:22:40 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CH2PEPF0000009C.mail.protection.outlook.com (10.167.244.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.18 via Frontend Transport; Fri, 24 Apr 2026 09:22:40 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 24 Apr 2026 04:22:36 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 3/4] iommu/amd: Clean up and simplify IVMD entry handling Date: Fri, 24 Apr 2026 09:22:12 +0000 Message-ID: <20260424092213.16976-4-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260424092213.16976-1-suravee.suthikulpanit@amd.com> References: <20260424092213.16976-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009C:EE_|SJ0PR12MB5664:EE_ X-MS-Office365-Filtering-Correlation-Id: 56cd7ec5-ded0-46f7-ce21-08dea1e30880 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|1800799024|82310400026|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: RndLC0jxfeyPm4au7rcVCyfO4MqMhqlkrDGqnZ8Dy+a13bBEpuakrOso3PixnNk7y3T2JmtfV+8wnlH8YV/Lho6YlJY2ja6uINr7+gJafufeE7akT6G47R0OSrV91QGM/QKx9GhQHcuU8YRzbh+nk+8ADNLAyYxEliEh6+nmWoxcxS7YlrfqzqGUDdycGKE0XKyKBKG0uasbpY+UgGh18Ycjk12wN/nDKBtyMO7qZI0fkCdljKVIUxHVRgJr9qpQlUgIcr4Fr6kM4SYkM9Ii/LxMUFf7aDo+RDnXfoH+mFo9Hs/JPbr4YvwthMG8DbnXql1VDWfUXfklq8vdSMBYWQZe4qeiX0IvCdeg/+DEYHdFf9p1AkNszWOj1CX/U0rtLoNrqihZyvXqaT+VJjvNvkZUhreloAjrUuTcwaYWRyW6qRkKryIvZItOZsrGQlfY1ZCKvU1JscmY7IKu6jzIcBIWAOe3ekly40ZfQnjeE/UxIo1YSYgZRoJ74Jslr8eFmsqEV32ft10uepdt3Wo0hESK6xCQHvGFD60dlBBdKJyZrKyPL/0OjMtaM31O1qJF1F6OzTZv1Z3jySoBhSfnoXdwcBIWVzczgGcApk9MJSoahJmNiKiOAbE6qb4xihE2cMWnebMRPpj+0AxvrETdTG7ZSAE91r7/6vFwPiga5/vwzxwcwGUcOsuENffV5KFBZKuPEOhoCpriy/eUpUppvusNhx6WzTvdaQBlxA8GlP7vIC7hQcXwMYfVWTBx5Ax8EfK2NEDVG+Mg+pBuxSIe/A== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(376014)(1800799024)(82310400026)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: os1a4TowmK2EwMdnzU7Xn9KNvyXAcjU7TS1QTraZlAJ/X5IYl6K9wjNbq2JOg95LLlf/TWaoDL+MinrVKW4eW80eT3oQ49zHkkXbUTZPU3i+GxDkHCYZOh59WqDD9b9vKafU24xw6bb3P5kdYek8EzWxGZ8JuYhzZ66IQ5stQDCpHUFJmgOVYRhBkH+awkDBL0SQhkWiI1Vsp9Up8JaRPrng70qJUJBcRZTyAnnfNArOEIWqX1tCDBwtbu3HW9XgxnC3LSWHX9UZOtYfOD6yW/1ZbWL4Z2NtUqi8c5I4uI92ZHwdwGRJeAzd8RloqvqY+ohNTKWvzU+eEfliTSGGpYWwfH1QlPI4OiOv/Ml+XX83rMb8EvWDULBvHh9OyLldt/jm8REH7nO8s4mkth6JVuVOCxIPQgf5ph5ixFCZ6NcQ3edukBLPOaYUzWKveyKl X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2026 09:22:40.4960 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 56cd7ec5-ded0-46f7-ce21-08dea1e30880 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5664 Content-Type: text/plain; charset="utf-8" Clean up IVMD ACPI flags and mask in amd_iommu_types.h, and drop the IOMMU_PROT_* / IOMMU_UNITY_MAP_FLAG_EXCL_RANGE, which only existed to carry IVMD semantics. Rename unity_map_entry and unity_map to ivmd_entry and ivmd_entry_map, store the raw IVMD flags byte from the ACPI table instead of shifting protection into a separate int, and derive IOMMU reserved regions from those flags in amd_iommu_get_resv_regions(). Also, rename struct list_head unity_map to ivmd_entry_map along with renaming the unity-map helper functions. Lastyly, add error message when handling invalid IVMD entry. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 18 +++++++------ drivers/iommu/amd/init.c | 39 +++++++++++++---------------- drivers/iommu/amd/iommu.c | 27 ++++++++++++++++---- 3 files changed, 49 insertions(+), 35 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 6b0f1b05aa47..9321b7cc200b 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -375,9 +375,11 @@ /* DTE[128:179] | DTE[184:191] */ #define DTE_DATA2_INTR_MASK ~GENMASK_ULL(55, 52) =20 -#define IOMMU_PROT_MASK 0x03 -#define IOMMU_PROT_IR 0x01 -#define IOMMU_PROT_IW 0x02 +#define IVMD_FLAG_UNITY BIT(0) +#define IVMD_FLAG_IR BIT(1) +#define IVMD_FLAG_IW BIT(2) +#define IVMD_FLAG_EXCL BIT(3) +#define IVMD_FLAG_MASK GENMASK_U32(3, 0) =20 /* IOMMU capabilities */ #define IOMMU_CAP_IOTLB 24 @@ -613,11 +615,11 @@ struct amd_iommu_pci_seg { u16 *alias_table; =20 /* - * A list of required unity mappings we find in ACPI. It is not locked + * A list of required IVMD entry we find in ACPI. It is not locked * because as runtime it is only read. It is created at ACPI table * parsing time. */ - struct list_head unity_map; + struct list_head ivmd_entry_map; }; =20 /* @@ -873,7 +875,7 @@ struct ivhd_dte_flags { /* * One entry for unity mappings parsed out of the ACPI table. */ -struct unity_map_entry { +struct ivmd_entry { struct list_head list; =20 /* starting device id this entry is used for (including) */ @@ -886,8 +888,8 @@ struct unity_map_entry { /* end address to unity map (including) */ u64 address_end; =20 - /* required protection */ - int prot; + /* IVMD flags for the entry */ + u8 flags; }; =20 /* diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 2e854f4639a7..4b62bb89a12c 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -70,11 +70,6 @@ #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04 #define IVHD_FLAG_ISOC_EN_MASK 0x08 =20 -#define IVMD_FLAG_EXCL_RANGE 0x08 -#define IVMD_FLAG_IW 0x04 -#define IVMD_FLAG_IR 0x02 -#define IVMD_FLAG_UNITY_MAP 0x01 - #define ACPI_DEVFLAG_INITPASS 0x01 #define ACPI_DEVFLAG_EXTINT 0x02 #define ACPI_DEVFLAG_NMI 0x04 @@ -134,7 +129,7 @@ struct ivhd_entry { =20 /* * An AMD IOMMU memory definition structure. It defines things like exclus= ion - * ranges for devices and regions that should be unity mapped. + * ranges, unity mapping for devices and regions. */ struct ivmd_header { u8 type; @@ -1708,7 +1703,7 @@ static struct amd_iommu_pci_seg *__init alloc_pci_seg= ment(u16 id, =20 pci_seg->id =3D id; init_llist_head(&pci_seg->dev_data_list); - INIT_LIST_HEAD(&pci_seg->unity_map); + INIT_LIST_HEAD(&pci_seg->ivmd_entry_map); list_add_tail(&pci_seg->list, &amd_iommu_pci_seg_list); =20 if (alloc_dev_table(pci_seg)) @@ -2301,8 +2296,8 @@ static int __init amd_iommu_init_pci(void) } =20 /* - * Order is important here to make sure any unity map requirements are - * fulfilled. The unity mappings are created and written to the device + * Order is important here to make sure any ivmd map requirements are + * fulfilled. The ivmd mappings are created and written to the device * table during the iommu_init_pci() call. * * After that we call init_device_table_dma() to make sure any @@ -2588,28 +2583,28 @@ static int iommu_init_irq(struct amd_iommu *iommu) * * The next functions belong to the third pass of parsing the ACPI * table. In this last pass the memory mapping requirements are - * gathered (like exclusion and unity mapping ranges). + * gathered (like exclusion and ivmd mapping ranges). * *************************************************************************= ***/ =20 -static void __init free_unity_maps(void) +static void __init free_ivmd_maps(void) { - struct unity_map_entry *entry, *next; + struct ivmd_entry *entry, *next; struct amd_iommu_pci_seg *p, *pci_seg; =20 for_each_pci_segment_safe(pci_seg, p) { - list_for_each_entry_safe(entry, next, &pci_seg->unity_map, list) { + list_for_each_entry_safe(entry, next, &pci_seg->ivmd_entry_map, list) { list_del(&entry->list); kfree(entry); } } } =20 -/* called for unity map ACPI definition */ -static int __init init_unity_map_range(struct ivmd_header *m, - struct acpi_table_header *ivrs_base) +/* called for ivmd map ACPI definition */ +static int __init init_ivmd_map_range(struct ivmd_header *m, + struct acpi_table_header *ivrs_base) { - struct unity_map_entry *e =3D NULL; + struct ivmd_entry *e =3D NULL; struct amd_iommu_pci_seg *pci_seg; char *s; =20 @@ -2642,7 +2637,7 @@ static int __init init_unity_map_range(struct ivmd_he= ader *m, } e->address_start =3D PAGE_ALIGN(m->range_start); e->address_end =3D e->address_start + PAGE_ALIGN(m->range_length); - e->prot =3D m->flags >> 1; + e->flags =3D m->flags; =20 DUMP_printk("%s devid_start: %04x:%02x:%02x.%x devid_end: " "%04x:%02x:%02x.%x range_start: %016llx range_end: %016llx" @@ -2653,7 +2648,7 @@ static int __init init_unity_map_range(struct ivmd_he= ader *m, PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end), e->address_start, e->address_end, m->flags); =20 - list_add_tail(&e->list, &pci_seg->unity_map); + list_add_tail(&e->list, &pci_seg->ivmd_entry_map); =20 return 0; } @@ -2669,8 +2664,8 @@ static int __init init_memory_definitions(struct acpi= _table_header *table) =20 while (p < end) { m =3D (struct ivmd_header *)p; - if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE)) - init_unity_map_range(m, table); + if (m->flags & (IVMD_FLAG_UNITY | IVMD_FLAG_EXCL)) + init_ivmd_map_range(m, table); =20 p +=3D m->length; } @@ -3115,7 +3110,7 @@ static bool __init check_ioapic_information(void) static void __init free_dma_resources(void) { amd_iommu_pdom_id_destroy(); - free_unity_maps(); + free_ivmd_maps(); } =20 static void __init ivinfo_init(void *ivrs) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index 4e7f5b993c65..b26d29cb2d66 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3050,7 +3050,7 @@ static void amd_iommu_get_resv_regions(struct device = *dev, struct list_head *head) { struct iommu_resv_region *region; - struct unity_map_entry *entry; + struct ivmd_entry *entry; struct amd_iommu *iommu; struct amd_iommu_pci_seg *pci_seg; int devid, sbdf; @@ -3063,25 +3063,42 @@ static void amd_iommu_get_resv_regions(struct devic= e *dev, iommu =3D get_amd_iommu_from_dev(dev); pci_seg =3D iommu->pci_seg; =20 - list_for_each_entry(entry, &pci_seg->unity_map, list) { + list_for_each_entry(entry, &pci_seg->ivmd_entry_map, list) { int type, prot =3D 0; size_t length; =20 if (devid < entry->devid_start || devid > entry->devid_end) continue; =20 + /* + * IVMD_FLAG_UNITY, IVMD_FLAG_IR, IVMD_FLAG_IW are ignored if + * IVMD_FLAG_EXCL is set. + */ + if ((entry->flags & IVMD_FLAG_EXCL) && + (entry->flags & (IVMD_FLAG_UNITY | IVMD_FLAG_IR | IVMD_FLAG_IW))) + pr_err(FW_BUG "%s: Invalid IVMD flags combination: %#02x for sbdf=3D%#x= . Ignore IW/IR/Unity flags\n", + __func__, entry->flags, sbdf); + + if (entry->flags & ~IVMD_FLAG_MASK) + pr_err("%s: Unknown flags: %#02x for sbdf=3D%#x\n", + __func__, entry->flags & ~IVMD_FLAG_MASK, sbdf); + type =3D IOMMU_RESV_DIRECT; length =3D entry->address_end - entry->address_start; - if (entry->prot & IOMMU_PROT_IR) + if (entry->flags & IVMD_FLAG_IR) prot |=3D IOMMU_READ; - if (entry->prot & IOMMU_PROT_IW) + if (entry->flags & IVMD_FLAG_IW) prot |=3D IOMMU_WRITE; + if (entry->flags & IVMD_FLAG_EXCL) { + type =3D IOMMU_RESV_RESERVED; + prot =3D 0; + } =20 region =3D iommu_alloc_resv_region(entry->address_start, length, prot, type, GFP_KERNEL); if (!region) { - dev_err(dev, "Out of memory allocating dm-regions\n"); + pr_err("%s: Out of memory allocating reserved regions for sbdf=3D%#x\n"= , __func__, sbdf); return; } list_add_tail(®ion->list, head); --=20 2.34.1 From nobody Tue Jun 16 19:33:18 2026 Received: from BL2PR02CU003.outbound.protection.outlook.com (mail-eastusazon11011010.outbound.protection.outlook.com [52.101.52.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 13EF3377EB0 for ; Fri, 24 Apr 2026 09:22:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.52.10 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777022569; cv=fail; b=FpI/JScI1hX7TExRhDA0FjkHu/8S1o0TF/Da+jl8dgkRHpGC3w+m1svXl0LedEgY2ry/7OeMp8LZn4o/bMUONoq/wu82w9VtL1fu7S2v6s5r5Q1XLFqD7ohkoMJB36Ltsjn49rYD1ROnnvvdY9jFRhfRoQ1qJUsQQQ2A59Z5usc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777022569; c=relaxed/simple; bh=MS1bnE/lcPxHS2a/dMjjj55O8vRWDYyH4lxRGUVSKds=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ituhvrPdi8M7N/kVK5xqu06k3PIyGHYtmTrAtpdkTBYpfzW6gmspCA4jswyQoWDjRkR50ktHmLWGEHl43eUEuW4mYWJCeE7bd+Nz8ToSyoRDrbkThjTTsAVPDuO+Tj8Kh+83w1hMvl+XnfubHicnV7RrbE7Z1mGDw99ysVWcF6M= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com; spf=fail smtp.mailfrom=amd.com; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b=mJ5xWhtD; arc=fail smtp.client-ip=52.101.52.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=amd.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=amd.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=amd.com header.i=@amd.com header.b="mJ5xWhtD" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Qmv9jwSClm3rSODU79scSkLQsDY5hw0T2XMG9otzbpg42gCJ/0HkvLem5RD5Vr5Wg3/32iJOXr0xdIK9Xmw1LSGT5ofZCQw1nVux+ls+Goi/xGUWC8MSRm/TnIxkinhTPM1pxn3wRsgiG8nwllVeLWwkfQns2s5xTPYvyts3PDVWVDANUHHgkxjRiVlPwZxTevP4vukbDtgiWDSijC7LQ7DBQcT84SuomfIbU+QQDGe84Sl7gSm0UB13+dV/YzRpNGiNtlYFpjTIbEYELRjh+E8ivV7Lz69ewozorDZwaxE2Ws5rP7DyXcfK82y2h8rMfu2cUGMzzrbS4ULxrYc26Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=iobC8+fBn1zRaKaB7kP1X6EpxRUnbxprao61PwXD1Ug=; b=AdwzucmmlbORQW/ajDdPOUrnFejGpQFkkbXRSxIt+BbB+S32OgsspDo65HXW5yV8tvsjlDQRZHolxiowiWYD5jhZNnJTjSgt/pSeifX1yR1l2KAiAU/4RUTEC2NhTYqwlf1jXNCZfuS8jG5jftqiuTGDJZ8kVB14X/D1zDRD/K8xrkn094TrjLKXruPxWxwzJmpv2VTNcP27bN704i/2sovJdjiQij6pcCDiQvlaq61zzyCdl8Wj/mMTQ1lSLg6Fvy2N3PTBkVF77JzDQV1+hX5ZrkOjftc6Wl0oiFX0UYJCgdT9+0eUBbjJyhZ6G5StEYYGzyBbEkc5684lPxFNRg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=vger.kernel.org smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amd.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=iobC8+fBn1zRaKaB7kP1X6EpxRUnbxprao61PwXD1Ug=; b=mJ5xWhtD7/9L7FlX9baquerWamXkZI2kkfmJF+o/biQcWA0I43ggZIihJ10wbfbAxAGzKxshV6ACQyaM+lCKBwJwexbpzwquIJiMyUWVtBn7nfhPs4kXm9j0eog65Gy9xpf3ZpseZiM+1Ea3RMIiexIE0ueqfQ51KTaO8CjcO1Y= Received: from CH0P220CA0028.NAMP220.PROD.OUTLOOK.COM (2603:10b6:610:ef::7) by CH2PR12MB4056.namprd12.prod.outlook.com (2603:10b6:610:a5::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.22; Fri, 24 Apr 2026 09:22:44 +0000 Received: from CH2PEPF0000009F.namprd02.prod.outlook.com (2603:10b6:610:ef:cafe::5) by CH0P220CA0028.outlook.office365.com (2603:10b6:610:ef::7) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9846.22 via Frontend Transport; Fri, 24 Apr 2026 09:22:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CH2PEPF0000009F.mail.protection.outlook.com (10.167.244.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.18 via Frontend Transport; Fri, 24 Apr 2026 09:22:43 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 24 Apr 2026 04:22:40 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 4/4] iommu/amd: Introduce boot option ivmd=seg:bus:dev.fun,start,size,flags Date: Fri, 24 Apr 2026 09:22:13 +0000 Message-ID: <20260424092213.16976-5-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260424092213.16976-1-suravee.suthikulpanit@amd.com> References: <20260424092213.16976-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009F:EE_|CH2PR12MB4056:EE_ X-MS-Office365-Filtering-Correlation-Id: 8323da29-216f-4a59-7db2-08dea1e30a6d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700016|18002099003|56012099003|22082099003; X-Microsoft-Antispam-Message-Info: YRdfQ8CNlhsQFi2cSkMmNMpyBV6UnfFde2+NUCBoriRohKhmG7bQ1P6cDmQ6nLc8KtO1hRNnBnbDtNg4msQPqZyfF5ccRmaXKAdZvHCC5duQHmkx0ZBzH1Q1gKOl8g5PcBt9qhe5KzBW8f3LjIAf5uI77zky2Si7FHttM0c4exBG5StHPbjiMeWqR6BjSfD79opEmN+vn2T8S0WVr+oic2WZshI+JM0eLR32AEsKl6sLGQUha7DTJty2XA8VDIFs7mYdqoepWx3IFFAQw3hHQbziUgh1B/7DjER/75k2GOCTIWdc99GPmpOn77Fhj0WuvI8VGHdIboEqsvY+0gcAGSZpBuM6LsjEG3Zgc5d8GTr0ik9HiGyKvvxVDMuHJx2tkTEMRUZn4heQRDkG7SufqvBI1k/ocZEHSeb3nDLQx0zJ8RRZ+/GDURFSxm/ilFVzPc9v4u+pZVaUNpNJskj5gv+k6AXdgX189fwNGnUL4GnZXqwb8NtemXoy+CrfbkA8SbDogMT4+F9yJdXtaQVcdTins43mkByaK5aVwv2gTGJZkkzgG+s98omyKtWMbOud/61zD9FT+BOnWpwcIjcggHsKCd/HFJaIlnU3CO5+Gln9n3lgfjgzJVAyKRVIw8gsJxN7OymwTBeakS3VTEYFf2AqSFhXNJkQU6PuFOSxE/ZUyhRIkzxh+TAuxfDtDhgeJ//NEQVY8t1iaXN8ai2y2mFEGRTVAq/l7oojMzHIctDiVyKGpONtka6QkS6pdvfBeOgX0uBKwtlFF/UkT/7LOQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700016)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: rAqFIbe9NBy1AOGnPOyQJ+IPlKqzRb2BXIObwIrU3+EjA/jHuauYS40OpnSyYP+ekss59QzYifvWTfd8Le1VTFqNE+iKIKbzaRB97ca723q3x69roElbZdjuTuU4lc5vHSzR8rQ7dy3W0btUQJPiCkii3lfZ2bBByAH1/x9L39f4qLerE3BfJfCBH4Bx4VfUMgm2H4YRsqsumCjm4thynkHd30LKpvo/4UZaxSHH6Vvk6n+l76YDNMSfHH1eiqFtSRxF9+lLp64tG0uMRQ4olBfB4i5XBlxNHtH+jpD/9tMUEr7HerGzwSwNQ40DVh+sPurEuLOX6Y02OGQyLfzSgDSZIl1hF+fLbIueidb8qlIr15dqvdvmjcrmVZK8q4ZQsVj71F1ywpN0Q0KKV8BN3H3vK/e+Dm7V1/2oGIm2TrGDXop6v0lhtL+nA5Zqf/Ge X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2026 09:22:43.7251 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8323da29-216f-4a59-7db2-08dea1e30a6d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009F.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4056 Content-Type: text/plain; charset="utf-8" IVRS table contains IVMD blocks, which allow firmware to specify memory usage requirements to communicate to system software based on its needs or on hardware characteristics. Each IVMD entry may be per-device, range of devices. Some BIOS specify incorrect or missing IVMD entry. Introduce a new ivmd boot option to allow user to specify up-to 4 per-device IVMD entries at boot time. The entries are stored during driver initialization, and will be added to the per-segment ivmd_entry_map so that they can be included during struct iommu_ops.get_resv_regions. Signed-off-by: Suravee Suthikulpanit --- .../admin-guide/kernel-parameters.txt | 16 +++ drivers/iommu/amd/amd_iommu_types.h | 14 +++ drivers/iommu/amd/init.c | 104 +++++++++++++++++- 3 files changed, 133 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 03a550630644..e680a258008f 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2897,6 +2897,22 @@ Kernel parameters PCI device ID 00:14.5, write the parameter as: ivrs_acpihid[0001:00:14.5]=3DAMD0020:0 =20 + ivmd [HW,X86-64] + Supplement IVMD unity mapping or exclusion ranges from + the kernel command line (in addition to the IVRS ACPI + table). May be specified multiple times. + + Form: + ivmd=3Dsegment:bus:dev.fn,start,length,flags + + start and length are byte counts (decimal or 0x hex). + flags is the IVMD flags byte (UNITY, IR, IW, EXCL bits + per the AMD IOMMU specification). Use segment 0 for + PCI segment zero. + + Example: + ivmd=3D0000:00:01.0,0xe0000000,0x100000,0xb + js=3D [HW,JOY] Analog joystick See Documentation/input/joydev/joystick.rst. =20 diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 9321b7cc200b..4f3387dd7fab 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -892,6 +892,20 @@ struct ivmd_entry { u8 flags; }; =20 +/* + * IVMD-style ranges from ivrs_ivmd=3D... ; applied in + * init_memory_definitions() once per-PCI-segment + * ivmd_entry_map exists. + */ +struct ivmd_cmdline { + struct list_head list; + u16 pci_seg; + u16 devid; + u64 range_start; + u64 range_length; + u8 flags; +}; + /* * Data structures for device handling */ diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index 4b62bb89a12c..1d51fa7d1217 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -208,10 +208,12 @@ enum iommu_init_state { static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE]; static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE]; static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZ= E]; +static struct ivmd_cmdline early_ivmd_cmdline_map[EARLY_MAP_SIZE] __initda= ta; =20 static int __initdata early_ioapic_map_size; static int __initdata early_hpet_map_size; static int __initdata early_acpihid_map_size; +static int early_ivmd_cmdline_map_size __initdata; =20 static bool __initdata cmdline_maps; =20 @@ -2653,6 +2655,47 @@ static int __init init_ivmd_map_range(struct ivmd_he= ader *m, return 0; } =20 +static int __init apply_ivmd_cmdline_entries(struct acpi_table_header *ivr= s_base) +{ + int i; + struct ivmd_entry *e; + struct amd_iommu_pci_seg *pci_seg; + + for (i =3D 0; i < early_ivmd_cmdline_map_size; i++) { + struct ivmd_cmdline *cmd =3D &early_ivmd_cmdline_map[i]; + + pci_seg =3D get_pci_segment(cmd->pci_seg, ivrs_base); + if (!pci_seg) { + pr_err("%s: PCI segment %#x unavailable\n", + __func__, cmd->pci_seg); + continue; + } + + if (cmd->devid > pci_seg->last_bdf) { + pr_err("%s: requestor %#x:%#02x:%#02x.%#02x exceeds segment %#x last BD= F %#x\n", + __func__, cmd->pci_seg, PCI_BUS_NUM(cmd->devid), + PCI_SLOT(cmd->devid), PCI_FUNC(cmd->devid), + pci_seg->id, pci_seg->last_bdf); + continue; + } + + e =3D kzalloc(sizeof(*e), GFP_KERNEL); + if (!e) { + pr_err("%s: Failed to allocate ivmd entry\n", __func__); + return -ENOMEM; + } + + e->devid_start =3D cmd->devid; + e->devid_end =3D cmd->devid; + e->address_start =3D PAGE_ALIGN(cmd->range_start); + e->address_end =3D e->address_start + PAGE_ALIGN(cmd->range_length); + e->flags =3D cmd->flags; + list_add_tail(&e->list, &pci_seg->ivmd_entry_map); + } + + return 0; +} + /* iterates over all memory definitions we find in the ACPI table */ static int __init init_memory_definitions(struct acpi_table_header *table) { @@ -2670,7 +2713,7 @@ static int __init init_memory_definitions(struct acpi= _table_header *table) p +=3D m->length; } =20 - return 0; + return apply_ivmd_cmdline_entries(table); } =20 /* @@ -3812,12 +3855,71 @@ static int __init parse_ivrs_acpihid(char *str) return 1; } =20 +/* + * ivmd=3Dseg:bus:dev.fn,start,length,flags + * + * start and length are in bytes (decimal or 0x hex). flags is the IVMD fl= ags + * byte (IVMD_FLAG_UNITY, IVMD_FLAG_IR, IVMD_FLAG_IW, IVMD_FLAG_EXCL). May= be + * repeated for multiple ranges. + */ +static int __init parse_ivmd(char *str) +{ + u32 seg, bus, dev, fn; + unsigned long long range_start, range_len; + unsigned int flags; + struct ivmd_cmdline *cmd; + + if (!str) + goto invalid; + + if (sscanf(str, "%x:%x:%x.%x,%llx,%llx,%x", + &seg, &bus, &dev, &fn, &range_start, + &range_len, &flags) !=3D 7) + goto invalid; + + if (flags & ~IVMD_FLAG_MASK) { + pr_err("%s: flags %#x contains unknown flags\n", __func__, flags); + return 1; + } + + if (!(flags & (IVMD_FLAG_UNITY | IVMD_FLAG_EXCL))) + pr_warn("%s: flags %#02x omit UNITY/EXCL; entry may have no effect\n", + __func__, (u8)flags); + + if (early_ivmd_cmdline_map_size =3D=3D EARLY_MAP_SIZE) { + pr_err("%s: Early IVMD command line map overflow - ignoring ivmd=3D%s\n", + __func__, str); + return 1; + } + + cmd =3D &early_ivmd_cmdline_map[early_ivmd_cmdline_map_size]; + early_ivmd_cmdline_map_size++; + + cmd->pci_seg =3D (u16)seg; + cmd->devid =3D PCI_DEVID(bus & 0xff, PCI_DEVFN(dev & 0x1f, fn & 0x7)); + cmd->range_start =3D range_start; + cmd->range_length =3D range_len; + cmd->flags =3D (u8)flags; + + pr_info("%s: segment=3D%04x dev=3D%02x:%02x.%x start=3D%#llx len=3D%#llx = flags=3D%#02x\n", + __func__, cmd->pci_seg, + PCI_BUS_NUM(cmd->devid), PCI_SLOT(cmd->devid), + PCI_FUNC(cmd->devid), range_start, range_len, cmd->flags); + + return 1; + +invalid: + pr_err("Invalid command line: ivmd=3D%s\n", str ? str : ""); + return 1; +} + __setup("amd_iommu_dump", parse_amd_iommu_dump); __setup("amd_iommu=3D", parse_amd_iommu_options); __setup("amd_iommu_intr=3D", parse_amd_iommu_intr); __setup("ivrs_ioapic", parse_ivrs_ioapic); __setup("ivrs_hpet", parse_ivrs_hpet); __setup("ivrs_acpihid", parse_ivrs_acpihid); +__setup("ivmd=3D", parse_ivmd); =20 bool amd_iommu_pasid_supported(void) { --=20 2.34.1