From nobody Wed Jun 17 07:36:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E70C30AD0A; Thu, 23 Apr 2026 19:49:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776973800; cv=none; b=K5C13h25LSv/xroBvkWdbYNEKR1Q5rBirqFX4wwyoYm5jPQDXMg7MvW1mWmWHeIljqumgvbeborkNWx4V7B/sYPBcaaYVQJN/jP5rl5rC61oECnORAc5/MMNMPS8masSmOaoDyQXygwlKoVPnDVWR1WabodIYzEN1aYbkv/mxXg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776973800; c=relaxed/simple; bh=yhg5gVajDM6Da2FgjY3mvjRRBtWbHEv5TqLXfC/zzJU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=pT5kQn+o2kRHk4oF16mcjjSXGazYuvfvqB8oyn8YCZ+HkcB+y8olgBIaFJMw9RWdxunivAHLi9p15sZq7Dl1OYNc+rqpAdoN8mibewm2vi+sflfEzPTAd8HbSlJ/vydbFOGPt2dvqMDhtyDeZsB9jCVolLKloAA+ZvePiYiPedE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=Gof7z4wL; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="Gof7z4wL" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id AE28B26E30; Thu, 23 Apr 2026 21:49:56 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id Xfdy58reHSr3; Thu, 23 Apr 2026 21:49:55 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776973795; bh=yhg5gVajDM6Da2FgjY3mvjRRBtWbHEv5TqLXfC/zzJU=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Gof7z4wLEw1THwcB3kYUtiAAjWyvZaXYF0Ah0mNzVq9q8HyKLHoA48eSZo3CgLSJn xq0kSgysgkdwr5iP6w2+SMjMSSkHsfQBYNJm7Ntio3X7ogDcIEn6OOvA0OqcXEnONP 3fD7mPipkfHZFMYuODhk0tmaIaHJXzoogZBJxe81h7EtJMM7+0+tdgTM6uQDdZu+3m v0XKW0CamKLB76dOK9vf7P8kLzw5VbmKWe3uzJWdU3mY8XrFZZ+qFSvfJAf6dwKaW4 F5b6NlRqkP7tdRNUoT2X0yO9WYZtfsGfGTNiHBBi2r9k2frpCp2W2ShQeZ8d/1x2Gg fOe0HqJMPP6+g== From: Kaustabh Chakraborty Date: Fri, 24 Apr 2026 01:09:00 +0530 Subject: [PATCH v5 01/11] dt-bindings: leds: document Samsung S2M series PMIC flash LED device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260424-s2mu005-pmic-v5-1-fcbc9da5a004@disroot.org> References: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> In-Reply-To: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan , Nam Tran , =?utf-8?q?=C5=81ukasz_Lebiedzi=C5=84ski?= Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty , Conor Dooley Certain Samsung S2M series PMICs have a flash LED controller with two LED channels, and with torch and flash control modes. Document the devicetree schema for the device. Acked-by: Conor Dooley Signed-off-by: Kaustabh Chakraborty --- .../bindings/leds/samsung,s2mu005-flash.yaml | 52 ++++++++++++++++++= ++++ 1 file changed, 52 insertions(+) diff --git a/Documentation/devicetree/bindings/leds/samsung,s2mu005-flash.y= aml b/Documentation/devicetree/bindings/leds/samsung,s2mu005-flash.yaml new file mode 100644 index 0000000000000..36051ab20509f --- /dev/null +++ b/Documentation/devicetree/bindings/leds/samsung,s2mu005-flash.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/samsung,s2mu005-flash.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Flash and Torch LED Controller for Samsung S2M series PMICs + +maintainers: + - Kaustabh Chakraborty + +description: | + The Samsung S2M series PMIC flash LED has two led channels (typically + as back and front camera flashes), with support for both torch and + flash modes. + + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +properties: + compatible: + enum: + - samsung,s2mu005-flash + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^led@[0-1]$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + reg: + enum: [0, 1] + + required: + - reg + +required: + - compatible + - "#address-cells" + - "#size-cells" + +additionalProperties: false --=20 2.53.0 From nobody Wed Jun 17 07:36:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E12838CFE5; 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arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="Tjyvp/h2" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id C979D25F7C; Thu, 23 Apr 2026 21:50:02 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 9kRrkUfy7Ex0; Thu, 23 Apr 2026 21:50:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776973802; bh=49gZmuy7/uaMr4IxZ6SU1T8b0OR9K5hUBztsiny6iO0=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=Tjyvp/h28HP9KD3FkyrZ9Cj7VDHTw8r6gRR0Yl73FZ1q5JnSPWkfPeFn5Tex1yDu9 UKXr1fv2nUjqqW8duGKzQZbfDbt+ePs7n0T/+pjQD36z23Y9EY6GI/27lRM9zGmLjn YKtFAHQJZUHTH8FJQ7LMYN4QNTXJLM++w/rR8HyEF6+/ASu3Po+4xNhOYxY15aFfop Z4gM5ycpH+U6thpNpPeOj7LtVP/m47YWmRo8mPIuvN9NQ9tb8d1r887MTB5sWdZMGo YEKZ4owf8RQOzMe2hMs95c0JD6QhQJ9+GFiCnebv+YOFcZgX9wzvWotohzUWUeDhNU joTsFkg/khzbA== From: Kaustabh Chakraborty Date: Fri, 24 Apr 2026 01:09:01 +0530 Subject: [PATCH v5 02/11] dt-bindings: extcon: document Samsung S2M series PMIC extcon device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260424-s2mu005-pmic-v5-2-fcbc9da5a004@disroot.org> References: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> In-Reply-To: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan , Nam Tran , =?utf-8?q?=C5=81ukasz_Lebiedzi=C5=84ski?= Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Certain Samsung S2M series PMICs have a MUIC device which reports various cable states by measuring the ID-GND resistance with an internal ADC. Document the devicetree schema for this device. Signed-off-by: Kaustabh Chakraborty Reviewed-by: Krzysztof Kozlowski --- .../bindings/extcon/samsung,s2mu005-muic.yaml | 40 ++++++++++++++++++= ++++ 1 file changed, 40 insertions(+) diff --git a/Documentation/devicetree/bindings/extcon/samsung,s2mu005-muic.= yaml b/Documentation/devicetree/bindings/extcon/samsung,s2mu005-muic.yaml new file mode 100644 index 0000000000000..0a320d5e2a352 --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/samsung,s2mu005-muic.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/extcon/samsung,s2mu005-muic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MUIC Device for Samsung S2M series PMICs + +maintainers: + - Kaustabh Chakraborty + +description: | + The Samsung S2M series PMIC MUIC device is a USB port accessory + detector. It reports multiple states depending on the ID-GND + resistance measured by an internal ADC. + + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +properties: + compatible: + enum: + - samsung,s2mu005-muic + + connector: + $ref: /schemas/connector/usb-connector.yaml# + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Port connecting to the USB controller or PHY. + +required: + - compatible + - connector + - port + +additionalProperties: false --=20 2.53.0 From nobody Wed Jun 17 07:36:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 878BC30FC27; Thu, 23 Apr 2026 19:50:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776973812; cv=none; b=iFqstCsjUVoDAl1Nklq9AYkhJtHOVcs7Xa6RFEPIDL9mQYpsTZtHzQc60yqAlLhx/jzwB5NltJ2hbddj57zTwsoJLgmzASE+7TrDljwBdYAH2KFta9qvtDFkqcI7BWDoYGkUpMMS0p9fRzQBgUtSZ3kjOFMvQgLVzsYMgkg3VjE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776973812; c=relaxed/simple; bh=wG5aVvMxMI0cXNDURk14EaW5rpeeJXdYvxDtGL++Q0g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=MYgE4++cFvyhP5adMqvEdX96ASzh+YZ5sc/+Bnpf1d9LttgFfp/Fm4SiY2k1DWGTN6F3CBXsl+LpmieH715Fn3sOwGHIJvHtusmu01rnFHeBCMZdsxpu+gHJnJZ8pQu53jE1bSKEG4UiObLisz49Ix/EKBSfVCCHCJQ6/FNLKBk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=NElyZ6pj; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="NElyZ6pj" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 34ED226DA5; Thu, 23 Apr 2026 21:50:09 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id HApEscDIVU-H; Thu, 23 Apr 2026 21:50:08 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776973808; bh=wG5aVvMxMI0cXNDURk14EaW5rpeeJXdYvxDtGL++Q0g=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=NElyZ6pj03bOT5FcS/NuhOQ5Fuwn1uTVjnm/xuGHCbMIxwHPHVcH5/UoPP0QqyALM Z4b7/mNAefz1ctpR1mZNPICfK849+zS0bhPj+Z6EFECcnYaI/9aCnIl4DyqVrYJz4E Q70Rxxz3+wSuA1qz4NxZL15Yo4lxC+sj22mMJOju9uyZQ10HOsWIs5wQseS33piaXL c6a3Fuava/hawCEHd2Tb1B2TveZg0oGTBYCHJNeg4+8ZSvmQNkf0uHS6A7Xq8wxYgQ xdktrc0rAJvAcGaovovw7EcnQT9heRfyGYowUYc03y5B7J9149vX3KHKqAKR5lnXqS rXEpVsDjf9KJw== From: Kaustabh Chakraborty Date: Fri, 24 Apr 2026 01:09:02 +0530 Subject: [PATCH v5 03/11] dt-bindings: mfd: add documentation for S2MU005 PMIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260424-s2mu005-pmic-v5-3-fcbc9da5a004@disroot.org> References: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> In-Reply-To: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan , Nam Tran , =?utf-8?q?=C5=81ukasz_Lebiedzi=C5=84ski?= Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Samsung's S2MU005 PMIC includes subdevices for a charger, an MUIC (Micro USB Interface Controller), and flash and RGB LED controllers. Add the compatible and documentation for the S2MU005 PMIC. Also, add an example for nodes for supported sub-devices, i.e. MUIC, flash LEDs, and RGB LEDs. Charger sub-device uses the node of the parent. Signed-off-by: Kaustabh Chakraborty Reviewed-by: Krzysztof Kozlowski --- .../bindings/mfd/samsung,s2mu005-pmic.yaml | 120 +++++++++++++++++= ++++ 1 file changed, 120 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/samsung,s2mu005-pmic.yam= l b/Documentation/devicetree/bindings/mfd/samsung,s2mu005-pmic.yaml new file mode 100644 index 0000000000000..0e6afb7d2017b --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/samsung,s2mu005-pmic.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/samsung,s2mu005-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MU005 Power Management IC + +maintainers: + - Kaustabh Chakraborty + +description: | + The S2MU005 is a companion power management IC which includes subdevices= for + a charger controller, an MUIC (Micro USB Interface Controller), and flas= h and + RGB LED controllers. + +allOf: + - $ref: /schemas/power/supply/power-supply.yaml# + +properties: + compatible: + const: samsung,s2mu005-pmic + + flash: + $ref: /schemas/leds/samsung,s2mu005-flash.yaml + description: + Child node describing flash LEDs. + + interrupts: + maxItems: 1 + + muic: + $ref: /schemas/extcon/samsung,s2mu005-muic.yaml# + description: + Child node describing MUIC device. + + multi-led: + type: object + + allOf: + - $ref: /schemas/leds/leds-class-multicolor.yaml# + + properties: + compatible: + const: samsung,s2mu005-rgb + + required: + - compatible + + unevaluatedProperties: false + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + pmic@3d { + compatible =3D "samsung,s2mu005-pmic"; + reg =3D <0x3d>; + interrupt-parent =3D <&gpa2>; + interrupts =3D <7 IRQ_TYPE_LEVEL_LOW>; + + monitored-battery =3D <&battery>; + + flash { + compatible =3D "samsung,s2mu005-flash"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_FLASH; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_FLASH; + function-enumerator =3D <1>; + }; + }; + + muic { + compatible =3D "samsung,s2mu005-muic"; + + connector { + compatible =3D "usb-b-connector"; + label =3D "micro-USB"; + type =3D "micro"; + }; + + port { + muic_to_usb: endpoint { + remote-endpoint =3D <&usb_to_muic>; + }; + }; + }; + + multi-led { + compatible =3D "samsung,s2mu005-rgb"; + color =3D ; + function =3D LED_FUNCTION_INDICATOR; + linux,default-trigger =3D "pattern"; + }; + }; + }; --=20 2.53.0 From nobody Wed Jun 17 07:36:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 865C138B12E; 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arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="bm7PlZUt" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 3622626E0B; Thu, 23 Apr 2026 21:50:17 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id P0KWN_iAOy0T; Thu, 23 Apr 2026 21:50:16 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776973816; bh=LFjAFAVwO5Nu/MOC+tNSl8yBOL7bZTUyf9oO3Hf2LD8=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=bm7PlZUtb5bqeuh9GlvZA/3B18rGFKJJSuOyjnR1BiBAvW29ekznHtbf66CorkgKM L9k4Uo/UkvqvHJ38cq0dLUOpuGvYVW61uiIq11B2hFz06Wbq1uWKJ4j9IfGKW/aefc 1DJZoONQtqi/LUmrOaAg6AYOGOTZ8eI/sdV6M4J+sRQeabjAC0h01K/ry3KyGZfc5a n76Ts7KiGmV9auxX6TAM8moEzkr3yAABOwynxAKSRBwgnMtWoDnZt+xufYUBFPxb7c xG/pj2oWzp9EY8t/M1AJ9Fu+WKRIdDVh+o3K/eCW15wHCulcubfYWDaeTmP9/BcQUl 2nhFzL3zMauGg== From: Kaustabh Chakraborty Date: Fri, 24 Apr 2026 01:09:03 +0530 Subject: [PATCH v5 04/11] mfd: sec: add support for S2MU005 PMIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260424-s2mu005-pmic-v5-4-fcbc9da5a004@disroot.org> References: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> In-Reply-To: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan , Nam Tran , =?utf-8?q?=C5=81ukasz_Lebiedzi=C5=84ski?= Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Samsung's S2MU005 PMIC includes subdevices for a charger, an MUIC (Micro USB Interface Controller), and flash and RGB LED controllers. S2MU005's interrupt registers can be properly divided into three regmap IRQ chips, one each for the charger, flash LEDs, and the MUIC. Add initial support for S2MU005 in the PMIC driver, along with it's three interrupt chips. Co-developed-by: =C5=81ukasz Lebiedzi=C5=84ski Signed-off-by: =C5=81ukasz Lebiedzi=C5=84ski Signed-off-by: Kaustabh Chakraborty --- drivers/mfd/sec-common.c | 16 ++ drivers/mfd/sec-i2c.c | 29 ++++ drivers/mfd/sec-irq.c | 74 ++++++++ include/linux/mfd/samsung/core.h | 1 + include/linux/mfd/samsung/irq.h | 66 +++++++ include/linux/mfd/samsung/s2mu005.h | 332 ++++++++++++++++++++++++++++++++= ++++ 6 files changed, 518 insertions(+) diff --git a/drivers/mfd/sec-common.c b/drivers/mfd/sec-common.c index bd8b5f9686892..ad1c7de83a620 100644 --- a/drivers/mfd/sec-common.c +++ b/drivers/mfd/sec-common.c @@ -105,6 +105,18 @@ static const struct mfd_cell s2mpu05_devs[] =3D { MFD_CELL_RES("s2mps15-rtc", s2mpu05_rtc_resources), }; =20 +static const struct resource s2mu005_muic_resources[] =3D { + DEFINE_RES_IRQ_NAMED(S2MU005_IRQ_MUIC_ATTACH, "attach"), + DEFINE_RES_IRQ_NAMED(S2MU005_IRQ_MUIC_DETACH, "detach"), +}; + +static const struct mfd_cell s2mu005_devs[] =3D { + MFD_CELL_NAME("s2mu005-charger"), + MFD_CELL_OF("s2mu005-flash", NULL, NULL, 0, 0, "samsung,s2mu005-flash"), + MFD_CELL_OF("s2mu005-muic", s2mu005_muic_resources, NULL, 0, 0, "samsung,= s2mu005-muic"), + MFD_CELL_OF("s2mu005-rgb", NULL, NULL, 0, 0, "samsung,s2mu005-rgb"), +}; + static void sec_pmic_dump_rev(struct sec_pmic_dev *sec_pmic) { unsigned int val; @@ -250,6 +262,10 @@ int sec_pmic_probe(struct device *dev, int device_type= , unsigned int irq, sec_devs =3D s2mpu05_devs; num_sec_devs =3D ARRAY_SIZE(s2mpu05_devs); break; + case S2MU005: + sec_devs =3D s2mu005_devs; + num_sec_devs =3D ARRAY_SIZE(s2mu005_devs); + break; default: return dev_err_probe(sec_pmic->dev, -EINVAL, "Unsupported device type %d\n", diff --git a/drivers/mfd/sec-i2c.c b/drivers/mfd/sec-i2c.c index 3132b849b4bc4..d8609886fcc80 100644 --- a/drivers/mfd/sec-i2c.c +++ b/drivers/mfd/sec-i2c.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -66,6 +67,19 @@ static bool s2mpu02_volatile(struct device *dev, unsigne= d int reg) } } =20 +static bool s2mu005_volatile(struct device *dev, unsigned int reg) +{ + switch (reg) { + case S2MU005_REG_CHGR_INT1M: + case S2MU005_REG_FLED_INT1M: + case S2MU005_REG_MUIC_INT1M: + case S2MU005_REG_MUIC_INT2M: + return false; + default: + return true; + } +} + static const struct regmap_config s2dos05_regmap_config =3D { .reg_bits =3D 8, .val_bits =3D 8, @@ -130,6 +144,15 @@ static const struct regmap_config s2mpu05_regmap_confi= g =3D { .val_bits =3D 8, }; =20 +static const struct regmap_config s2mu005_regmap_config =3D { + .reg_bits =3D 8, + .val_bits =3D 8, + + .max_register =3D S2MU005_REG_MUIC_LDOADC_H, + .volatile_reg =3D s2mu005_volatile, + .cache_type =3D REGCACHE_FLAT_S, +}; + static const struct regmap_config s5m8767_regmap_config =3D { .reg_bits =3D 8, .val_bits =3D 8, @@ -203,6 +226,11 @@ static const struct sec_pmic_i2c_platform_data s2mpu05= _data =3D { .device_type =3D S2MPU05, }; =20 +static const struct sec_pmic_i2c_platform_data s2mu005_data =3D { + .regmap_cfg =3D &s2mu005_regmap_config, + .device_type =3D S2MU005, +}; + static const struct sec_pmic_i2c_platform_data s5m8767_data =3D { .regmap_cfg =3D &s5m8767_regmap_config, .device_type =3D S5M8767X, @@ -217,6 +245,7 @@ static const struct of_device_id sec_pmic_i2c_of_match[= ] =3D { { .compatible =3D "samsung,s2mps15-pmic", .data =3D &s2mps15_data, }, { .compatible =3D "samsung,s2mpu02-pmic", .data =3D &s2mpu02_data, }, { .compatible =3D "samsung,s2mpu05-pmic", .data =3D &s2mpu05_data, }, + { .compatible =3D "samsung,s2mu005-pmic", .data =3D &s2mu005_data, }, { .compatible =3D "samsung,s5m8767-pmic", .data =3D &s5m8767_data, }, { }, }; diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c index 133188391f7c2..91a2922463fb6 100644 --- a/drivers/mfd/sec-irq.c +++ b/drivers/mfd/sec-irq.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include "sec-core.h" @@ -223,6 +224,65 @@ static const struct regmap_irq s2mpu05_irqs[] =3D { REGMAP_IRQ_REG(S2MPU05_IRQ_TSD, 2, S2MPU05_IRQ_TSD_MASK), }; =20 +static const struct regmap_irq s2mu005_irqs[] =3D { + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_DETBAT, 0, S2MU005_IRQ_CHGR_DETBAT_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_BAT, 0, S2MU005_IRQ_CHGR_BAT_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_IVR, 0, S2MU005_IRQ_CHGR_IVR_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_EVENT, 0, S2MU005_IRQ_CHGR_EVENT_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_CHG, 0, S2MU005_IRQ_CHGR_CHG_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_VMID, 0, S2MU005_IRQ_CHGR_VMID_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_WCIN, 0, S2MU005_IRQ_CHGR_WCIN_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_CHGR_VBUS, 0, S2MU005_IRQ_CHGR_VBUS_MASK), + + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_LBPROT, 1, S2MU005_IRQ_FLED_LBPROT_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_OPENCH2, 1, S2MU005_IRQ_FLED_OPENCH2_MASK= ), + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_OPENCH1, 1, S2MU005_IRQ_FLED_OPENCH1_MASK= ), + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_SHORTCH2, 1, S2MU005_IRQ_FLED_SHORTCH2_MA= SK), + REGMAP_IRQ_REG(S2MU005_IRQ_FLED_SHORTCH1, 1, S2MU005_IRQ_FLED_SHORTCH1_MA= SK), + + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_ATTACH, 2, S2MU005_IRQ_MUIC_ATTACH_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_DETACH, 2, S2MU005_IRQ_MUIC_DETACH_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_KP, 2, S2MU005_IRQ_MUIC_KP_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_LKP, 2, S2MU005_IRQ_MUIC_LKP_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_LKR, 2, S2MU005_IRQ_MUIC_LKR_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_RIDCHG, 2, S2MU005_IRQ_MUIC_RIDCHG_MASK), + + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_VBUSON, 3, S2MU005_IRQ_MUIC_VBUSON_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_RSVD, 3, S2MU005_IRQ_MUIC_RSVD_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_ADC, 3, S2MU005_IRQ_MUIC_ADC_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_STUCK, 3, S2MU005_IRQ_MUIC_STUCK_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_STUCKRCV, 3, S2MU005_IRQ_MUIC_STUCKRCV_MA= SK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_MHDL, 3, S2MU005_IRQ_MUIC_MHDL_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_AVCHG, 3, S2MU005_IRQ_MUIC_AVCHG_MASK), + REGMAP_IRQ_REG(S2MU005_IRQ_MUIC_VBUSOFF, 3, S2MU005_IRQ_MUIC_VBUSOFF_MASK= ), +}; + +static unsigned int s2mu005_irq_get_reg(struct regmap_irq_chip_data *data, + unsigned int base, int index) +{ + const unsigned int irqf_regs[] =3D { + S2MU005_REG_CHGR_INT1, + S2MU005_REG_FLED_INT1, + S2MU005_REG_MUIC_INT1, + S2MU005_REG_MUIC_INT2, + }; + const unsigned int mask_regs[] =3D { + S2MU005_REG_CHGR_INT1M, + S2MU005_REG_FLED_INT1M, + S2MU005_REG_MUIC_INT1M, + S2MU005_REG_MUIC_INT2M, + }; + + switch (base) { + case S2MU005_REG_CHGR_INT1: + return irqf_regs[index]; + case S2MU005_REG_CHGR_INT1M: + return mask_regs[index]; + } + + return base; +} + static const struct regmap_irq s5m8767_irqs[] =3D { REGMAP_IRQ_REG(S5M8767_IRQ_PWRR, 0, S5M8767_IRQ_PWRR_MASK), REGMAP_IRQ_REG(S5M8767_IRQ_PWRF, 0, S5M8767_IRQ_PWRF_MASK), @@ -337,6 +397,17 @@ static const struct regmap_irq_chip s2mpu05_irq_chip = =3D { .ack_base =3D S2MPU05_REG_INT1, }; =20 +static const struct regmap_irq_chip s2mu005_irq_chip =3D { + .name =3D "s2mu005", + .irqs =3D s2mu005_irqs, + .num_irqs =3D ARRAY_SIZE(s2mu005_irqs), + .num_regs =3D 4, + .status_base =3D S2MU005_REG_CHGR_INT1, + .mask_base =3D S2MU005_REG_CHGR_INT1M, + .ack_base =3D S2MU005_REG_CHGR_INT1, + .get_irq_reg =3D s2mu005_irq_get_reg, +}; + static const struct regmap_irq_chip s5m8767_irq_chip =3D { .name =3D "s5m8767", .irqs =3D s5m8767_irqs, @@ -442,6 +513,9 @@ struct regmap_irq_chip_data *sec_irq_init(struct sec_pm= ic_dev *sec_pmic) case S2MPU05: sec_irq_chip =3D &s2mpu05_irq_chip; break; + case S2MU005: + sec_irq_chip =3D &s2mu005_irq_chip; + break; default: return dev_err_ptr_probe(sec_pmic->dev, -EINVAL, "Unsupported device typ= e %d\n", sec_pmic->device_type); diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/c= ore.h index 4480c631110a6..6191f409de945 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -47,6 +47,7 @@ enum sec_device_type { S2MPS15X, S2MPU02, S2MPU05, + S2MU005, }; =20 /** diff --git a/include/linux/mfd/samsung/irq.h b/include/linux/mfd/samsung/ir= q.h index 6eab95de6fa83..19d0f0e12944f 100644 --- a/include/linux/mfd/samsung/irq.h +++ b/include/linux/mfd/samsung/irq.h @@ -408,6 +408,72 @@ enum s2mpu05_irq { #define S2MPU05_IRQ_INT140C_MASK BIT(1) #define S2MPU05_IRQ_TSD_MASK BIT(2) =20 +enum s2mu005_irq { + S2MU005_IRQ_CHGR_DETBAT, + S2MU005_IRQ_CHGR_BAT, + S2MU005_IRQ_CHGR_IVR, + S2MU005_IRQ_CHGR_EVENT, + S2MU005_IRQ_CHGR_CHG, + S2MU005_IRQ_CHGR_VMID, + S2MU005_IRQ_CHGR_WCIN, + S2MU005_IRQ_CHGR_VBUS, + + S2MU005_IRQ_FLED_LBPROT, + S2MU005_IRQ_FLED_OPENCH2, + S2MU005_IRQ_FLED_OPENCH1, + S2MU005_IRQ_FLED_SHORTCH2, + S2MU005_IRQ_FLED_SHORTCH1, + + S2MU005_IRQ_MUIC_ATTACH, + S2MU005_IRQ_MUIC_DETACH, + S2MU005_IRQ_MUIC_KP, + S2MU005_IRQ_MUIC_LKP, + S2MU005_IRQ_MUIC_LKR, + S2MU005_IRQ_MUIC_RIDCHG, + + S2MU005_IRQ_MUIC_VBUSON, + S2MU005_IRQ_MUIC_RSVD, + S2MU005_IRQ_MUIC_ADC, + S2MU005_IRQ_MUIC_STUCK, + S2MU005_IRQ_MUIC_STUCKRCV, + S2MU005_IRQ_MUIC_MHDL, + S2MU005_IRQ_MUIC_AVCHG, + S2MU005_IRQ_MUIC_VBUSOFF, + + S2MU005_IRQ_NR, +}; + +#define S2MU005_IRQ_CHGR_DETBAT_MASK BIT(0) +#define S2MU005_IRQ_CHGR_BAT_MASK BIT(1) +#define S2MU005_IRQ_CHGR_IVR_MASK BIT(2) +#define S2MU005_IRQ_CHGR_EVENT_MASK BIT(3) +#define S2MU005_IRQ_CHGR_CHG_MASK BIT(4) +#define S2MU005_IRQ_CHGR_VMID_MASK BIT(5) +#define S2MU005_IRQ_CHGR_WCIN_MASK BIT(6) +#define S2MU005_IRQ_CHGR_VBUS_MASK BIT(7) + +#define S2MU005_IRQ_FLED_LBPROT_MASK BIT(2) +#define S2MU005_IRQ_FLED_OPENCH2_MASK BIT(4) +#define S2MU005_IRQ_FLED_OPENCH1_MASK BIT(5) +#define S2MU005_IRQ_FLED_SHORTCH2_MASK BIT(6) +#define S2MU005_IRQ_FLED_SHORTCH1_MASK BIT(7) + +#define S2MU005_IRQ_MUIC_ATTACH_MASK BIT(0) +#define S2MU005_IRQ_MUIC_DETACH_MASK BIT(1) +#define S2MU005_IRQ_MUIC_KP_MASK BIT(2) +#define S2MU005_IRQ_MUIC_LKP_MASK BIT(3) +#define S2MU005_IRQ_MUIC_LKR_MASK BIT(4) +#define S2MU005_IRQ_MUIC_RIDCHG_MASK BIT(5) + +#define S2MU005_IRQ_MUIC_VBUSON_MASK BIT(0) +#define S2MU005_IRQ_MUIC_RSVD_MASK BIT(1) +#define S2MU005_IRQ_MUIC_ADC_MASK BIT(2) +#define S2MU005_IRQ_MUIC_STUCK_MASK BIT(3) +#define S2MU005_IRQ_MUIC_STUCKRCV_MASK BIT(4) +#define S2MU005_IRQ_MUIC_MHDL_MASK BIT(5) +#define S2MU005_IRQ_MUIC_AVCHG_MASK BIT(6) +#define S2MU005_IRQ_MUIC_VBUSOFF_MASK BIT(7) + enum s5m8767_irq { S5M8767_IRQ_PWRR, S5M8767_IRQ_PWRF, diff --git a/include/linux/mfd/samsung/s2mu005.h b/include/linux/mfd/samsun= g/s2mu005.h new file mode 100644 index 0000000000000..46e7759545af2 --- /dev/null +++ b/include/linux/mfd/samsung/s2mu005.h @@ -0,0 +1,332 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * Copyright (c) 2026 Kaustabh Chakraborty + * Copyright (c) 2026 =C5=81ukasz Lebiedzi=C5=84ski + */ + +#ifndef __LINUX_MFD_S2MU005_H +#define __LINUX_MFD_S2MU005_H + +#include +#include + +/* S2MU005 registers */ +enum s2mu005_reg { + S2MU005_REG_CHGR_INT1, + S2MU005_REG_CHGR_INT1M, + + S2MU005_REG_FLED_INT1, + S2MU005_REG_FLED_INT1M, + + S2MU005_REG_MUIC_INT1, + S2MU005_REG_MUIC_INT2, + S2MU005_REG_MUIC_INT1M, + S2MU005_REG_MUIC_INT2M, + + S2MU005_REG_CHGR_STATUS0, + S2MU005_REG_CHGR_STATUS1, + S2MU005_REG_CHGR_STATUS2, + S2MU005_REG_CHGR_STATUS3, + S2MU005_REG_CHGR_STATUS4, + S2MU005_REG_CHGR_STATUS5, + S2MU005_REG_CHGR_CTRL0, + S2MU005_REG_CHGR_CTRL1, + S2MU005_REG_CHGR_CTRL2, + S2MU005_REG_CHGR_CTRL3, + S2MU005_REG_CHGR_CTRL4, + S2MU005_REG_CHGR_CTRL5, + S2MU005_REG_CHGR_CTRL6, + S2MU005_REG_CHGR_CTRL7, + S2MU005_REG_CHGR_CTRL8, + S2MU005_REG_CHGR_CTRL9, + S2MU005_REG_CHGR_CTRL10, + S2MU005_REG_CHGR_CTRL11, + S2MU005_REG_CHGR_CTRL12, + S2MU005_REG_CHGR_CTRL13, + S2MU005_REG_CHGR_CTRL14, + S2MU005_REG_CHGR_CTRL15, + S2MU005_REG_CHGR_CTRL16, + S2MU005_REG_CHGR_CTRL17, + S2MU005_REG_CHGR_CTRL18, + S2MU005_REG_CHGR_CTRL19, + S2MU005_REG_CHGR_TEST0, + S2MU005_REG_CHGR_TEST1, + S2MU005_REG_CHGR_TEST2, + S2MU005_REG_CHGR_TEST3, + S2MU005_REG_CHGR_TEST4, + S2MU005_REG_CHGR_TEST5, + S2MU005_REG_CHGR_TEST6, + S2MU005_REG_CHGR_TEST7, + S2MU005_REG_CHGR_TEST8, + S2MU005_REG_CHGR_TEST9, + S2MU005_REG_CHGR_TEST10, + + S2MU005_REG_FLED_STATUS, + S2MU005_REG_FLED_CH0_CTRL0, + S2MU005_REG_FLED_CH0_CTRL1, + S2MU005_REG_FLED_CH0_CTRL2, + S2MU005_REG_FLED_CH0_CTRL3, + S2MU005_REG_FLED_CH1_CTRL0, + S2MU005_REG_FLED_CH1_CTRL1, + S2MU005_REG_FLED_CH1_CTRL2, + S2MU005_REG_FLED_CH1_CTRL3, + S2MU005_REG_FLED_CTRL0, + S2MU005_REG_FLED_CTRL1, + S2MU005_REG_FLED_CTRL2, + S2MU005_REG_FLED_CTRL3, + S2MU005_REG_FLED_CTRL4, + S2MU005_REG_FLED_CTRL5, + S2MU005_REG_FLED_CTRL6, + + S2MU005_REG_RGB_EN, + S2MU005_REG_RGB_CH0_CTRL, + S2MU005_REG_RGB_CH1_CTRL, + S2MU005_REG_RGB_CH2_CTRL, + S2MU005_REG_RGB_CH0_RAMP, + S2MU005_REG_RGB_CH0_STAY, + S2MU005_REG_RGB_CH1_RAMP, + S2MU005_REG_RGB_CH1_STAY, + S2MU005_REG_RGB_CH2_RAMP, + S2MU005_REG_RGB_CH2_STAY, + S2MU005_REG_RGB_TEST0, + S2MU005_REG_RGB_CTRL0, + + S2MU005_REG_MUIC_ADC, + S2MU005_REG_MUIC_DEV1, + S2MU005_REG_MUIC_DEV2, + S2MU005_REG_MUIC_DEV3, + S2MU005_REG_MUIC_BUTTON1, + S2MU005_REG_MUIC_BUTTON2, + S2MU005_REG_MUIC_RESET, + S2MU005_REG_MUIC_CHGTYPE, + S2MU005_REG_MUIC_DEVAPPLE, + S2MU005_REG_MUIC_BCDRESCAN, + S2MU005_REG_MUIC_TEST1, + S2MU005_REG_MUIC_TEST2, + S2MU005_REG_MUIC_TEST3, + + S2MU005_REG_ID =3D 0x73, + + S2MU005_REG_MUIC_CTRL1 =3D 0xb2, + S2MU005_REG_MUIC_TIMERSET1, + S2MU005_REG_MUIC_TIMERSET2, + S2MU005_REG_MUIC_SWCTRL, + S2MU005_REG_MUIC_TIMERSET3, + S2MU005_REG_MUIC_CTRL2, + S2MU005_REG_MUIC_CTRL3, + + S2MU005_REG_MUIC_LDOADC_L =3D 0xbf, + S2MU005_REG_MUIC_LDOADC_H, +}; + +#define S2MU005_REG_FLED_CH_CTRL0(x) (S2MU005_REG_FLED_CH0_CTRL0 + 4 * (x)) +#define S2MU005_REG_FLED_CH_CTRL1(x) (S2MU005_REG_FLED_CH0_CTRL1 + 4 * (x)) +#define S2MU005_REG_FLED_CH_CTRL2(x) (S2MU005_REG_FLED_CH0_CTRL2 + 4 * (x)) +#define S2MU005_REG_FLED_CH_CTRL3(x) (S2MU005_REG_FLED_CH0_CTRL3 + 4 * (x)) + +#define S2MU005_REG_RGB_CH_CTRL(x) (S2MU005_REG_RGB_CH0_CTRL + 1 * (x)) +#define S2MU005_REG_RGB_CH_RAMP(x) (S2MU005_REG_RGB_CH0_RAMP + 2 * (x)) +#define S2MU005_REG_RGB_CH_STAY(x) (S2MU005_REG_RGB_CH0_STAY + 2 * (x)) + +/* S2MU005_REG_CHGR_STATUS0 */ +#define S2MU005_CHGR_VBUS BIT(7) +#define S2MU005_CHGR_WCIN BIT(6) +#define S2MU005_CHGR_VMID BIT(5) +#define S2MU005_CHGR_CHG BIT(4) +#define S2MU005_CHGR_STAT GENMASK(3, 0) + +#define S2MU005_CHGR_STAT_DONE 8 +#define S2MU005_CHGR_STAT_TOPOFF 7 +#define S2MU005_CHGR_STAT_DONE_FLAG 6 +#define S2MU005_CHGR_STAT_CV 5 +#define S2MU005_CHGR_STAT_CC 4 +#define S2MU005_CHGR_STAT_COOL_CHG 3 +#define S2MU005_CHGR_STAT_PRE_CHG 2 + +/* S2MU005_REG_CHGR_STATUS1 */ +#define S2MU005_CHGR_DETBAT BIT(7) +#define S2MU005_CHGR_VBUS_OVP GENMASK(6, 4) + +#define S2MU005_CHGR_VBUS_OVP_OVERVOLT 2 + +/* S2MU005_REG_CHGR_STATUS2 */ +#define S2MU005_CHGR_BAT GENMASK(6, 4) + +#define S2MU005_CHGR_BAT_VOLT_DET 7 +#define S2MU005_CHGR_BAT_FAST_CHG_DET 6 +#define S2MU005_CHGR_BAT_COOL_CHG_DET 5 +#define S2MU005_CHGR_BAT_LOW_CHG 2 +#define S2MU005_CHGR_BAT_SELF_DISCHG 1 +#define S2MU005_CHGR_BAT_OVP_DET 0 + +/* S2MU005_REG_CHGR_STATUS3 */ +#define S2MU005_CHGR_EVT GENMASK(3, 0) + +#define S2MU005_CHGR_EVT_WDT_RST 6 +#define S2MU005_CHGR_EVT_WDT_SUSP 5 +#define S2MU005_CHGR_EVT_VSYS_VUVLO 4 +#define S2MU005_CHGR_EVT_VSYS_VOVP 3 +#define S2MU005_CHGR_EVT_THERM_FOLDBACK 2 +#define S2MU005_CHGR_EVT_THERM_SHUTDOWN 1 + +/* S2MU005_REG_CHGR_CTRL0 */ +#define S2MU005_CHGR_CHG_EN BIT(4) +#define S2MU005_CHGR_OP_MODE GENMASK(2, 0) + +#define S2MU005_CHGR_OP_MODE_OTG BIT(2) +#define S2MU005_CHGR_OP_MODE_CHG BIT(1) + +/* S2MU005_REG_CHGR_CTRL1 */ +#define S2MU005_CHGR_VIN_DROP GENMASK(6, 4) + +/* S2MU005_REG_CHGR_CTRL2 */ +#define S2MU005_CHGR_IN_CURR_LIM GENMASK(5, 0) + +/* S2MU005_REG_CHGR_CTRL4 */ +#define S2MU005_CHGR_OTG_OCP_ON BIT(5) +#define S2MU005_CHGR_OTG_OCP_OFF BIT(4) +#define S2MU005_CHGR_OTG_OCP GENMASK(3, 2) +#define S2MU005_CHGR_OTG_OCP_1P5A 0x3 + +/* S2MU005_REG_CHGR_CTRL5 */ +#define S2MU005_CHGR_VMID_BOOST GENMASK(4, 0) +#define S2MU005_CHGR_VMID_BOOST_5P1V 0x16 + +/* S2MU005_REG_CHGR_CTRL6 */ +#define S2MU005_CHGR_COOL_CHG_CURR GENMASK(5, 0) + +/* S2MU005_REG_CHGR_CTRL7 */ +#define S2MU005_CHGR_FAST_CHG_CURR GENMASK(5, 0) + +/* S2MU005_REG_CHGR_CTRL8 */ +#define S2MU005_CHGR_VF_VBAT GENMASK(6, 1) + +/* S2MU005_REG_CHGR_CTRL10 */ +#define S2MU005_CHGR_TOPOFF_CURR(x) (GENMASK(3, 0) << 4 * (x)) + +/* S2MU005_REG_CHGR_CTRL11 */ +#define S2MU005_CHGR_OSC_BOOST GENMASK(6, 5) +#define S2MU005_CHGR_OSC_BUCK GENMASK(4, 3) +#define S2MU005_CHGR_OSC_BOOST_2MHZ 0x3 + +/* S2MU005_REG_CHGR_CTRL12 */ +#define S2MU005_CHGR_WDT GENMASK(2, 0) + +#define S2MU005_CHGR_WDT_ON BIT(2) +#define S2MU005_CHGR_WDT_OFF BIT(1) + +/* S2MU005_REG_CHGR_CTRL15 */ +#define S2MU005_CHGR_OTG_EN GENMASK(3, 2) +#define S2MU005_CHGR_OTG_EN_ON 0x3 + +/* S2MU005_REG_FLED_STATUS */ +#define S2MU005_FLED_FLASH_STATUS(x) (BIT(7) >> 2 * (x)) +#define S2MU005_FLED_TORCH_STATUS(x) (BIT(6) >> 2 * (x)) + +/* S2MU005_REG_FLED_CHx_CTRL0 */ +#define S2MU005_FLED_FLASH_IOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CHx_CTRL1 */ +#define S2MU005_FLED_TORCH_IOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CHx_CTRL2 */ +#define S2MU005_FLED_TORCH_TIMEOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CHx_CTRL3 */ +#define S2MU005_FLED_FLASH_TIMEOUT GENMASK(3, 0) + +/* S2MU005_REG_FLED_CTRL1 */ +#define S2MU005_FLED_CH_EN BIT(7) + +/* + * S2MU005_REG_FLED_CTRL4 - Rev. EVT0 + * S2MU005_REG_FLED_CTRL6 - Rev. EVT1 and later + */ +#define S2MU005_FLED_FLASH_EN(x) (GENMASK(7, 6) >> 4 * (x)) +#define S2MU005_FLED_TORCH_EN(x) (GENMASK(5, 4) >> 4 * (x)) + +/* S2MU005_REG_RGB_EN */ +#define S2MU005_RGB_RESET BIT(6) +#define S2MU005_RGB_SLOPE GENMASK(5, 0) + +#define S2MU005_RGB_SLOPE_CONST (BIT(4) | BIT(2) | BIT(0)) +#define S2MU005_RGB_SLOPE_SMOOTH (BIT(5) | BIT(3) | BIT(1)) + +/* S2MU005_REG_RGB_CHx_RAMP */ +#define S2MU005_RGB_CH_RAMP_UP GENMASK(7, 4) +#define S2MU005_RGB_CH_RAMP_DN GENMASK(3, 0) + +/* S2MU005_REG_RGB_CHx_STAY */ +#define S2MU005_RGB_CH_STAY_HI GENMASK(7, 4) +#define S2MU005_RGB_CH_STAY_LO GENMASK(3, 0) + +/* S2MU005_REG_MUIC_DEV1 */ +#define S2MU005_MUIC_OTG BIT(7) +#define S2MU005_MUIC_DCP BIT(6) +#define S2MU005_MUIC_CDP BIT(5) +#define S2MU005_MUIC_T1_T2_CHG BIT(4) +#define S2MU005_MUIC_UART BIT(3) +#define S2MU005_MUIC_SDP BIT(2) +#define S2MU005_MUIC_LANHUB BIT(1) +#define S2MU005_MUIC_AUDIO BIT(0) + +/* S2MU005_REG_MUIC_DEV2 */ +#define S2MU005_MUIC_SDP_1P8S BIT(7) +#define S2MU005_MUIC_AV BIT(6) +#define S2MU005_MUIC_TTY BIT(5) +#define S2MU005_MUIC_PPD BIT(4) +#define S2MU005_MUIC_JIG_UART_OFF BIT(3) +#define S2MU005_MUIC_JIG_UART_ON BIT(2) +#define S2MU005_MUIC_JIG_USB_OFF BIT(1) +#define S2MU005_MUIC_JIG_USB_ON BIT(0) + +/* S2MU005_REG_MUIC_DEV3 */ +#define S2MU005_MUIC_U200_CHG BIT(7) +#define S2MU005_MUIC_VBUS_AV BIT(4) +#define S2MU005_MUIC_VBUS_R255 BIT(1) +#define S2MU005_MUIC_MHL BIT(0) + +/* S2MU005_REG_MUIC_DEVAPPLE */ +#define S2MU005_MUIC_APPLE_CHG_0P5A BIT(7) +#define S2MU005_MUIC_APPLE_CHG_1P0A BIT(6) +#define S2MU005_MUIC_APPLE_CHG_2P0A BIT(5) +#define S2MU005_MUIC_APPLE_CHG_2P4A BIT(4) +#define S2MU005_MUIC_SDP_DCD_OUT BIT(3) +#define S2MU005_MUIC_RID_WAKEUP BIT(2) +#define S2MU005_MUIC_VBUS_WAKEUP BIT(1) +#define S2MU005_MUIC_BCV1P2_OR_OPEN BIT(0) + +/* S2MU005_REG_ID */ +#define S2MU005_ID_MASK GENMASK(3, 0) + +/* S2MU005_REG_MUIC_SWCTRL */ +#define S2MU005_MUIC_DM_DP GENMASK(7, 2) +#define S2MU005_MUIC_JIG BIT(0) + +#define S2MU005_MUIC_DM_DP_UART 0x12 +#define S2MU005_MUIC_DM_DP_USB 0x09 + +/* S2MU005_REG_MUIC_CTRL1 */ +#define S2MU005_MUIC_OPEN BIT(4) +#define S2MU005_MUIC_RAW_DATA BIT(3) +#define S2MU005_MUIC_MAN_SW BIT(2) +#define S2MU005_MUIC_WAIT BIT(1) +#define S2MU005_MUIC_IRQ BIT(0) + +/* S2MU005_REG_MUIC_CTRL3 */ +#define S2MU005_MUIC_ONESHOT_ADC BIT(2) + +/* S2MU005_REG_MUIC_LDOADC_L and S2MU005_REG_MUIC_LDOADC_H */ +#define S2MU005_MUIC_VSET GENMASK(4, 0) + +#define S2MU005_MUIC_VSET_3P0V 0x1f +#define S2MU005_MUIC_VSET_2P6V 0x0e +#define S2MU005_MUIC_VSET_2P4V 0x0c +#define S2MU005_MUIC_VSET_2P2V 0x0a +#define S2MU005_MUIC_VSET_2P0V 0x08 +#define S2MU005_MUIC_VSET_1P5V 0x03 +#define S2MU005_MUIC_VSET_1P4V 0x02 +#define S2MU005_MUIC_VSET_1P2V 0x00 + +#endif /* __LINUX_MFD_S2MU005_H */ --=20 2.53.0 From nobody Wed Jun 17 07:36:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 806B138CFE5; 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arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="TqEBPuSg" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id B3AE52675F; Thu, 23 Apr 2026 21:50:24 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id cHcNEIrNhiGI; Thu, 23 Apr 2026 21:50:24 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776973824; bh=IGWSMsR9l3YcM+vGFQnwqbuQBc1K81j9HFRpS0NQ6D4=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=TqEBPuSgtKzfQ8hr0Xp64VvOwkGPTQYd0rEnJU9RTObZoYBtoS3vtnZGNuduCTsIS J+XqrpfMYbX3yFJ9occHlsw44QYPZh44TkPlZuHypKbNxSS7skLNuvhh2Is7gfQGyR DcGX8CUOXRnd6gvsEYJEhlpC7mdfVzDNQzS4+qy/uLA2/ehr8R6/NB85yObufmQOzQ cQN6ODqw6oqwKy4kkmrcd+8h6mIPOAu6yNhxYna8+EXeQy3HkuvfPNZVdii8CX+06m rvF6B2nWDDZmd9eel5/JCibUSf7hVAB1HfCO8UAt3mjbRZ4aRCswDO8X5EDEPsB1ES hP/pcDQgVO7+Q== From: Kaustabh Chakraborty Date: Fri, 24 Apr 2026 01:09:04 +0530 Subject: [PATCH v5 05/11] mfd: sec: set DMA coherent mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260424-s2mu005-pmic-v5-5-fcbc9da5a004@disroot.org> References: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> In-Reply-To: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan , Nam Tran , =?utf-8?q?=C5=81ukasz_Lebiedzi=C5=84ski?= Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Kernel logs are filled with "DMA mask not set" messages for every sub-device. The device does not use DMA for communication, so these messages are useless. Disable the coherent DMA mask for the PMIC device, which is also propagated to sub-devices. Signed-off-by: Kaustabh Chakraborty --- drivers/mfd/sec-common.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/mfd/sec-common.c b/drivers/mfd/sec-common.c index ad1c7de83a620..afc9e691bb67c 100644 --- a/drivers/mfd/sec-common.c +++ b/drivers/mfd/sec-common.c @@ -215,6 +215,9 @@ int sec_pmic_probe(struct device *dev, int device_type,= unsigned int irq, if (IS_ERR(irq_data)) return PTR_ERR(irq_data); =20 + dev->coherent_dma_mask =3D 0; + dev->dma_mask =3D &dev->coherent_dma_mask; + pm_runtime_set_active(sec_pmic->dev); =20 switch (sec_pmic->device_type) { --=20 2.53.0 From nobody Wed Jun 17 07:36:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23BCC391E73; Thu, 23 Apr 2026 19:50:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776973834; cv=none; b=TAGrR1hDNYsA4NV3fsTxeg3MzEc8UTjKa6zSZCh2gGOiwSTirZc7MwDugtQbx2iDf/nwNDuvM55s8KyTA1YMEl4tzd8JnCo05KzFHXzFpB2SHk5Cz3XOyx5Vs17bj8KVM235eycOlAho0C8pYyELE2H7lD5m0ZYneIGAL8OMPd0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776973834; c=relaxed/simple; bh=SEkUWKgRpe6vdksyqBr5521jAeA/CZj1U2dwz0Gcgqw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bjK4KIcKKntN/5t8HbaJLjZTAufijxH7ET8P9JU2+FrStCIxHaaTWk1qAP26sLOsqZIyWnTweM56UOHX01hXEqr/c9JlsvEcqtaAXC1Up/xut4/tk22hJp+DRY5QL1EC+TM45ZhsOjYGp7fzvENbkOD9HNcs2wr4nhm+dKLD3p4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=ku9I2Uqu; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="ku9I2Uqu" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id BD62C26EC7; Thu, 23 Apr 2026 21:50:31 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 09-GytBVZI6t; Thu, 23 Apr 2026 21:50:31 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776973831; bh=SEkUWKgRpe6vdksyqBr5521jAeA/CZj1U2dwz0Gcgqw=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=ku9I2Uqu231RmaAEajc6DDXInOrULwY1JB0nSrhGRaEuee+j2X97vg6jlxd56pzFx NWU4zs4/1Z9cC3IOQDtNVz/+6fx9xHX1D+RkhdnSCcGeiXMxKMwjnSBafYxWZBjmTe g9TsahdsAPLMvwvWNhNuJ298gQNlp4d8rKYSdYW5iqNfIr+i9bSq+gDc9KIctjb12U Y7wSCP5RvRSMkS0QW0PfEbQldULBc8mBqW4HrHxkkzfDrSb7wpsaal8Y7STeYSoPmd quX2ccxMjPTD/WNlFU83MvQNYff2njR9vlMp+s/ASAGYM1EU9Kz+yve18ldT4lKI41 xGuKcmU5lqULA== From: Kaustabh Chakraborty Date: Fri, 24 Apr 2026 01:09:05 +0530 Subject: [PATCH v5 06/11] mfd: sec: resolve PMIC revision in S2MU005 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260424-s2mu005-pmic-v5-6-fcbc9da5a004@disroot.org> References: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> In-Reply-To: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan , Nam Tran , =?utf-8?q?=C5=81ukasz_Lebiedzi=C5=84ski?= Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty In devices other than S2MPG1X, the revision can be retrieved from the first register of the PMIC regmap. In S2MU005 however, the location is in offset 0x73. Introduce a switch-case block to allow selecting the REG_ID register. S2MU005 also has a field mask for the revision. Apply it using FIELD_GET() and get the extracted value. Signed-off-by: Kaustabh Chakraborty --- drivers/mfd/sec-common.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/mfd/sec-common.c b/drivers/mfd/sec-common.c index afc9e691bb67c..fe92bc4a3dd26 100644 --- a/drivers/mfd/sec-common.c +++ b/drivers/mfd/sec-common.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -119,20 +120,25 @@ static const struct mfd_cell s2mu005_devs[] =3D { =20 static void sec_pmic_dump_rev(struct sec_pmic_dev *sec_pmic) { - unsigned int val; + unsigned int reg, mask, val; =20 - /* For s2mpg1x, the revision is in a different regmap */ switch (sec_pmic->device_type) { case S2MPG10: case S2MPG11: + /* For s2mpg1x, the revision is in a different regmap */ return; - default: + case S2MU005: + reg =3D S2MU005_REG_ID; + mask =3D S2MU005_ID_MASK; break; + default: + /* For other device types, REG_ID is always the first register. */ + reg =3D S2MPS11_REG_ID; + mask =3D ~0; } =20 - /* For each device type, the REG_ID is always the first register */ - if (!regmap_read(sec_pmic->regmap_pmic, S2MPS11_REG_ID, &val)) - dev_dbg(sec_pmic->dev, "Revision: 0x%x\n", val); + if (!regmap_read(sec_pmic->regmap_pmic, reg, &val)) + dev_dbg(sec_pmic->dev, "Revision: 0x%x\n", field_get(mask, val)); } =20 static void sec_pmic_configure(struct sec_pmic_dev *sec_pmic) --=20 2.53.0 From nobody Wed Jun 17 07:36:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F191D38E133; Thu, 23 Apr 2026 19:50:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776973842; cv=none; b=rxbc1b6lw7vM8SQfNglWcc8AcJxD48I4dnh6vaGWcE1Z5xmcKFAXkQuS2LcoGRDFIwToMaWmuFy54wA7izYcyVC1JzdOJVhw4nnVO4bLZZ5MfY6wDCxj7pOYgv/ersPgQkYvrKdf2JSvGhkrHET68xGBAJCxzEWu5/RwHQ9EUR8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776973842; c=relaxed/simple; bh=cfpbhpQNgGVhnRRMf4ZxWDpz78+RDImmD7OiBUAm+hA=; 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Thu, 23 Apr 2026 21:50:37 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776973837; bh=cfpbhpQNgGVhnRRMf4ZxWDpz78+RDImmD7OiBUAm+hA=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=FG5yY2jl8fE6Rz2oZwWYIabMo5KvT1kbFyJ/Ojuek+Kq+04AWIe9sDQXLhfZwzq+8 NJobiJpPid4Z4qE2xpi7at/N9WNJcCcirYawIbTfT50lJZv6oesMyOtsoj7vW5uNjX M0CfF5aMJ71XXoh7Yw23w4qsSEO1rK2nxDm3PoTPlXmCMBZIHi7KIytKxTgLgOizV1 mGPuQR+RKEgfwODF0sOzlie4w8Pf+FQOHFcuE3bybn9iOnwTfFLgd0XClmQA5liro+ gXdX+x7VIR6lfcrarx0Jup2ovYDm+YLM4p1kH6bxBtYDswpHZFnFUyvPy7hn9ZPlD1 3zHHcK5JcSX8w== From: Kaustabh Chakraborty Date: Fri, 24 Apr 2026 01:09:06 +0530 Subject: [PATCH v5 07/11] leds: flash: add support for Samsung S2M series PMIC flash LED device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260424-s2mu005-pmic-v5-7-fcbc9da5a004@disroot.org> References: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> In-Reply-To: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan , Nam Tran , =?utf-8?q?=C5=81ukasz_Lebiedzi=C5=84ski?= Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Add support for flash LEDs found in certain Samsung S2M series PMICs. The device has two channels for LEDs, typically for the back and front cameras in mobile devices. Both channels can be independently controlled, and can be operated in torch or flash modes. The driver includes initial support for the S2MU005 PMIC flash LEDs. Signed-off-by: Kaustabh Chakraborty --- drivers/leds/flash/Kconfig | 12 ++ drivers/leds/flash/Makefile | 1 + drivers/leds/flash/leds-s2m-flash.c | 358 ++++++++++++++++++++++++++++++++= ++++ 3 files changed, 371 insertions(+) diff --git a/drivers/leds/flash/Kconfig b/drivers/leds/flash/Kconfig index 5e08102a67841..be62e05277429 100644 --- a/drivers/leds/flash/Kconfig +++ b/drivers/leds/flash/Kconfig @@ -114,6 +114,18 @@ config LEDS_RT8515 To compile this driver as a module, choose M here: the module will be called leds-rt8515. =20 +config LEDS_S2M_FLASH + tristate "Samsung S2M series PMICs flash/torch LED support" + depends on LEDS_CLASS + depends on MFD_SEC_CORE + depends on V4L2_FLASH_LED_CLASS || !V4L2_FLASH_LED_CLASS + select REGMAP_IRQ + help + This option enables support for the flash/torch LEDs found in + certain Samsung S2M series PMICs, such as the S2MU005. It has + a LED channel dedicated for every physical LED. The LEDs can + be controlled in flash and torch modes. + config LEDS_SGM3140 tristate "LED support for the SGM3140" depends on V4L2_FLASH_LED_CLASS || !V4L2_FLASH_LED_CLASS diff --git a/drivers/leds/flash/Makefile b/drivers/leds/flash/Makefile index 712fb737a428e..44e6c1b4beb37 100644 --- a/drivers/leds/flash/Makefile +++ b/drivers/leds/flash/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_LEDS_MAX77693) +=3D leds-max77693.o obj-$(CONFIG_LEDS_QCOM_FLASH) +=3D leds-qcom-flash.o obj-$(CONFIG_LEDS_RT4505) +=3D leds-rt4505.o obj-$(CONFIG_LEDS_RT8515) +=3D leds-rt8515.o +obj-$(CONFIG_LEDS_S2M_FLASH) +=3D leds-s2m-flash.o obj-$(CONFIG_LEDS_SGM3140) +=3D leds-sgm3140.o obj-$(CONFIG_LEDS_SY7802) +=3D leds-sy7802.o obj-$(CONFIG_LEDS_TPS6131X) +=3D leds-tps6131x.o diff --git a/drivers/leds/flash/leds-s2m-flash.c b/drivers/leds/flash/leds-= s2m-flash.c new file mode 100644 index 0000000000000..177d23b432ce6 --- /dev/null +++ b/drivers/leds/flash/leds-s2m-flash.c @@ -0,0 +1,358 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Flash and Torch LED Driver for Samsung S2M series PMICs. + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * Copyright (c) 2026 Kaustabh Chakraborty + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_CHANNELS 2 + +struct s2m_led { + struct regmap *regmap; + struct led_classdev_flash fled; + struct v4l2_flash *v4l2_flash; + /* + * The mutex object prevents the concurrent access of flash control + * registers by the LED and V4L2 subsystems. + */ + struct mutex lock; + unsigned int reg_enable; + u8 channel; + u8 flash_brightness; + u8 flash_timeout; +}; + +static struct s2m_led *to_s2m_led(struct led_classdev_flash *fled) +{ + return container_of(fled, struct s2m_led, fled); +} + +static struct led_classdev_flash *to_s2m_fled(struct led_classdev *cdev) +{ + return container_of(cdev, struct led_classdev_flash, led_cdev); +} + +static int s2m_fled_flash_brightness_set(struct led_classdev_flash *fled, = u32 brightness) +{ + struct s2m_led *led =3D to_s2m_led(fled); + struct led_flash_setting *setting =3D &fled->brightness; + + led->flash_brightness =3D (brightness - setting->min) / setting->step; + + return 0; +} + +static int s2m_fled_flash_timeout_set(struct led_classdev_flash *fled, u32= timeout) +{ + struct s2m_led *led =3D to_s2m_led(fled); + struct led_flash_setting *setting =3D &fled->timeout; + + led->flash_timeout =3D (timeout - setting->min) / setting->step; + + return 0; +} + +#if IS_ENABLED(CONFIG_V4L2_FLASH_LED_CLASS) +static int s2m_fled_flash_external_strobe_set(struct v4l2_flash *v4l2_flas= h, bool enable) +{ + struct s2m_led *led =3D to_led(v4l2_flash->fled_cdev); + + mutex_lock(&led->lock); + + led->fled.ops->strobe_set(&led->fled, enable); + + mutex_unlock(&led->lock); + + return 0; +} + +static const struct v4l2_flash_ops s2m_fled_v4l2_flash_ops =3D { + .external_strobe_set =3D s2m_fled_flash_external_strobe_set, +}; +#else +static const struct v4l2_flash_ops s2m_fled_v4l2_flash_ops; +#endif + +static void s2m_fled_v4l2_flash_release(void *v4l2_flash) +{ + v4l2_flash_release(v4l2_flash); +} + +static int s2mu005_fled_torch_brightness_set(struct led_classdev *cdev, en= um led_brightness value) +{ + struct s2m_led *led =3D to_s2m_led(to_s2m_fled(cdev)); + int ret; + + mutex_lock(&led->lock); + + if (!value) { + ret =3D regmap_clear_bits(led->regmap, led->reg_enable, + S2MU005_FLED_TORCH_EN(led->channel)); + if (ret < 0) + dev_err(cdev->dev, "failed to disable torch LED\n"); + goto unlock; + } + + ret =3D regmap_update_bits(led->regmap, S2MU005_REG_FLED_CH_CTRL1(led->ch= annel), + S2MU005_FLED_TORCH_IOUT, + FIELD_PREP(S2MU005_FLED_TORCH_IOUT, value - 1)); + if (ret < 0) { + dev_err(cdev->dev, "failed to set torch current\n"); + goto unlock; + } + + ret =3D regmap_set_bits(led->regmap, led->reg_enable, S2MU005_FLED_TORCH_= EN(led->channel)); + if (ret < 0) { + dev_err(cdev->dev, "failed to enable torch LED\n"); + goto unlock; + } + +unlock: + mutex_unlock(&led->lock); + + return ret; +} + +static int s2mu005_fled_flash_strobe_set(struct led_classdev_flash *fled, = bool state) +{ + struct s2m_led *led =3D to_s2m_led(fled); + int ret; + + mutex_lock(&led->lock); + + ret =3D regmap_clear_bits(led->regmap, led->reg_enable, S2MU005_FLED_FLAS= H_EN(led->channel)); + if (ret < 0) { + dev_err(fled->led_cdev.dev, "failed to disable flash LED\n"); + goto unlock; + } + + if (!state) + goto unlock; + + ret =3D regmap_update_bits(led->regmap, S2MU005_REG_FLED_CH_CTRL0(led->ch= annel), + S2MU005_FLED_FLASH_IOUT, + FIELD_PREP(S2MU005_FLED_FLASH_IOUT, led->flash_brightness)); + if (ret < 0) { + dev_err(fled->led_cdev.dev, "failed to set flash brightness\n"); + goto unlock; + } + + ret =3D regmap_update_bits(led->regmap, S2MU005_REG_FLED_CH_CTRL3(led->ch= annel), + S2MU005_FLED_FLASH_TIMEOUT, + FIELD_PREP(S2MU005_FLED_FLASH_TIMEOUT, led->flash_timeout)); + if (ret < 0) { + dev_err(fled->led_cdev.dev, "failed to set flash timeout\n"); + goto unlock; + } + + ret =3D regmap_set_bits(led->regmap, led->reg_enable, S2MU005_FLED_FLASH_= EN(led->channel)); + if (ret < 0) { + dev_err(fled->led_cdev.dev, "failed to enable flash LED\n"); + goto unlock; + } + +unlock: + mutex_unlock(&led->lock); + + return 0; +} + +static int s2mu005_fled_flash_strobe_get(struct led_classdev_flash *fled, = bool *state) +{ + struct s2m_led *led =3D to_s2m_led(fled); + u32 val; + int ret; + + mutex_lock(&led->lock); + + ret =3D regmap_read(led->regmap, S2MU005_REG_FLED_STATUS, &val); + if (ret < 0) { + dev_err(fled->led_cdev.dev, "failed to fetch LED status"); + goto unlock; + } + + *state =3D !!(val & S2MU005_FLED_FLASH_STATUS(led->channel)); + +unlock: + mutex_unlock(&led->lock); + + return ret; +} + +static const struct led_flash_ops s2mu005_fled_flash_ops =3D { + .flash_brightness_set =3D s2m_fled_flash_brightness_set, + .timeout_set =3D s2m_fled_flash_timeout_set, + .strobe_set =3D s2mu005_fled_flash_strobe_set, + .strobe_get =3D s2mu005_fled_flash_strobe_get, +}; + +static int s2mu005_fled_init(struct s2m_led *led, struct device *dev, stru= ct regmap *regmap, + unsigned int nr_channels) +{ + unsigned int val; + int i, ret; + + /* Enable the LED channels. */ + ret =3D regmap_set_bits(regmap, S2MU005_REG_FLED_CTRL1, S2MU005_FLED_CH_E= N); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to enable LED channels\n"); + + ret =3D regmap_read(regmap, S2MU005_REG_ID, &val); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to read revision\n"); + + for (i =3D 0; i < nr_channels; i++) { + /* + * Read the revision register. Revision EVT0 has the register + * at CTRL4, while EVT1 and higher have it at CTRL6. + */ + if (FIELD_GET(S2MU005_ID_MASK, val) =3D=3D 0) + led[i].reg_enable =3D S2MU005_REG_FLED_CTRL4; + else + led[i].reg_enable =3D S2MU005_REG_FLED_CTRL6; + } + + return 0; +} + +static int s2mu005_fled_init_channel(struct s2m_led *led, struct device *d= ev, + struct fwnode_handle *fwnp) +{ + struct led_classdev *cdev =3D &led->fled.led_cdev; + struct led_init_data init_data =3D {}; + struct v4l2_flash_config v4l2_cfg =3D {}; + int ret; + + cdev->max_brightness =3D 16; + cdev->brightness_set_blocking =3D s2mu005_fled_torch_brightness_set; + cdev->flags |=3D LED_DEV_CAP_FLASH; + + led->fled.timeout.min =3D 62000; + led->fled.timeout.step =3D 62000; + led->fled.timeout.max =3D 992000; + led->fled.timeout.val =3D 992000; + + led->fled.brightness.min =3D 25000; + led->fled.brightness.step =3D 25000; + led->fled.brightness.max =3D 375000; /* 400000 causes flickering */ + led->fled.brightness.val =3D 375000; + + s2m_fled_flash_timeout_set(&led->fled, led->fled.timeout.val); + s2m_fled_flash_brightness_set(&led->fled, led->fled.brightness.val); + + led->fled.ops =3D &s2mu005_fled_flash_ops; + + init_data.fwnode =3D fwnp; + ret =3D devm_led_classdev_flash_register_ext(dev, &led->fled, &init_data); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to create LED flash device\n"); + + v4l2_cfg.intensity.min =3D led->fled.timeout.min; + v4l2_cfg.intensity.step =3D led->fled.timeout.step; + v4l2_cfg.intensity.max =3D led->fled.timeout.max; + v4l2_cfg.intensity.val =3D led->fled.timeout.val; + + v4l2_cfg.has_external_strobe =3D true; + + led->v4l2_flash =3D v4l2_flash_init(dev, fwnp, &led->fled, &s2m_fled_v4l2= _flash_ops, + &v4l2_cfg); + if (IS_ERR(led->v4l2_flash)) { + v4l2_flash_release(led->v4l2_flash); + return dev_err_probe(dev, PTR_ERR(led->v4l2_flash), + "failed to create V4L2 flash device\n"); + } + + ret =3D devm_add_action_or_reset(dev, (void *)s2m_fled_v4l2_flash_release= , led->v4l2_flash); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to add cleanup action\n"); + + return 0; +} + +static int s2m_fled_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sec_pmic_dev *ddata =3D dev_get_drvdata(dev->parent); + struct s2m_led *led; + int ret; + + led =3D devm_kzalloc(dev, sizeof(*led) * MAX_CHANNELS, GFP_KERNEL); + if (!led) + return -ENOMEM; + + switch (platform_get_device_id(pdev)->driver_data) { + case S2MU005: + ret =3D s2mu005_fled_init(led, dev, ddata->regmap_pmic, MAX_CHANNELS); + if (ret) + return ret; + break; + default: + return dev_err_probe(dev, -ENODEV, "device type %d is not supported by d= river\n", + ddata->device_type); + } + + device_for_each_child_node_scoped(dev, child) { + u32 reg; + + if (fwnode_property_read_u32(child, "reg", ®)) + continue; + + if (led[reg].regmap) { + dev_warn(dev, "duplicate node for channel %d\n", reg); + continue; + } + + led[reg].regmap =3D ddata->regmap_pmic; + led[reg].channel =3D (u8)reg; + + ret =3D devm_mutex_init(dev, &led[reg].lock); + if (ret) + return dev_err_probe(dev, ret, "failed to create mutex\n"); + + switch (platform_get_device_id(pdev)->driver_data) { + case S2MU005: + ret =3D s2mu005_fled_init_channel(led + reg, dev, child); + if (ret < 0) + return ret; + break; + } + } + + return 0; +} + +static const struct platform_device_id s2m_fled_id_table[] =3D { + { "s2mu005-flash", S2MU005 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, s2m_fled_id_table); + +static const struct of_device_id s2m_fled_of_match_table[] =3D { + { .compatible =3D "samsung,s2mu005-flash", .data =3D (void *)S2MU005 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, s2m_fled_of_match_table); + +static struct platform_driver s2m_fled_driver =3D { + .driver =3D { + .name =3D "s2m-flash", + }, + .probe =3D s2m_fled_probe, + .id_table =3D s2m_fled_id_table, +}; +module_platform_driver(s2m_fled_driver); + +MODULE_DESCRIPTION("Flash/Torch LED Driver For Samsung S2M Series PMICs"); +MODULE_AUTHOR("Kaustabh Chakraborty "); +MODULE_LICENSE("GPL"); --=20 2.53.0 From nobody Wed Jun 17 07:36:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23727397E8A; Thu, 23 Apr 2026 19:50:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776973848; cv=none; b=PDTLYBRMsVWfJAQzJO9BCFeVDlMbcjGoom/AGxbePqB06y3Fl32ypQUCV++BKNTPRXtMi87wi3PCUknFsdEgYcK4XmEqDThUkaMdWceE1mngsTxibQrmStkoPre6DOAcrqyoWMhug7bYDYNPncJmZqiGXmKUQO4ecAGtlrH80Ko= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776973848; c=relaxed/simple; bh=rsRkgbshtktSWvwQMo2NtEvUnQ6shzPQs4UCMeD9YAY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LzIMI6V0qKQGIIF4T1lGy9GOUDe7CTsC/uxfOueAlNBE8vJGmkXJg2OGLp8kW/FGXdb3BWeSb+EODzSjiEpXhJ8n0zuwqPJpEGf1g1JZrRRDc5pPbVJAm77+QWFUMjWHdRuV1t5UoXIxV+c85NOFX00B8fv8kacsKQlN1Ty88N8= ARC-Authentication-Results: i=1; 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s=mail; t=1776973843; bh=rsRkgbshtktSWvwQMo2NtEvUnQ6shzPQs4UCMeD9YAY=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=CruYKeGyxlFLAt5f7uEf1uFWIs6/Y3Eufh8dMIkabq2ri9tEMjRIqeBiXPqHDS761 XmB0Cii3pn8KK+Dq9V8PoF/YbLo5Oqcd1gF0okvgxvxjJxneGMWwcYepHJsVGgZWZA gXzDdwyTftrunjOyItMRCXA47Tu007aV7HMxaTAtARAwq6Rw3f3LV/rJ0G+eaCBfvX YuNzsvb3rpAAWJjWFTlDP/zyOB1ANA73B5rBAOSTq3SIVWn9YvVmuDR/WnwJzQnV1q rDSImEaC8M4zwJqAK1o6fp5/fd0Iu5VBuL5qATvchbauCcpf2aNVFEu+gTpAlcs8b0 Z8njkxQztcwQQ== From: Kaustabh Chakraborty Date: Fri, 24 Apr 2026 01:09:07 +0530 Subject: [PATCH v5 08/11] leds: rgb: add support for Samsung S2M series PMIC RGB LED device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260424-s2mu005-pmic-v5-8-fcbc9da5a004@disroot.org> References: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> In-Reply-To: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan , Nam Tran , =?utf-8?q?=C5=81ukasz_Lebiedzi=C5=84ski?= Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Add support for the RGB LEDs found in certain Samsung S2M series PMICs. The device has three LED channels, controlled as a single device. These LEDs are typically used as status indicators in mobile phones. The driver includes initial support for the S2MU005 PMIC RGB LEDs. Signed-off-by: Kaustabh Chakraborty --- drivers/leds/rgb/Kconfig | 11 + drivers/leds/rgb/Makefile | 1 + drivers/leds/rgb/leds-s2m-rgb.c | 446 ++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 458 insertions(+) diff --git a/drivers/leds/rgb/Kconfig b/drivers/leds/rgb/Kconfig index 28ef4c487367c..30051342f4e4d 100644 --- a/drivers/leds/rgb/Kconfig +++ b/drivers/leds/rgb/Kconfig @@ -75,6 +75,17 @@ config LEDS_QCOM_LPG =20 If compiled as a module, the module will be named leds-qcom-lpg. =20 +config LEDS_S2M_RGB + tristate "Samsung S2M series PMICs RGB LED support" + depends on LEDS_CLASS + depends on MFD_SEC_CORE + select REGMAP_IRQ + help + This option enables support for the S2MU005 RGB LEDs. These + devices have three LED channels, with 8-bit brightness control + for each channel. It's usually found in mobile phones as + status indicators. + config LEDS_MT6370_RGB tristate "LED Support for MediaTek MT6370 PMIC" depends on MFD_MT6370 diff --git a/drivers/leds/rgb/Makefile b/drivers/leds/rgb/Makefile index be45991f63f50..98050e1aa4255 100644 --- a/drivers/leds/rgb/Makefile +++ b/drivers/leds/rgb/Makefile @@ -6,4 +6,5 @@ obj-$(CONFIG_LEDS_LP5812) +=3D leds-lp5812.o obj-$(CONFIG_LEDS_NCP5623) +=3D leds-ncp5623.o obj-$(CONFIG_LEDS_PWM_MULTICOLOR) +=3D leds-pwm-multicolor.o obj-$(CONFIG_LEDS_QCOM_LPG) +=3D leds-qcom-lpg.o +obj-$(CONFIG_LEDS_S2M_RGB) +=3D leds-s2m-rgb.o obj-$(CONFIG_LEDS_MT6370_RGB) +=3D leds-mt6370-rgb.o diff --git a/drivers/leds/rgb/leds-s2m-rgb.c b/drivers/leds/rgb/leds-s2m-rg= b.c new file mode 100644 index 0000000000000..51d12f2ef762a --- /dev/null +++ b/drivers/leds/rgb/leds-s2m-rgb.c @@ -0,0 +1,446 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RGB LED Driver for Samsung S2M series PMICs. + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * Copyright (c) 2026 Kaustabh Chakraborty + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct s2m_rgb { + struct device *dev; + struct regmap *regmap; + struct led_classdev_mc mc; + enum sec_device_type device_type; + /* + * The mutex object prevents race conditions when evaluation and + * application of LED pattern state. + */ + struct mutex lock; + /* + * State variables representing the current LED pattern, these only to + * be accessed when lock is held. + */ + u8 ramp_up; + u8 ramp_dn; + u8 stay_hi; + u8 stay_lo; +}; + +static struct led_classdev_mc *to_s2m_mc(struct led_classdev *cdev) +{ + return container_of(cdev, struct led_classdev_mc, led_cdev); +} + +static struct s2m_rgb *to_s2m_rgb(struct led_classdev_mc *mc) +{ + return container_of(mc, struct s2m_rgb, mc); +} + +static const u32 s2mu005_rgb_lut_ramp[] =3D { + 0, 100, 200, 300, 400, 500, 600, 700, + 800, 1000, 1200, 1400, 1600, 1800, 2000, 2200, +}; + +static const u32 s2mu005_rgb_lut_stay_hi[] =3D { + 100, 200, 300, 400, 500, 750, 1000, 1250, + 1500, 1750, 2000, 2250, 2500, 2750, 3000, 3250, +}; + +static const u32 s2mu005_rgb_lut_stay_lo[] =3D { + 0, 500, 1000, 1500, 2000, 2500, 3000, 3500, + 4000, 4500, 5000, 6000, 7000, 8000, 10000, 12000, +}; + +static int s2mu005_rgb_apply_params(struct s2m_rgb *rgb) +{ + struct regmap *regmap =3D rgb->regmap; + unsigned int ramp_val =3D 0; + unsigned int stay_val =3D 0; + int ret; + int i; + + ramp_val |=3D FIELD_PREP(S2MU005_RGB_CH_RAMP_UP, rgb->ramp_up); + ramp_val |=3D FIELD_PREP(S2MU005_RGB_CH_RAMP_DN, rgb->ramp_dn); + + stay_val |=3D FIELD_PREP(S2MU005_RGB_CH_STAY_HI, rgb->stay_hi); + stay_val |=3D FIELD_PREP(S2MU005_RGB_CH_STAY_LO, rgb->stay_lo); + + ret =3D regmap_write(regmap, S2MU005_REG_RGB_EN, S2MU005_RGB_RESET); + if (ret < 0) { + dev_err(rgb->dev, "failed to reset RGB LEDs\n"); + return ret; + } + + for (i =3D 0; i < rgb->mc.num_colors; i++) { + ret =3D regmap_write(regmap, S2MU005_REG_RGB_CH_CTRL(i), + rgb->mc.subled_info[i].brightness); + if (ret < 0) { + dev_err(rgb->dev, "failed to set LED brightness\n"); + return ret; + } + + ret =3D regmap_write(regmap, S2MU005_REG_RGB_CH_RAMP(i), ramp_val); + if (ret < 0) { + dev_err(rgb->dev, "failed to set ramp timings\n"); + return ret; + } + + ret =3D regmap_write(regmap, S2MU005_REG_RGB_CH_STAY(i), stay_val); + if (ret < 0) { + dev_err(rgb->dev, "failed to set stay timings\n"); + return ret; + } + } + + ret =3D regmap_update_bits(regmap, S2MU005_REG_RGB_EN, S2MU005_RGB_SLOPE, + S2MU005_RGB_SLOPE_SMOOTH); + if (ret < 0) { + dev_err(rgb->dev, "failed to set ramp slope\n"); + return ret; + } + + return 0; +} + +static int s2mu005_rgb_reset_params(struct s2m_rgb *rgb) +{ + struct regmap *regmap =3D rgb->regmap; + int ret; + + ret =3D regmap_write(regmap, S2MU005_REG_RGB_EN, S2MU005_RGB_RESET); + if (ret < 0) { + dev_err(rgb->dev, "failed to reset RGB LEDs\n"); + return ret; + } + + rgb->ramp_up =3D 0; + rgb->ramp_dn =3D 0; + rgb->stay_hi =3D 0; + rgb->stay_lo =3D 0; + + return 0; +} + +static int s2m_rgb_lut_calc_timing(const u32 *lut, const size_t len, + const u32 req_time, u8 *idx) +{ + int lo =3D 0; + int hi =3D len - 2; + + /* Bounds checking */ + if (req_time < lut[0] || req_time > lut[len - 1]) + return -EINVAL; + + /* + * Perform a binary search to pick the best timing from the LUT. + * + * The search algorithm picks two consecutive elements of the + * LUT and tries to search the pair between which the requested + * time lies. + */ + while (lo <=3D hi) { + *idx =3D (lo + hi) / 2; + + if ((lut[*idx] <=3D req_time) && (req_time <=3D lut[*idx + 1])) + break; + + if ((req_time < lut[*idx]) && (req_time < lut[*idx + 1])) + hi =3D *idx - 1; + else + lo =3D *idx + 1; + } + + /* + * The searched timing is always less than the requested time. At + * times, the succeeding timing in the LUT is closer thus more + * accurate. Adjust the resulting value if that's the case. + */ + if (abs(req_time - lut[*idx]) > abs(lut[*idx + 1] - req_time)) + (*idx)++; + + return 0; +} + +static int s2m_rgb_pattern_set(struct led_classdev *cdev, struct led_patte= rn *pattern, + u32 len, int repeat) +{ + struct s2m_rgb *rgb =3D to_s2m_rgb(to_s2m_mc(cdev)); + const u32 *lut_ramp_up, *lut_ramp_dn, *lut_stay_hi, *lut_stay_lo; + size_t lut_ramp_up_len, lut_ramp_dn_len, lut_stay_hi_len, lut_stay_lo_len; + int brightness_peak =3D 0; + u32 time_hi =3D 0, time_lo =3D 0; + bool ramp_up_en, ramp_dn_en; + int ret; + int i; + + /* + * The typical pattern supported by this device can be + * represented with the following graph: + * + * 255 T ''''''-. .-'''''''-. + * | '. .' '. + * | \ / \ + * | '. .' '. + * | '-...........-' '- + * 0 +----------------------------------------------------> time (s) + * + * <---- HIGH ----><-- LOW --><-------- HIGH ---------> + * <-----><-------><---------><-------><-----><-------> + * stay_hi ramp_dn stay_lo ramp_up stay_hi ramp_dn + * + * There are two states, named HIGH and LOW. HIGH has a non-zero + * brightness level, while LOW is of zero brightness. The + * pattern provided should mention only one zero and non-zero + * brightness level. The hardware always starts the pattern from + * the HIGH state, as shown in the graph. + * + * The HIGH state can be divided in three somewhat equal timings: + * ramp_up, stay_hi, and ramp_dn. The LOW state has only one + * timing: stay_lo. + */ + + /* Only indefinitely looping patterns are supported. */ + if (repeat !=3D -1) + return -EINVAL; + + /* Pattern should consist of at least two tuples. */ + if (len < 2) + return -EINVAL; + + for (i =3D 0; i < len; i++) { + int brightness =3D pattern[i].brightness; + u32 delta_t =3D pattern[i].delta_t; + + if (brightness) { + /* + * The pattern shold define only one non-zero + * brightness in the HIGH state. The device + * doesn't have any provisions to handle + * multiple peak brightness levels. + */ + if (brightness_peak && brightness_peak !=3D brightness) + return -EINVAL; + + brightness_peak =3D brightness; + time_hi +=3D delta_t; + ramp_dn_en =3D !!delta_t; + } else { + time_lo +=3D delta_t; + ramp_up_en =3D !!delta_t; + } + } + + switch (rgb->device_type) { + case S2MU005: + lut_ramp_up =3D s2mu005_rgb_lut_ramp; + lut_ramp_up_len =3D ARRAY_SIZE(s2mu005_rgb_lut_ramp); + lut_ramp_dn =3D s2mu005_rgb_lut_ramp; + lut_ramp_dn_len =3D ARRAY_SIZE(s2mu005_rgb_lut_ramp); + lut_stay_hi =3D s2mu005_rgb_lut_stay_hi; + lut_stay_hi_len =3D ARRAY_SIZE(s2mu005_rgb_lut_stay_hi); + lut_stay_lo =3D s2mu005_rgb_lut_stay_lo; + lut_stay_lo_len =3D ARRAY_SIZE(s2mu005_rgb_lut_stay_lo); + break; + default: + /* execution shouldn't reach here */ + break; + } + + mutex_lock(&rgb->lock); + + /* + * The timings ramp_up, stay_hi, and ramp_dn of the HIGH state + * are roughly equal. Firstly, calculate and set timings for + * ramp_up and ramp_dn (making sure they're exactly equal). + */ + rgb->ramp_up =3D 0; + rgb->ramp_dn =3D 0; + + if (ramp_up_en) { + ret =3D s2m_rgb_lut_calc_timing(lut_ramp_up, lut_ramp_up_len, time_hi / = 3, + &rgb->ramp_up); + if (ret < 0) + goto param_fail; + } + + if (ramp_dn_en) { + ret =3D s2m_rgb_lut_calc_timing(lut_ramp_dn, lut_ramp_dn_len, time_hi / = 3, + &rgb->ramp_dn); + if (ret < 0) + goto param_fail; + } + + /* + * Subtract the allocated ramp timings from time_hi (and also + * making sure it doesn't underflow!). The remaining time is + * allocated to stay_hi. + */ + time_hi -=3D min(time_hi, lut_ramp_up[rgb->ramp_up]); + time_hi -=3D min(time_hi, lut_ramp_dn[rgb->ramp_dn]); + + ret =3D s2m_rgb_lut_calc_timing(lut_stay_hi, lut_stay_hi_len, time_hi, &r= gb->stay_hi); + if (ret < 0) + goto param_fail; + + ret =3D s2m_rgb_lut_calc_timing(lut_stay_lo, lut_stay_lo_len, time_lo, &r= gb->stay_lo); + if (ret < 0) + goto param_fail; + + led_mc_calc_color_components(&rgb->mc, brightness_peak); + switch (rgb->device_type) { + case S2MU005: + ret =3D s2mu005_rgb_apply_params(rgb); + break; + default: + /* execution shouldn't reach here */ + break; + } + if (ret < 0) + goto param_fail; + + mutex_unlock(&rgb->lock); + + return 0; + +param_fail: + rgb->ramp_up =3D 0; + rgb->ramp_dn =3D 0; + rgb->stay_hi =3D 0; + rgb->stay_lo =3D 0; + + mutex_unlock(&rgb->lock); + + return ret; +} + +static int s2m_rgb_pattern_clear(struct led_classdev *cdev) +{ + struct s2m_rgb *rgb =3D to_s2m_rgb(to_s2m_mc(cdev)); + int ret =3D 0; + + mutex_lock(&rgb->lock); + + switch (rgb->device_type) { + case S2MU005: + ret =3D s2mu005_rgb_reset_params(rgb); + break; + default: + /* execution shouldn't reach here */ + break; + } + + mutex_unlock(&rgb->lock); + + return ret; +} + +static int s2m_rgb_brightness_set(struct led_classdev *cdev, enum led_brig= htness value) +{ + struct s2m_rgb *rgb =3D to_s2m_rgb(to_s2m_mc(cdev)); + int ret =3D 0; + + if (!value) + return s2m_rgb_pattern_clear(cdev); + + mutex_lock(&rgb->lock); + + led_mc_calc_color_components(&rgb->mc, value); + switch (rgb->device_type) { + case S2MU005: + ret =3D s2mu005_rgb_apply_params(rgb); + break; + default: + /* execution shouldn't reach here */ + break; + } + + mutex_unlock(&rgb->lock); + + return ret; +} + +static struct mc_subled s2mu005_rgb_subled_info[] =3D { + { .channel =3D 0, .color_index =3D LED_COLOR_ID_BLUE }, + { .channel =3D 1, .color_index =3D LED_COLOR_ID_GREEN }, + { .channel =3D 2, .color_index =3D LED_COLOR_ID_RED }, +}; + +static int s2m_rgb_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sec_pmic_dev *pmic_drvdata =3D dev_get_drvdata(dev->parent); + struct s2m_rgb *rgb; + struct led_init_data init_data =3D {}; + int ret; + + rgb =3D devm_kzalloc(dev, sizeof(*rgb), GFP_KERNEL); + if (!rgb) + return -ENOMEM; + + platform_set_drvdata(pdev, rgb); + rgb->dev =3D dev; + rgb->regmap =3D pmic_drvdata->regmap_pmic; + rgb->device_type =3D platform_get_device_id(pdev)->driver_data; + + switch (rgb->device_type) { + case S2MU005: + rgb->mc.subled_info =3D s2mu005_rgb_subled_info; + rgb->mc.num_colors =3D ARRAY_SIZE(s2mu005_rgb_subled_info); + break; + default: + return dev_err_probe(dev, -ENODEV, "device type %d is not supported by d= river\n", + pmic_drvdata->device_type); + } + + rgb->mc.led_cdev.max_brightness =3D 255; + rgb->mc.led_cdev.brightness_set_blocking =3D s2m_rgb_brightness_set; + rgb->mc.led_cdev.pattern_set =3D s2m_rgb_pattern_set; + rgb->mc.led_cdev.pattern_clear =3D s2m_rgb_pattern_clear; + + ret =3D devm_mutex_init(dev, &rgb->lock); + if (ret) + return dev_err_probe(dev, ret, "failed to create mutex lock\n"); + + init_data.fwnode =3D of_fwnode_handle(dev->of_node); + ret =3D devm_led_classdev_multicolor_register_ext(dev, &rgb->mc, &init_da= ta); + if (ret < 0) + return dev_err_probe(dev, ret, "failed to create LED device\n"); + + return 0; +} + +static const struct platform_device_id s2m_rgb_id_table[] =3D { + { "s2mu005-rgb", S2MU005 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, s2m_rgb_id_table); + +static const struct of_device_id s2m_rgb_of_match_table[] =3D { + { .compatible =3D "samsung,s2mu005-rgb", .data =3D (void *)S2MU005 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, s2m_rgb_of_match_table); + +static struct platform_driver s2m_rgb_driver =3D { + .driver =3D { + .name =3D "s2m-rgb", + }, + .probe =3D s2m_rgb_probe, + .id_table =3D s2m_rgb_id_table, +}; +module_platform_driver(s2m_rgb_driver); + +MODULE_DESCRIPTION("RGB LED Driver For Samsung S2M Series PMICs"); +MODULE_AUTHOR("Kaustabh Chakraborty "); +MODULE_LICENSE("GPL"); --=20 2.53.0 From nobody Wed Jun 17 07:36:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEE592D6E66; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260424-s2mu005-pmic-v5-9-fcbc9da5a004@disroot.org> References: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> In-Reply-To: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan , Nam Tran , =?utf-8?q?=C5=81ukasz_Lebiedzi=C5=84ski?= Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Add documentation to describe how hardware patterns (as defined by the documentation of led-class-multicolor) are parsed and implemented by the Samsung S2M series PMIC RGB LED driver. Signed-off-by: Kaustabh Chakraborty --- Documentation/leds/index.rst | 1 + Documentation/leds/leds-s2m-rgb.rst | 60 +++++++++++++++++++++++++++++++++= ++++ 2 files changed, 61 insertions(+) diff --git a/Documentation/leds/index.rst b/Documentation/leds/index.rst index bebf440042787..23fa9ff7aaf4b 100644 --- a/Documentation/leds/index.rst +++ b/Documentation/leds/index.rst @@ -28,6 +28,7 @@ LEDs leds-lp5812 leds-mlxcpld leds-mt6370-rgb + leds-s2m-rgb leds-sc27xx leds-st1202 leds-qcom-lpg diff --git a/Documentation/leds/leds-s2m-rgb.rst b/Documentation/leds/leds-= s2m-rgb.rst new file mode 100644 index 0000000000000..4f89a8c89ea86 --- /dev/null +++ b/Documentation/leds/leds-s2m-rgb.rst @@ -0,0 +1,60 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Samsung S2M Series PMIC RGB LED Driver +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +Description +----------- + +The RGB LED on the S2M series PMIC hardware features a three-channel LED t= hat +is grouped together as a single device. Furthermore, it supports 8-bit +brightness control for each channel. This LED is typically used as a status +indicator in mobile devices. It also supports various parameters for hardw= are +patterns. + +The hardware pattern can be programmed using the "pattern" trigger, using = the +hw_pattern attribute. + +/sys/class/leds//repeat +---------------------------- + +The hardware supports only indefinitely repeating patterns. The repeat +attribute must be set to -1 for hardware patterns to function. + +/sys/class/leds//hw_pattern +-------------------------------- + +Specify a hardware pattern for the RGB LEDs. + +The pattern is a series of brightness levels and durations in milliseconds. +There should be only one non-zero brightness level. Unlike the results +described in leds-trigger-pattern, the transitions between on and off stat= es +are smoothed out by the hardware. + +Simple pattern:: + + "255 3000 0 1000" + + 255 -+ ''''''-. .-'''''''-. + | '. .' '. + | \ / \ + | '. .' '. + | '-.......-' '- + 0 -+-------+-------+-------+-------+-------+-------+--> time (s) + 0 1 2 3 4 5 6 + +As described in leds-trigger-pattern, it is also possible to use zero-leng= th +entries to disable the ramping mechanism. + +On-Off pattern:: + + "255 1000 255 0 0 1000 0 0" + + 255 -+ ------+ +-------+ +-------+ + | | | | | | + | | | | | | + | | | | | | + | +-------+ +-------+ +------- + 0 -+-------+-------+-------+-------+-------+-------+--> time (s) + 0 1 2 3 4 5 6 --=20 2.53.0 From nobody Wed Jun 17 07:36:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C00CF397E6A; Thu, 23 Apr 2026 19:50:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776973860; cv=none; b=dby9CKzVVN5SCzy70P/u4R79gJWitLpm4AYB+gt29SRFnERKbhKkxTtvaEVRO+9v6FBJLYGlw4IlKuDgEwyC6HR2HR9iHJKCQnutLNlLhxXCLRiwCoDeqZN0OLQDK8z5zV1Kf9d8sqGYLAZqy3QXPrbz08Lh3IEyy9Flu8UiO20= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776973860; c=relaxed/simple; bh=fDGy8zCbKZjuU7SUb4iiNUBbrbAOmp37dV9Iyi+Nb8M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ow6Wlzpcb39nmwR0T55QQ5qEmiO/+4ifIytvT80Y2HmmBQkAh+scYNjctAXxE8wiH0tRpbeUZPqh2YJug/zRGEOPjRTzxV1ukDZF+8OfO1eshhgaCpCX7G/Umx3k4HJWoLcQRFgy6vU/yhrRrDppOSxcppHDycNroddjUpVMKbQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=jeeBkK64; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="jeeBkK64" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 76653267CD; Thu, 23 Apr 2026 21:50:57 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id MwlpZ2QX9163; Thu, 23 Apr 2026 21:50:56 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776973856; bh=fDGy8zCbKZjuU7SUb4iiNUBbrbAOmp37dV9Iyi+Nb8M=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=jeeBkK64n2xe4lFTj6Wfx2lDJd8Jmu7aCfsPOfWmyfjmiXXpwSSNUfXl5s6xo8wle IVBiJta1Ua1Rq6ZV94yWw7gQCWVmlpPJETHFwM3Qdw7DCf3v9PdU+4whxTiAKHD2ob A3ijWVq2ryhm18FJ4fK+/ZVXKqyUrzkPacd+Z3j4DIC6HovrLFSf/7HHhBl2piDteC w0WsF2dMFFzBkQGs8KqA6vxVklZ/uZEdzZi6KdUP05K33Ob4+SDHFonkgaF1pVC15R 3HC3w2XMedm+Cn8rCtDI4YQLIq476RmwYDMKW149VF6U1jjQp+DeV9sxYgLTL4fF+2 FT2uSnoMqB9Bg== From: Kaustabh Chakraborty Date: Fri, 24 Apr 2026 01:09:09 +0530 Subject: [PATCH v5 10/11] extcon: add support for Samsung S2M series PMIC extcon devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260424-s2mu005-pmic-v5-10-fcbc9da5a004@disroot.org> References: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> In-Reply-To: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan , Nam Tran , =?utf-8?q?=C5=81ukasz_Lebiedzi=C5=84ski?= Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Add a driver for MUIC devices found in certain Samsung S2M series PMICs These are USB port accessory detectors. These devices report multiple cable states depending on the ID-GND resistance measured by an internal ADC. The driver includes initial support for the S2MU005 PMIC extcon. Signed-off-by: Kaustabh Chakraborty --- drivers/extcon/Kconfig | 10 ++ drivers/extcon/Makefile | 1 + drivers/extcon/extcon-s2m.c | 345 ++++++++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 356 insertions(+) diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig index 68d9df7d2dae0..19c712e591955 100644 --- a/drivers/extcon/Kconfig +++ b/drivers/extcon/Kconfig @@ -183,6 +183,16 @@ config EXTCON_RT8973A and switch that is optimized to protect low voltage system from abnormal high input voltage (up to 28V). =20 +config EXTCON_S2M + tristate "Samsung S2M series PMIC EXTCON support" + depends on MFD_SEC_CORE + select REGMAP_IRQ + help + This option enables support for MUIC devices found in certain + Samsung S2M series PMICs, such as the S2MU005. These devices + have internal ADCs measuring the ID-GND resistance, thereby + can be used as a USB port accessory detector. + config EXTCON_SM5502 tristate "Silicon Mitus SM5502/SM5504/SM5703 EXTCON support" depends on I2C diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile index 6482f2bfd6611..e3939786f3474 100644 --- a/drivers/extcon/Makefile +++ b/drivers/extcon/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_EXTCON_PALMAS) +=3D extcon-palmas.o obj-$(CONFIG_EXTCON_PTN5150) +=3D extcon-ptn5150.o obj-$(CONFIG_EXTCON_QCOM_SPMI_MISC) +=3D extcon-qcom-spmi-misc.o obj-$(CONFIG_EXTCON_RT8973A) +=3D extcon-rt8973a.o +obj-$(CONFIG_EXTCON_S2M) +=3D extcon-s2m.o obj-$(CONFIG_EXTCON_SM5502) +=3D extcon-sm5502.o obj-$(CONFIG_EXTCON_USB_GPIO) +=3D extcon-usb-gpio.o obj-$(CONFIG_EXTCON_USBC_CROS_EC) +=3D extcon-usbc-cros-ec.o diff --git a/drivers/extcon/extcon-s2m.c b/drivers/extcon/extcon-s2m.c new file mode 100644 index 0000000000000..e57031b0066bb --- /dev/null +++ b/drivers/extcon/extcon-s2m.c @@ -0,0 +1,345 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Extcon Driver for Samsung S2M series PMICs. + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * Copyright (C) 2026 Kaustabh Chakraborty + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct s2m_muic { + struct device *dev; + struct regmap *regmap; + struct extcon_dev *extcon; + struct s2m_muic_irq_data *irq_data; + const unsigned int *extcon_cable; + bool attached; +}; + +struct s2m_muic_irq_data { + const char *name; + int (*const handler)(struct s2m_muic *); + int irq; +}; + +static int s2mu005_muic_detach(struct s2m_muic *priv) +{ + int ret; + int i; + + ret =3D regmap_set_bits(priv->regmap, S2MU005_REG_MUIC_CTRL1, + S2MU005_MUIC_MAN_SW); + if (ret < 0) { + dev_err(priv->dev, "failed to disable manual switching\n"); + return ret; + } + + ret =3D regmap_set_bits(priv->regmap, S2MU005_REG_MUIC_CTRL3, + S2MU005_MUIC_ONESHOT_ADC); + if (ret < 0) { + dev_err(priv->dev, "failed to enable ADC oneshot mode\n"); + return ret; + } + + ret =3D regmap_clear_bits(priv->regmap, S2MU005_REG_MUIC_SWCTRL, ~0); + if (ret < 0) { + dev_err(priv->dev, "failed to clear switch control register\n"); + return ret; + } + + /* Find all set states and clear them */ + for (i =3D 0; priv->extcon_cable[i]; i++) { + unsigned int state =3D priv->extcon_cable[i]; + + if (extcon_get_state(priv->extcon, state) =3D=3D true) + extcon_set_state_sync(priv->extcon, state, false); + } + + priv->attached =3D false; + + return 0; +} + +static int s2mu005_muic_attach(struct s2m_muic *priv) +{ + unsigned int type; + int ret; + + /* If any device is already attached, detach it */ + if (priv->attached) { + s2mu005_muic_detach(priv); + msleep(100); + } + + ret =3D regmap_read(priv->regmap, S2MU005_REG_MUIC_DEV1, &type); + if (ret < 0) { + dev_err(priv->dev, "failed to read DEV1 register\n"); + return ret; + } + + /* + * All USB connections which require communication via its D+ + * and D- wires need it. + */ + if (type & (S2MU005_MUIC_OTG | S2MU005_MUIC_DCP | S2MU005_MUIC_SDP)) { + ret =3D regmap_update_bits(priv->regmap, S2MU005_REG_MUIC_SWCTRL, + S2MU005_MUIC_DM_DP, + FIELD_PREP(S2MU005_MUIC_DM_DP, + S2MU005_MUIC_DM_DP_USB)); + if (ret < 0) { + dev_err(priv->dev, "failed to configure DM/DP pins\n"); + return ret; + } + } + + /* + * For OTG connections, enable manual switching and ADC oneshot + * mode. Since the port will now be supplying power, the + * internal ADC (measuring the ID-GND resistance) is made to + * poll periodically for any changes, so as to prevent any + * damages due to power. + */ + if (type & S2MU005_MUIC_OTG) { + ret =3D regmap_clear_bits(priv->regmap, S2MU005_REG_MUIC_CTRL1, + S2MU005_MUIC_MAN_SW); + if (ret < 0) { + dev_err(priv->dev, "failed to enable manual switching\n"); + return ret; + } + + ret =3D regmap_clear_bits(priv->regmap, S2MU005_REG_MUIC_CTRL3, + S2MU005_MUIC_ONESHOT_ADC); + if (ret < 0) { + dev_err(priv->dev, "failed to disable ADC oneshot mode\n"); + return ret; + } + } + + switch (type) { + case S2MU005_MUIC_OTG: + dev_dbg(priv->dev, "USB OTG connection detected\n"); + extcon_set_state_sync(priv->extcon, EXTCON_USB_HOST, true); + priv->attached =3D true; + break; + case S2MU005_MUIC_CDP: + dev_dbg(priv->dev, "USB CDP connection detected\n"); + extcon_set_state_sync(priv->extcon, EXTCON_USB, true); + extcon_set_state_sync(priv->extcon, EXTCON_CHG_USB_CDP, true); + priv->attached =3D true; + break; + case S2MU005_MUIC_SDP: + dev_dbg(priv->dev, "USB SDP connection detected\n"); + extcon_set_state_sync(priv->extcon, EXTCON_USB, true); + extcon_set_state_sync(priv->extcon, EXTCON_CHG_USB_SDP, true); + priv->attached =3D true; + break; + case S2MU005_MUIC_DCP: + dev_dbg(priv->dev, "USB DCP connection detected\n"); + extcon_set_state_sync(priv->extcon, EXTCON_USB, true); + extcon_set_state_sync(priv->extcon, EXTCON_CHG_USB_DCP, true); + priv->attached =3D true; + break; + case S2MU005_MUIC_UART: + dev_dbg(priv->dev, "UART connection detected\n"); + extcon_set_state_sync(priv->extcon, EXTCON_JIG, true); + priv->attached =3D true; + break; + } + + if (!priv->attached) + dev_warn(priv->dev, "failed to recognize the device attached\n"); + + return ret; +} + +static int s2mu005_muic_init(struct s2m_muic *priv) +{ + int ret =3D 0; + + ret =3D regmap_update_bits(priv->regmap, S2MU005_REG_MUIC_LDOADC_L, + S2MU005_MUIC_VSET, + FIELD_PREP(S2MU005_MUIC_VSET, + S2MU005_MUIC_VSET_3P0V)); + if (ret < 0) { + dev_err(priv->dev, "failed to set internal ADC voltage regulator\n"); + return ret; + } + + ret =3D regmap_update_bits(priv->regmap, S2MU005_REG_MUIC_LDOADC_H, + S2MU005_MUIC_VSET, + FIELD_PREP(S2MU005_MUIC_VSET, + S2MU005_MUIC_VSET_3P0V)); + if (ret < 0) { + dev_err(priv->dev, "failed to set internal ADC voltage regulator\n"); + return ret; + } + + ret =3D regmap_clear_bits(priv->regmap, S2MU005_REG_MUIC_CTRL1, + S2MU005_MUIC_IRQ); + if (ret < 0) { + dev_err(priv->dev, "failed to enable MUIC interrupts\n"); + return ret; + } + + return s2mu005_muic_attach(priv); +} + +static const unsigned int s2mu005_muic_extcon_cable[] =3D { + EXTCON_USB, + EXTCON_USB_HOST, + EXTCON_CHG_USB_SDP, + EXTCON_CHG_USB_DCP, + EXTCON_CHG_USB_CDP, + EXTCON_JIG, + EXTCON_NONE, +}; + +static struct s2m_muic_irq_data s2mu005_muic_irq_data[] =3D { + { + .name =3D "attach", + .handler =3D s2mu005_muic_attach + }, { + .name =3D "detach", + .handler =3D s2mu005_muic_detach + }, { + /* sentinel */ + } +}; + +static irqreturn_t s2m_muic_irq_func(int virq, void *data) +{ + struct s2m_muic *priv =3D data; + const struct s2m_muic_irq_data *irq_data =3D priv->irq_data; + int ret; + int i; + + for (i =3D 0; irq_data[i].handler; i++) { + if (virq !=3D irq_data[i].irq) + continue; + + ret =3D irq_data[i].handler(priv); + if (ret < 0) + dev_err(priv->dev, "failed to handle interrupt for %s (%d)\n", + irq_data[i].name, ret); + break; + } + + return IRQ_HANDLED; +} + +static int s2m_muic_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sec_pmic_dev *pmic_drvdata =3D dev_get_drvdata(dev->parent); + struct s2m_muic *priv; + int ret; + int i; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + platform_set_drvdata(pdev, priv); + priv->dev =3D dev; + priv->regmap =3D pmic_drvdata->regmap_pmic; + + switch (platform_get_device_id(pdev)->driver_data) { + case S2MU005: + priv->extcon_cable =3D s2mu005_muic_extcon_cable; + priv->irq_data =3D s2mu005_muic_irq_data; + /* Initialize MUIC */ + ret =3D s2mu005_muic_init(priv); + break; + default: + return dev_err_probe(dev, -ENODEV, + "device type %d is not supported by driver\n", + pmic_drvdata->device_type); + } + if (ret < 0) + return dev_err_probe(dev, ret, "failed to initialize MUIC\n"); + + priv->extcon =3D devm_extcon_dev_allocate(dev, priv->extcon_cable); + if (IS_ERR(priv->extcon)) + return dev_err_probe(dev, PTR_ERR(priv->extcon), + "failed to allocate memory for extcon\n"); + + ret =3D devm_extcon_dev_register(dev, priv->extcon); + if (ret) + return dev_err_probe(dev, ret, "failed to register extcon device\n"); + + for (i =3D 0; priv->irq_data[i].handler; i++) { + int irq =3D platform_get_irq_byname_optional(pdev, + priv->irq_data[i].name); + if (irq =3D=3D -ENXIO) + continue; + if (irq <=3D 0) + return dev_err_probe(dev, -EINVAL, "failed to get IRQ %s\n", + priv->irq_data[i].name); + + priv->irq_data[i].irq =3D irq; + ret =3D devm_request_threaded_irq(dev, irq, NULL, + s2m_muic_irq_func, IRQF_ONESHOT, + priv->irq_data[i].name, priv); + if (ret) + return dev_err_probe(dev, ret, "failed to request IRQ\n"); + } + + return 0; +} + +static void s2m_muic_remove(struct platform_device *pdev) +{ + struct s2m_muic *priv =3D dev_get_drvdata(&pdev->dev); + + /* + * Disabling the MUIC device is important as it disables manual + * switching mode, thereby enabling auto switching mode. + * + * This is to ensure that when the board is powered off, it + * goes into LPM charging mode when a USB charger is connected. + */ + switch (platform_get_device_id(pdev)->driver_data) { + case S2MU005: + s2mu005_muic_detach(priv); + break; + } +} + +static const struct platform_device_id s2m_muic_id_table[] =3D { + { "s2mu005-muic", S2MU005 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, s2m_muic_id_table); + +static const struct of_device_id s2m_muic_of_match_table[] =3D { + { + .compatible =3D "samsung,s2mu005-muic", + .data =3D (void *)S2MU005, + }, { + /* sentinel */ + }, +}; +MODULE_DEVICE_TABLE(of, s2m_muic_of_match_table); + +static struct platform_driver s2m_muic_driver =3D { + .driver =3D { + .name =3D "s2m-muic", + }, + .probe =3D s2m_muic_probe, + .remove =3D s2m_muic_remove, + .id_table =3D s2m_muic_id_table, +}; +module_platform_driver(s2m_muic_driver); + +MODULE_DESCRIPTION("Extcon Driver For Samsung S2M Series PMICs"); +MODULE_AUTHOR("Kaustabh Chakraborty "); +MODULE_LICENSE("GPL"); --=20 2.53.0 From nobody Wed Jun 17 07:36:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1991B39769D; Thu, 23 Apr 2026 19:51:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776973870; cv=none; b=kRy5SpXj3Blx6Z+WqCJXTsKNl1HijNY1RX3tbIj3cutHs2LRWmaB5J0vO6/RVAwRyGDaeg7iOZlfSpwwma6Sg84qHdangzsIq/5FbQgOX+cSqKWQrvKIex6MjKG8kQTlj9VgL1n+C0C6Vv5qlESPMgvD9hs1Hannlt9owRSMNGQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776973870; c=relaxed/simple; bh=5N/CTSyzp4i9loObyhppJLQYxvuPtFpz0fmq5A2XMkA=; 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Thu, 23 Apr 2026 21:51:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776973864; bh=5N/CTSyzp4i9loObyhppJLQYxvuPtFpz0fmq5A2XMkA=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=jCTa0qGO1pAXjCXK6fMlYOsUeP6ciUjVjnP47LPt4reERkGmu6oBU3cSf39WQe/ie gy0z9DU+DsWysuRL/6sBVVI86QfvpWFda/qUltqbLN+OUvQ61EM4tZrknZDLHwWLpk uPUpddekO+oLHLByZmc58s8oAX/V1Eh/OcnG4TEZsrynAg10j/rjAxiAyfVMu+4AMY m/FCYqWfWVJ20Trz5xe2VlxdWPO2phhjxSaLF1F2svIakYrMT0tNV60NRg3mo8EweY O7DC+gsTy3/ox6yePUwUS7t1FWaAoC017uClSRqEu9bu2CWXzqK/ElLfM8MHNoUzes vEZFFZ2GO3uWw== From: Kaustabh Chakraborty Date: Fri, 24 Apr 2026 01:09:10 +0530 Subject: [PATCH v5 11/11] power: supply: add support for Samsung S2M series PMIC charger device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260424-s2mu005-pmic-v5-11-fcbc9da5a004@disroot.org> References: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> In-Reply-To: <20260424-s2mu005-pmic-v5-0-fcbc9da5a004@disroot.org> To: Lee Jones , Pavel Machek , Rob Herring , Krzysztof Kozlowski , Conor Dooley , MyungJoo Ham , Chanwoo Choi , Sebastian Reichel , Krzysztof Kozlowski , =?utf-8?q?Andr=C3=A9_Draszik?= , Alexandre Belloni , Jonathan Corbet , Shuah Khan , Nam Tran , =?utf-8?q?=C5=81ukasz_Lebiedzi=C5=84ski?= Cc: linux-leds@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-rtc@vger.kernel.org, linux-doc@vger.kernel.org, Kaustabh Chakraborty Add a driver for charger controllers found in certain Samsung S2M series PMICs. The driver has very basic support for the device, with only charger online reporting working, and USB 2.0 device negotiations working. The driver includes initial support for the S2MU005 PMIC charger. Co-developed-by: =C5=81ukasz Lebiedzi=C5=84ski Signed-off-by: =C5=81ukasz Lebiedzi=C5=84ski Signed-off-by: Kaustabh Chakraborty --- drivers/power/supply/Kconfig | 11 ++ drivers/power/supply/Makefile | 1 + drivers/power/supply/s2m-charger.c | 299 +++++++++++++++++++++++++++++++++= ++++ 3 files changed, 311 insertions(+) diff --git a/drivers/power/supply/Kconfig b/drivers/power/supply/Kconfig index 83392ed6a8da9..6270e6d16fbbb 100644 --- a/drivers/power/supply/Kconfig +++ b/drivers/power/supply/Kconfig @@ -856,6 +856,17 @@ config CHARGER_RK817 help Say Y to include support for Rockchip RK817 Battery Charger. =20 +config CHARGER_S2M + tristate "Samsung S2M series PMIC battery charger support" + depends on EXTCON_S2M + depends on MFD_SEC_CORE + select REGMAP_IRQ + help + This option enables support for charger devices found in + certain Samsung S2M series PMICs, such as the S2MU005. These + devices provide USB power supply information and also required + for USB OTG role switching. + config CHARGER_SMB347 tristate "Summit Microelectronics SMB3XX Battery Charger" depends on I2C diff --git a/drivers/power/supply/Makefile b/drivers/power/supply/Makefile index 7ee839dca7f33..738814650ea0f 100644 --- a/drivers/power/supply/Makefile +++ b/drivers/power/supply/Makefile @@ -107,6 +107,7 @@ obj-$(CONFIG_CHARGER_BQ25890) +=3D bq25890_charger.o obj-$(CONFIG_CHARGER_BQ25980) +=3D bq25980_charger.o obj-$(CONFIG_CHARGER_BQ256XX) +=3D bq256xx_charger.o obj-$(CONFIG_CHARGER_RK817) +=3D rk817_charger.o +obj-$(CONFIG_CHARGER_S2M) +=3D s2m-charger.o obj-$(CONFIG_CHARGER_SMB347) +=3D smb347-charger.o obj-$(CONFIG_CHARGER_TPS65090) +=3D tps65090-charger.o obj-$(CONFIG_CHARGER_TPS65217) +=3D tps65217_charger.o diff --git a/drivers/power/supply/s2m-charger.c b/drivers/power/supply/s2m-= charger.c new file mode 100644 index 0000000000000..b32cea55b8b04 --- /dev/null +++ b/drivers/power/supply/s2m-charger.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Battery Charger Driver for Samsung S2M series PMICs. + * + * Copyright (c) 2015 Samsung Electronics Co., Ltd + * Copyright (c) 2026 Kaustabh Chakraborty + * Copyright (c) 2026 =C5=81ukasz Lebiedzi=C5=84ski + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct s2m_chgr { + struct device *dev; + struct regmap *regmap; + struct power_supply *psy; + struct extcon_dev *extcon; + struct work_struct extcon_work; + struct notifier_block extcon_nb; +}; + +static int s2mu005_chgr_get_online(struct s2m_chgr *priv, int *value) +{ + u32 val; + int ret =3D 0; + + ret =3D regmap_read(priv->regmap, S2MU005_REG_CHGR_STATUS0, &val); + if (ret < 0) { + dev_err(priv->dev, "failed to read register (%d)\n", ret); + return ret; + } + + *value =3D !!(val & S2MU005_CHGR_CHG); + + return ret; +} + +static void s2mu005_chgr_get_usb_type(struct s2m_chgr *priv, int *value) +{ + if (extcon_get_state(priv->extcon, EXTCON_CHG_USB_CDP)) + *value =3D POWER_SUPPLY_USB_TYPE_CDP; + if (extcon_get_state(priv->extcon, EXTCON_CHG_USB_SDP)) + *value =3D POWER_SUPPLY_USB_TYPE_SDP; + if (extcon_get_state(priv->extcon, EXTCON_CHG_USB_DCP)) + *value =3D POWER_SUPPLY_USB_TYPE_DCP; + else + *value =3D POWER_SUPPLY_USB_TYPE_UNKNOWN; +} + +static int s2mu005_chgr_get_property(struct power_supply *psy, + enum power_supply_property psp, + union power_supply_propval *val) +{ + struct s2m_chgr *priv =3D power_supply_get_drvdata(psy); + int ret =3D 0; + + switch (psp) { + case POWER_SUPPLY_PROP_ONLINE: + ret =3D s2mu005_chgr_get_online(priv, &val->intval); + break; + case POWER_SUPPLY_PROP_USB_TYPE: + s2mu005_chgr_get_usb_type(priv, &val->intval); + break; + default: + return -EINVAL; + } + + return ret; +} + +static int s2mu005_chgr_mode_set_host(struct s2m_chgr *priv) +{ + int ret; + + /* set mode to OTG */ + ret =3D regmap_update_bits(priv->regmap, S2MU005_REG_CHGR_CTRL0, + S2MU005_CHGR_OP_MODE, + FIELD_PREP(S2MU005_CHGR_OP_MODE, + S2MU005_CHGR_OP_MODE_OTG)); + if (ret < 0) { + dev_err(priv->dev, "failed to set OTG mode (%d)\n", ret); + return ret; + } + + /* set boost frequency to 2MHz */ + ret =3D regmap_update_bits(priv->regmap, S2MU005_REG_CHGR_CTRL11, + S2MU005_CHGR_OSC_BOOST, + FIELD_PREP(S2MU005_CHGR_OSC_BOOST, + S2MU005_CHGR_OSC_BOOST_2MHZ)); + if (ret < 0) { + dev_err(priv->dev, "failed to set boost frequency (%d)\n", ret); + return ret; + } + + /* set OTG current limit to 1.5 A */ + ret =3D regmap_update_bits(priv->regmap, S2MU005_REG_CHGR_CTRL4, + S2MU005_CHGR_OTG_OCP, + FIELD_PREP(S2MU005_CHGR_OTG_OCP, + S2MU005_CHGR_OTG_OCP_1P5A)); + if (ret < 0) { + dev_err(priv->dev, "failed to set OTG current limit (%d)\n", ret); + return ret; + } + + /* VBUS switches are OFF when OTG over-current happens */ + ret =3D regmap_set_bits(priv->regmap, S2MU005_REG_CHGR_CTRL4, + S2MU005_CHGR_OTG_OCP_OFF); + if (ret < 0) { + dev_err(priv->dev, "failed to set OTG OCP switch (%d)\n", ret); + return ret; + } + + /* set OTG voltage to 5.1 V */ + ret =3D regmap_update_bits(priv->regmap, S2MU005_REG_CHGR_CTRL5, + S2MU005_CHGR_VMID_BOOST, + FIELD_PREP(S2MU005_CHGR_VMID_BOOST, + S2MU005_CHGR_VMID_BOOST_5P1V)); + if (ret < 0) { + dev_err(priv->dev, "failed to set OTG voltage (%d)\n", ret); + return ret; + } + + /* turn on OTG */ + ret =3D regmap_update_bits(priv->regmap, S2MU005_REG_CHGR_CTRL15, + S2MU005_CHGR_OTG_EN, + FIELD_PREP(S2MU005_CHGR_OTG_EN, + S2MU005_CHGR_OTG_EN_ON)); + if (ret < 0) + dev_err(priv->dev, "failed to turn on OTG (%d)\n", ret); + return ret; +} + +static int s2mu005_chgr_mode_set_charger(struct s2m_chgr *priv) +{ + int ret; + + /* first reset to mode 0 */ + ret =3D regmap_clear_bits(priv->regmap, S2MU005_REG_CHGR_CTRL0, + S2MU005_CHGR_OP_MODE); + if (ret < 0) { + dev_err(priv->dev, "failed to reset opmode (%d)\n", ret); + return ret; + } + + /* wait for the charger to settle before switching to charging mode */ + msleep(50); + /* then set to charging mode */ + ret =3D regmap_update_bits(priv->regmap, S2MU005_REG_CHGR_CTRL0, + S2MU005_CHGR_OP_MODE, + FIELD_PREP(S2MU005_CHGR_OP_MODE, + S2MU005_CHGR_OP_MODE_CHG)); + if (ret < 0) + dev_err(priv->dev, "failed to set opmode to charging (%d)\n", ret); + return ret; +} + +static int s2mu005_chgr_mode_unset(struct s2m_chgr *priv) +{ + int ret; + + /* turn off OTG */ + ret =3D regmap_clear_bits(priv->regmap, S2MU005_REG_CHGR_CTRL15, + S2MU005_CHGR_OTG_EN); + if (ret < 0) { + dev_err(priv->dev, "failed to turn off OTG (%d)\n", ret); + return ret; + } + + /* reset operation mode */ + ret =3D regmap_clear_bits(priv->regmap, S2MU005_REG_CHGR_CTRL0, + S2MU005_CHGR_OP_MODE); + if (ret < 0) + dev_err(priv->dev, "failed to reset opmode (%d)\n", ret); + return ret; +} + +static void s2mu005_chgr_extcon_work(struct work_struct *work) +{ + struct s2m_chgr *priv =3D container_of(work, struct s2m_chgr, extcon_work= ); + + if (extcon_get_state(priv->extcon, EXTCON_USB_HOST)) + s2mu005_chgr_mode_set_host(priv); + else if (extcon_get_state(priv->extcon, EXTCON_USB)) + s2mu005_chgr_mode_set_charger(priv); + else + s2mu005_chgr_mode_unset(priv); + + power_supply_changed(priv->psy); +} + +static const enum power_supply_property s2mu005_chgr_properties[] =3D { + POWER_SUPPLY_PROP_ONLINE, + POWER_SUPPLY_PROP_USB_TYPE, +}; + +static const struct power_supply_desc s2mu005_chgr_psy_desc =3D { + .name =3D "s2mu005-charger", + .type =3D POWER_SUPPLY_TYPE_USB, + .properties =3D s2mu005_chgr_properties, + .num_properties =3D ARRAY_SIZE(s2mu005_chgr_properties), + .get_property =3D s2mu005_chgr_get_property, + .usb_types =3D BIT(POWER_SUPPLY_USB_TYPE_CDP) | + BIT(POWER_SUPPLY_USB_TYPE_SDP) | + BIT(POWER_SUPPLY_USB_TYPE_DCP) | + BIT(POWER_SUPPLY_USB_TYPE_UNKNOWN), +}; + +static int s2m_chgr_extcon_notifier(struct notifier_block *nb, + unsigned long event, void *param) +{ + struct s2m_chgr *priv =3D container_of(nb, struct s2m_chgr, extcon_nb); + + schedule_work(&priv->extcon_work); + + return NOTIFY_OK; +} + +static int s2m_chgr_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct sec_pmic_dev *pmic_drvdata =3D dev_get_drvdata(dev->parent); + struct s2m_chgr *priv; + struct device_node *extcon_node __free(device_node) =3D NULL; + struct power_supply_config psy_cfg =3D {}; + const struct power_supply_desc *psy_desc; + work_func_t extcon_work_func; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + platform_set_drvdata(pdev, priv); + priv->dev =3D dev; + priv->regmap =3D pmic_drvdata->regmap_pmic; + + switch (platform_get_device_id(pdev)->driver_data) { + case S2MU005: + psy_desc =3D &s2mu005_chgr_psy_desc; + extcon_work_func =3D s2mu005_chgr_extcon_work; + break; + default: + return dev_err_probe(dev, -ENODEV, + "device type %d is not supported by driver\n", + pmic_drvdata->device_type); + } + + psy_cfg.drv_data =3D priv; + psy_cfg.fwnode =3D dev_fwnode(dev->parent); + priv->psy =3D devm_power_supply_register(dev, psy_desc, &psy_cfg); + if (IS_ERR(priv->psy)) + return dev_err_probe(dev, PTR_ERR(priv->psy), + "failed to register power supply subsystem\n"); + + /* MUIC is mandatory. If unavailable, request probe deferral */ + extcon_node =3D of_get_child_by_name(dev->parent->of_node, "muic"); + priv->extcon =3D extcon_find_edev_by_node(extcon_node); + if (IS_ERR(priv->extcon)) + return -EPROBE_DEFER; + + ret =3D devm_work_autocancel(dev, &priv->extcon_work, extcon_work_func); + if (ret) + return dev_err_probe(dev, ret, "failed to initialize extcon work\n"); + + priv->extcon_nb.notifier_call =3D s2m_chgr_extcon_notifier; + ret =3D devm_extcon_register_notifier_all(dev, priv->extcon, &priv->extco= n_nb); + if (ret) + dev_err_probe(dev, ret, "failed to register extcon notifier\n"); + + return 0; +} + +static const struct platform_device_id s2m_chgr_id_table[] =3D { + { "s2mu005-charger", S2MU005 }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, s2m_chgr_id_table); + +static struct platform_driver s2m_chgr_driver =3D { + .driver =3D { + .name =3D "s2m-charger", + }, + .probe =3D s2m_chgr_probe, + .id_table =3D s2m_chgr_id_table, +}; +module_platform_driver(s2m_chgr_driver); + +MODULE_DESCRIPTION("Battery Charger Driver For Samsung S2M Series PMICs"); +MODULE_AUTHOR("Kaustabh Chakraborty "); +MODULE_AUTHOR("=C5=81ukasz Lebiedzi=C5=84ski "); +MODULE_LICENSE("GPL"); --=20 2.53.0