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Thu, 23 Apr 2026 23:31:43 -0700 (PDT) Received: from hu-smankad-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c7977031729sm17754692a12.25.2026.04.23.23.31.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Apr 2026 23:31:43 -0700 (PDT) From: Sneh Mankad Date: Fri, 24 Apr 2026 12:01:24 +0530 Subject: [PATCH] pinctrl: qcom: Add irq_get/set_irqchip_state() for msm gpio irqchip Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260424-pinctrl_irqchip_states-v1-1-85286f078916@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIADsO62kC/x3MQQqAIBBA0avErBPKJKirRITYWANhNiMRhHdPW r7F/y8IMqHAWL3AeJPQGQraugK327ChorUYdKP7xmijIgWX+FiIL7dTXCTZhKKsReM77QffI5Q 4Mnp6/vE05/wB4xH6RmgAAAA= X-Change-ID: 20260424-pinctrl_irqchip_states-aae4f32f9f6e To: Bjorn Andersson , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Maulik Shah , Sneh Mankad X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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The msm gpio irqchip however do not implement this function making it impossible to replay the gpio interrupt on any MPM irqchip based SoC. Add the missing irq_get/set_irqchip_state() APIs. Implement only IRQCHIP_STATE_PENDING case which MPM irqchip uses. Signed-off-by: Maulik Shah Signed-off-by: Sneh Mankad --- drivers/pinctrl/qcom/pinctrl-msm.c | 39 ++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 39 insertions(+) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinc= trl-msm.c index 45b3a2763eb85405fecdd4770ba3d4ab684563f0..925fca82252413d8e21fb47a0cc= 3a9ade7d5fe67 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -1305,6 +1305,43 @@ static int msm_gpio_irq_set_affinity(struct irq_data= *d, return -EINVAL; } =20 +static int msm_gpio_irq_set_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool val) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl =3D gpiochip_get_data(gc); + const struct msm_pingroup *g =3D &pctrl->soc->groups[d->hwirq]; + + if (which !=3D IRQCHIP_STATE_PENDING) + return -EINVAL; + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return -EINVAL; + + msm_writel_intr_status(val, pctrl, g); + + return 0; +} + +static int msm_gpio_irq_get_irqchip_state(struct irq_data *d, + enum irqchip_irq_state which, bool *val) +{ + struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct msm_pinctrl *pctrl =3D gpiochip_get_data(gc); + const struct msm_pingroup *g =3D &pctrl->soc->groups[d->hwirq]; + + if (which !=3D IRQCHIP_STATE_PENDING) + return -EINVAL; + + if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) + return -EINVAL; + + g =3D &pctrl->soc->groups[d->hwirq]; + *val =3D msm_readl_intr_status(pctrl, g); + + return 0; +} + static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_i= nfo) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); @@ -1393,6 +1430,8 @@ static const struct irq_chip msm_gpio_irq_chip =3D { .irq_request_resources =3D msm_gpio_irq_reqres, .irq_release_resources =3D msm_gpio_irq_relres, .irq_set_affinity =3D msm_gpio_irq_set_affinity, + .irq_set_irqchip_state =3D msm_gpio_irq_set_irqchip_state, + .irq_get_irqchip_state =3D msm_gpio_irq_get_irqchip_state, .irq_set_vcpu_affinity =3D msm_gpio_irq_set_vcpu_affinity, .flags =3D (IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SET_TYPE_MASKED | --- base-commit: b4e07588e743c989499ca24d49e752c074924a9a change-id: 20260424-pinctrl_irqchip_states-aae4f32f9f6e Best regards, --=20 Sneh Mankad