From nobody Sun Jun 14 00:41:37 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CF09135CB89; Thu, 23 Apr 2026 14:57:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776956249; cv=none; b=rBV+RN/bRtuty/oPzKqnXQr4mYGvjlWHI9vcj9KT1Q3HkNneFXLukRS6wahwX+gsqD1qkV74MEGeDY8L4lOP4K6sa0rKCbVFn09+EZjRQxTlnkxpZdu4IrCHpt59Jb3mpo4U9t63GDUhblzYVYs6wxauO01Q0hgCZ6d0s0CPBEM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776956249; c=relaxed/simple; bh=1lCxQiOyX8NlNUlBXXqPzc/TAeshReaRt3/gRTPwcmk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OpQ2vYPZQx3ZWNY52RVPaAEHcDvrFf2tSexlcYJ9mHooIy31CWqzK/OVhHUn4tkwlBIo1YeQC/ei0kkJ22d6avmvHy4bpchPY407VfK7uT46JqBEkgTL+pHub3ZFgzMM4GHYzszNCYo/zZEMFy6RrCYvH5xTtZG/JyuxB9dXA4Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=o0upl1Sy; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="o0upl1Sy" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63N8uN7A1565720; Thu, 23 Apr 2026 14:57:24 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=rM7GAu+3vsO 6bUBWuQYh1+164AM80heJ0y1xmJjvzEI=; b=o0upl1Sywc8TbG4FGc5It00u9I7 dYNlbQY/xwkUXTQhqFSQKQWLyy/NzsMOh2tFAGHWNXLsppKlXMPQ+0qk76EeSYzP 9htqkjG4ppaOxX1wkJpmmmcWBOzVK0uxWyVdRJUvai6umHbGzqhy9t5QjhnJQjb/ 0Q6d7Si8p0kquohs52vohsmtuFOWA/DRs8cKSRXGWy9v/dAy/dtyiTaxWPaI+Pqe tGpZ0NXk4O3xjFdoV1l41Ne0aaZd/JczJHzRYGzS+uSpWxu2NaBIQQEv0a95H32q YlNqkNU1Zey2OrbSOcJE7OlM8ptdgXdovF+4EZ7pr0FXRIACiHpwFwEVDyQ== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dq16wvkfx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2026 14:57:23 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.7/8.18.1.7) with ESMTP id 63NEvJTJ010858; Thu, 23 Apr 2026 14:57:20 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 4dm31k24a9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2026 14:57:20 +0000 (GMT) Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.1.12) with ESMTP id 63NEvJsU010851; Thu, 23 Apr 2026 14:57:19 GMT Received: from hu-devc-hyd-u24-a.qualcomm.com (hu-msavaliy-hyd.qualcomm.com [10.147.246.140]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 63NEvJX7010848 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2026 14:57:19 +0000 (GMT) Received: by hu-devc-hyd-u24-a.qualcomm.com (Postfix, from userid 429934) id 1B59721C47; Thu, 23 Apr 2026 20:27:18 +0530 (+0530) From: Mukesh Kumar Savaliya To: viken.dadhaniya@oss.qualcomm.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, Frank.Li@kernel.org, andersson@kernel.org, konradybcio@kernel.org, dmitry.baryshkov@oss.qualcomm.com, linmq006@gmail.com, quic_jseerapu@quicinc.com, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Cc: krzysztof.kozlowski@oss.qualcomm.com, bartosz.golaszewski@oss.qualcomm.com, bjorn.andersson@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, Mukesh Kumar Savaliya Subject: [PATCH v7 1/4] dt-bindings: i2c: qcom,i2c-geni: Document multi-owner controller support Date: Thu, 23 Apr 2026 20:25:48 +0530 Message-ID: <20260423145705.545552-2-mukesh.savaliya@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com> References: <20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIzMDE0OSBTYWx0ZWRfXwVSasqSQacK2 vBhkENQd7WCXaAws6RAP9WjY8kG2w8hliA0dQm5rcUrM76fNh8McDy/2yvr8dMJC+qnX5G0pqdD 95xy2svL2pPAewtEL8PhZYxc+e3+yt3zuUS4DRnkNCNeT5NUN68P0KRukbKyWAQwiToKKFCH9lJ lkR2D/qVbyYRQ6REy4wBzOXQSRjJBwMLlBUiTbvhfaF0Z6mj7elab3+ZExtGQBTdCjM3bR83Adb sWCPYhNkIhsO1MCC7I3zKv4KXXq610doimtvgZUNezZ0YJUpN4/fQWDaSw7+d6nNpoWt/zjxj75 W40L0cCk8HN8OY1i3vz5/zEekgAYWOPdYBlAotj7Cggysxd36Ie3j/KrEMQA2RsbSF+5Nb7jY1V NS4Onwv+6pQjpYkHrUM1Mn/2Ipi5FmXOA9PBpfr8he3mdjPzNRgVpscjjvvSdrura977F6OPbII lC0YJK5SAxe4GHX45+A== X-Authority-Analysis: v=2.4 cv=dL+WXuZb c=1 sm=1 tr=0 ts=69ea3354 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=yG_STSell-aZfaz4LqIA:9 X-Proofpoint-GUID: AvTQKP4MHy-e4Uh3TqYYgjxSt41jbgqH X-Proofpoint-ORIG-GUID: AvTQKP4MHy-e4Uh3TqYYgjxSt41jbgqH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 spamscore=0 priorityscore=1501 malwarescore=0 adultscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604230149 Content-Type: text/plain; charset="utf-8" Document a DeviceTree property to describe QUP-based I2C controllers that are shared with one or more other system processors. On some Qualcomm platforms, a QUP-based I2C controller may be accessed by multiple system processors (for example, APPS and DSP). In such configurations, the operating system must not assume exclusive ownership of the controller or its associated hardware resources. The new qcom,qup-multi-owner property indicates that the controller is externally shared and that the operating system must avoid operations which rely on sole control of the hardware. Acked-by: Rob Herring (Arm) Signed-off-by: Mukesh Kumar Savaliya --- .../devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml = b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml index 51534953a69c..9401dc2d5052 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml @@ -60,6 +60,13 @@ properties: power-domains: maxItems: 1 =20 + qcom,qup-multi-owner: + type: boolean + description: + Indicates that the QUP-based controller is shared with one or more + other system processors and must not be assumed to have exclusive + ownership by the operating system. + reg: maxItems: 1 =20 --=20 2.43.0 From nobody Sun Jun 14 00:41:37 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07402356A38; Thu, 23 Apr 2026 14:57:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776956252; cv=none; b=OnhBb2y+RMk/gLCRlgxUTtZgGbmiaaBiaPUHbiaIvA6ltCb5g6eURloVtzxIJfKqS7TPZpYjwtMqP/4mZY9wrjpMb83ASL5kKPDzojtRP1ThKs9EvW/sRfC9NSfpj0tWKcqOpfjAbLT47PBRgRsUGLiT2hkWOcj63tJD1x87acg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776956252; c=relaxed/simple; bh=uTb32AlKUMSsaMjCNRPHfgllDmLNV1GMGVEGJsim/44=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=V9FmZum5MrnplU5fhtd6egQtEv1zEXHMbYVV7TLjezO6fa9wG0bxGNIza5ONBzPTrs2Bxl1SQ/TaPBXAJf/1tin+ewk7C+n0qzFbxLTMLOHHA8CBxIJ16GZHjM67WQ9Lv8pfG5VvTY9OqpTCUf1uflIQ4qsHRJUrM5to/LKK0zM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=OEmdG6wP; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="OEmdG6wP" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63N8uEOb3044044; Thu, 23 Apr 2026 14:57:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=GIpI3/sbwCq vsOS1v8tVH3O7wzjYPHgHjDmdIJ9+LoQ=; b=OEmdG6wPPPIscMkPr4QnqbIqE+O +y/2K3E/ek3UkWQzapAlUWSdSinDw5HKvl0nNx8q+nLaCrWCmlKhK4pQgwOr43gl 970pwRRa3kXaC6QUn0up4kJ3K7a1DGd5I18CRLthyZFrmjbiAHzMVjzxE/QqEv0R vT0fKkegUPDbc+P/3Izx8/luGaGKAZ6b/EyaAHv2LBMm/yugILNt/834TTxVJGoZ dtr808/ka96rB76hRTiBhft5LLFUF3ao1GUMPlR58YudTV6DcyjqYCoUFfROAwWE sstahH0wK7adsKjozHZGH1oIrjAAFqfN91xdeKWdxcLMXjrWkxKKdfrhnkQ== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dq1jh4eqe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2026 14:57:27 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.7/8.18.1.7) with ESMTP id 63NEvOM5010901; Thu, 23 Apr 2026 14:57:24 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 4dm31k24ar-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2026 14:57:24 +0000 (GMT) Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.1.12) with ESMTP id 63NEvNFm010879; Thu, 23 Apr 2026 14:57:23 GMT Received: from hu-devc-hyd-u24-a.qualcomm.com (hu-msavaliy-hyd.qualcomm.com [10.147.246.140]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 63NEvNq0010877 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2026 14:57:23 +0000 (GMT) Received: by hu-devc-hyd-u24-a.qualcomm.com (Postfix, from userid 429934) id 5DC3F21C47; Thu, 23 Apr 2026 20:27:22 +0530 (+0530) From: Mukesh Kumar Savaliya To: viken.dadhaniya@oss.qualcomm.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, Frank.Li@kernel.org, andersson@kernel.org, konradybcio@kernel.org, dmitry.baryshkov@oss.qualcomm.com, linmq006@gmail.com, quic_jseerapu@quicinc.com, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Cc: krzysztof.kozlowski@oss.qualcomm.com, bartosz.golaszewski@oss.qualcomm.com, bjorn.andersson@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, Mukesh Kumar Savaliya Subject: [PATCH v7 2/4] dmaengine: qcom: gpi: Add lock/unlock TREs for multi-owner I2C transfers Date: Thu, 23 Apr 2026 20:25:49 +0530 Message-ID: <20260423145705.545552-3-mukesh.savaliya@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com> References: <20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIzMDE0OSBTYWx0ZWRfX5S9wGn4pQhD1 gAjZDUfA87A4haLN6/8ovFMfDW+4x9XEDJZrfCAokUC52+U+6lUCi2DlGN9Xn0SpmYSL5lKePqP z37aaQOy0MgTQRqnIbLXXOvRQRIaimjdC9Y9sAHVwohOF4IJvShMCiYFmDWSO3IwzXK1SGD8pIB FAT+4OgqeB56vKmXSSZtzcdm7lY4+LfpIOHqS+M0WaFpj5qW8/F6oAfB+sRy/XaFPwdAagiFGdx 9k5w/CnJPcWG+mDPnqiUxCxBIf5JuQOdJcIhG4ZRSaa5eUdzRBdVBjsmAp7V8nslFLR9/3Zulgk E5/LUUTo1VDRSilHKLJDWxz/3S4SH7nHJDd2qT9ZIZSuatuYCXyBtpOrnnUET1+EWOienu17ni/ skh4KX3p2sXEf5307/zW9uYzJwZf75GTppyBXaV1P3qWftzuaM4cz09y88TiwaScsku10AvtPR/ gv2nsr6tp3IwlCwVuEw== X-Authority-Analysis: v=2.4 cv=OeyoyBTY c=1 sm=1 tr=0 ts=69ea3357 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=mSgB-p_1VGLq_7tLs9EA:9 X-Proofpoint-GUID: xxn2LeVrkiJzN-4XwIon1KeZAV4jQgbl X-Proofpoint-ORIG-GUID: xxn2LeVrkiJzN-4XwIon1KeZAV4jQgbl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 adultscore=0 suspectscore=0 phishscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604230149 Content-Type: text/plain; charset="utf-8" Some platforms use a QUP-based I2C controller in a configuration where the controller is shared with another system processor (described in DT using qcom,qup-multi-owner). In such setups, GPI hardware lock/unlock TREs can be used to serialize access to the controller. Add support to emit lock and unlock TREs around I2C transfers and increase the maximum TRE count to account for the additional elements. Also simplify the client interface by replacing multiple boolean fields (shared flag and message position tracking) with a single lock_action selector (acquire/release/none), as the GPI driver only needs to know whether to emit lock/unlock TREs for a given transfer. Signed-off-by: Mukesh Kumar Savaliya --- drivers/dma/qcom/gpi.c | 44 +++++++++++++++++++++++++++++++- include/linux/dma/qcom-gpi-dma.h | 18 +++++++++++++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c index 6e30f3aa401e..a1f391dd1747 100644 --- a/drivers/dma/qcom/gpi.c +++ b/drivers/dma/qcom/gpi.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2020, Linaro Limited + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 #include @@ -67,6 +68,14 @@ #define TRE_DMA_LEN GENMASK(23, 0) #define TRE_DMA_IMMEDIATE_LEN GENMASK(3, 0) =20 +/* Lock TRE */ +#define TRE_LOCK BIT(0) +#define TRE_MINOR_TYPE GENMASK(19, 16) +#define TRE_MAJOR_TYPE GENMASK(23, 20) + +/* Unlock TRE */ +#define TRE_UNLOCK BIT(8) + /* Register offsets from gpi-top */ #define GPII_n_CH_k_CNTXT_0_OFFS(n, k) (0x20000 + (0x4000 * (n)) + (0x80 *= (k))) #define GPII_n_CH_k_CNTXT_0_EL_SIZE GENMASK(31, 24) @@ -518,7 +527,7 @@ struct gpii { bool ieob_set; }; =20 -#define MAX_TRE 3 +#define MAX_TRE 5 =20 struct gpi_desc { struct virt_dma_desc vd; @@ -1625,12 +1634,27 @@ static int gpi_create_i2c_tre(struct gchan *chan, s= truct gpi_desc *desc, unsigned long flags) { struct gpi_i2c_config *i2c =3D chan->config; + enum gpi_lock_action lock_action =3D i2c->lock_action; struct device *dev =3D chan->gpii->gpi_dev->dev; unsigned int tre_idx =3D 0; dma_addr_t address; struct gpi_tre *tre; unsigned int i; =20 + /* Optional lock TRE before transfer */ + if (lock_action =3D=3D GPI_LOCK_ACQUIRE) { + tre =3D &desc->tre[tre_idx]; + tre_idx++; + + tre->dword[0] =3D 0; + tre->dword[1] =3D 0; + tre->dword[2] =3D 0; + tre->dword[3] =3D u32_encode_bits(1, TRE_LOCK); + tre->dword[3] |=3D u32_encode_bits(1, TRE_FLAGS_IEOB); + tre->dword[3] |=3D u32_encode_bits(0, TRE_MINOR_TYPE); + tre->dword[3] |=3D u32_encode_bits(3, TRE_MAJOR_TYPE); + } + /* first create config tre if applicable */ if (i2c->set_config) { tre =3D &desc->tre[tre_idx]; @@ -1690,6 +1714,24 @@ static int gpi_create_i2c_tre(struct gchan *chan, st= ruct gpi_desc *desc, =20 if (!(flags & DMA_PREP_INTERRUPT)) tre->dword[3] |=3D u32_encode_bits(1, TRE_FLAGS_BEI); + + /* If multi-owner and this is the release boundary, chain it */ + if (i2c->lock_action =3D=3D GPI_LOCK_RELEASE) + tre->dword[3] |=3D u32_encode_bits(1, TRE_FLAGS_CHAIN); + } + + /* Optional unlock TRE after transfer */ + if (lock_action =3D=3D GPI_LOCK_RELEASE && i2c->op !=3D I2C_READ) { + tre =3D &desc->tre[tre_idx]; + tre_idx++; + + tre->dword[0] =3D 0; + tre->dword[1] =3D 0; + tre->dword[2] =3D 0; + tre->dword[3] =3D u32_encode_bits(1, TRE_UNLOCK); + tre->dword[3] |=3D u32_encode_bits(1, TRE_FLAGS_IEOB); + tre->dword[3] |=3D u32_encode_bits(1, TRE_MINOR_TYPE); + tre->dword[3] |=3D u32_encode_bits(3, TRE_MAJOR_TYPE); } =20 for (i =3D 0; i < tre_idx; i++) diff --git a/include/linux/dma/qcom-gpi-dma.h b/include/linux/dma/qcom-gpi-= dma.h index 6680dd1a43c6..36cbb85499b4 100644 --- a/include/linux/dma/qcom-gpi-dma.h +++ b/include/linux/dma/qcom-gpi-dma.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2020, Linaro Limited + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 #ifndef QCOM_GPI_DMA_H @@ -51,6 +52,21 @@ enum i2c_op { I2C_READ, }; =20 +/** + * enum gpi_lock_action - request lock/unlock TRE sequencing + * @GPI_LOCK_NONE: No lock/unlock TRE requested for this transfer + * @GPI_LOCK_ACQUIRE: Emit a lock TRE before the transfer + * @GPI_LOCK_RELEASE: Emit an unlock TRE after the transfer + * + * Used by protocol drivers for multi-owner controller setups (e.g. when + * DeviceTree indicates the controller is shared via qcom,qup-multi-owner). + */ +enum gpi_lock_action { + GPI_LOCK_NONE =3D 0, + GPI_LOCK_ACQUIRE, + GPI_LOCK_RELEASE, +}; + /** * struct gpi_i2c_config - i2c config for peripheral * @@ -65,6 +81,7 @@ enum i2c_op { * @rx_len: receive length for buffer * @op: i2c cmd * @muli-msg: is part of multi i2c r-w msgs + * @lock_action: request lock/unlock TRE sequencing for this transfer */ struct gpi_i2c_config { u8 set_config; @@ -78,6 +95,7 @@ struct gpi_i2c_config { u32 rx_len; enum i2c_op op; bool multi_msg; + enum gpi_lock_action lock_action; }; =20 #endif /* QCOM_GPI_DMA_H */ --=20 2.43.0 From nobody Sun Jun 14 00:41:37 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1B4CF359A62; Thu, 23 Apr 2026 14:57:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776956255; cv=none; b=fVtmyY8kZlPSZkeCOg818SA7xu+mrTxBMxyQUkfPEEwHzeQBaYluNEeYTe8wh6Le/gCEm1vYGYEDUYdDTnj7m/QvuAOUQWpgOx1Rm0etdjX5RxcFAThoOLsf7FJpiRqU2yWzVb97ua5Erc6vMvjjfQM8vnOrJNeZnkMIdeOiJI0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776956255; c=relaxed/simple; bh=e7t6ShQ2cI3Mz6AmaHsbAxeWQh28RjNT6mgVG3MLxxw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hWzXB+Cz9ZKUgVlbltrEqJIZsUK/i5SkPEc0uHu7qEqL8Wg1ayWLKjxLG8THqrlx0nh6MLjMdnvlvs2PowYaoExcc4g6fwgp+mxLmo3+hWJtxN7TuYqpqPB85KLa8AsXmaf77l8G0nmChF22y8zM1WVdW8sziyzG0WNBPtMafgw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=kY/JaW/8; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="kY/JaW/8" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63N8uEtN3044055; Thu, 23 Apr 2026 14:57:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=MVr+iQ0IOVH oD8QLuy6TdPdop5YCIZQZqq7rbtOLfq4=; b=kY/JaW/81tBDC3bTJ+dVIQt0hSs 1h3N0RZEV68z56FENw+xhRDypU6TI2fCcY0IJlcQ1XSi5i2mkIgmdRQzhoYqUBAz wEF/v6ZUDN+MI1+Dy4DU4tvqX4WccIwe6lcN49Yk5Vme3N+BuLvQI4HEoRnBnBzE 0MMI5vNKMIu4odslVmtFK7yh4ZNqm2nBNOpj94XO4FQZ9boPa7LN5C5TuqnL3XOq 7lwCHx6ltYompWl3AD9bMvU5TH1HyCaEos1xk6I0kKQgP4d4ehQKZh+Pt7E3DCas fo40XpEPAYZU5MitramtUfru3Omi/WGRK6aaViyQlLYOxRgM1uRY/8Qlb5w== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dq1jh4eqj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2026 14:57:29 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.7/8.18.1.7) with ESMTP id 63NEvQO5011425; Thu, 23 Apr 2026 14:57:26 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 4dm31k24b4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2026 14:57:26 +0000 (GMT) Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.1.12) with ESMTP id 63NEvQnW011419; Thu, 23 Apr 2026 14:57:26 GMT Received: from hu-devc-hyd-u24-a.qualcomm.com (hu-msavaliy-hyd.qualcomm.com [10.147.246.140]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 63NEvPrS011417 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2026 14:57:26 +0000 (GMT) Received: by hu-devc-hyd-u24-a.qualcomm.com (Postfix, from userid 429934) id E3BF521C47; Thu, 23 Apr 2026 20:27:24 +0530 (+0530) From: Mukesh Kumar Savaliya To: viken.dadhaniya@oss.qualcomm.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, Frank.Li@kernel.org, andersson@kernel.org, konradybcio@kernel.org, dmitry.baryshkov@oss.qualcomm.com, linmq006@gmail.com, quic_jseerapu@quicinc.com, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Cc: krzysztof.kozlowski@oss.qualcomm.com, bartosz.golaszewski@oss.qualcomm.com, bjorn.andersson@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, Mukesh Kumar Savaliya Subject: [PATCH v7 3/4] soc: qcom: geni-se: Keep pinctrl active for multi-owner controllers Date: Thu, 23 Apr 2026 20:25:50 +0530 Message-ID: <20260423145705.545552-4-mukesh.savaliya@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com> References: <20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIzMDE0OSBTYWx0ZWRfX3wQntq8X80DI jdfK1b/mplihxHrqiHMq6M66n4l5ku3HLfiKXQCaiWNqCFmUKtkNuKR6oLOkZf7qUsNiBptMIrp UCxeDBsCZyab63xMxAlWJgzPU/EcwHtNUHdrCWyXIbQ6sdWuFfraAK/4aHwuPT2vLEskizDZEnq MprEdmwWjRW85/KT86bEyH7N9MI4Pb4f6AjDf0CXTtZw1c1xmU3XldMOs7ltQ8iXXvGBbkq7uHf GAY6oPRAt5Ztq4hJOVDyD+CMVAyh6422fIMI4fjoRofKJnlxTcu0WemV0RS0bPCQIK/DWw2UtUZ Vd6H64PHc8rxd027gknKFxbDRPXl/TD11M/hyOQqlTUKv5NEOqe2b5pmeyYNvC+QGav8dpF1QyG Ys98PQUgJYswh3wjCPoM8PHHrWiL27/Ls8k+1Oxf3abVaChe4aSelZSWPioZMOHUiEq1wV9yAtp ABLjXQ+MWblGP3YUmPQ== X-Authority-Analysis: v=2.4 cv=OeyoyBTY c=1 sm=1 tr=0 ts=69ea335a cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=AU6ItHRBSQEJJjuWNb0A:9 X-Proofpoint-GUID: yn-QgtGEoKNj2wWp8mn69598A6mtBZow X-Proofpoint-ORIG-GUID: yn-QgtGEoKNj2wWp8mn69598A6mtBZow X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 adultscore=0 suspectscore=0 phishscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604230149 Content-Type: text/plain; charset="utf-8" On platforms where a GENI Serial Engine is shared with another system processor, selecting the "sleep" pinctrl state can disrupt ongoing transfers initiated by the other processor. Teach geni_se_resources_off() to skip selecting the pinctrl sleep state when the Serial Engine is marked as shared, while still allowing the rest of the resource shutdown sequence to proceed. This is required for multi-owner configurations (described via DeviceTree with qcom,qup-multi-owner on the protocol controller node). Reviewed-by: Konrad Dybcio Signed-off-by: Mukesh Kumar Savaliya --- drivers/soc/qcom/qcom-geni-se.c | 15 +++++++++++---- include/linux/soc/qcom/geni-se.h | 2 ++ 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index cd1779b6a91a..1a60832ace16 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -597,10 +597,17 @@ int geni_se_resources_off(struct geni_se *se) =20 if (has_acpi_companion(se->dev)) return 0; - - ret =3D pinctrl_pm_select_sleep_state(se->dev); - if (ret) - return ret; + /* + * Select the "sleep" pinctrl state only when the serial engine is + * exclusively owned by this system processor. For shared controller + * configurations, another system processor may still be using the pins, + * and switching them to "sleep" can disrupt ongoing transfers. + */ + if (!se->multi_owner) { + ret =3D pinctrl_pm_select_sleep_state(se->dev); + if (ret) + return ret; + } =20 geni_se_clks_off(se); return 0; diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni= -se.h index 0a984e2579fe..46217cac73c3 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -63,6 +63,7 @@ struct geni_icc_path { * @num_clk_levels: Number of valid clock levels in clk_perf_tbl * @clk_perf_tbl: Table of clock frequency input to serial engine clock * @icc_paths: Array of ICC paths for SE + * @multi_owner: True if SE is shared between multiple owners. */ struct geni_se { void __iomem *base; @@ -72,6 +73,7 @@ struct geni_se { unsigned int num_clk_levels; unsigned long *clk_perf_tbl; struct geni_icc_path icc_paths[3]; + bool multi_owner; }; =20 /* Common SE registers */ --=20 2.43.0 From nobody Sun Jun 14 00:41:37 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12F093126B2; Thu, 23 Apr 2026 14:57:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776956265; cv=none; b=SYZ4bD7ceBKk9Wrz51Qa6mtN2WRbuRLy/KbP0OFAZ1CcP4XVeudljwMoJvBif2UQQAZ5NU2IvJ4fFe1i2oLmKYpLaVwHpGnmuiD8GCtsHqrTFC3RRJou7m9VT6BWeRcvX2Q4nWIpFB1EXpikcTmKq4VrBg2Nts5ZuVJrKUqJjvo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776956265; c=relaxed/simple; bh=5wWO8YpZZeKWSICm5+VAGrGxxREHvjDClIgimaLRvN4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qiwzlh+xhywg0A/NaAY+kg66Vlyh4I5aOXS4HBhKsi+cofSzQEgNEGsw5xdGrnOk1bZqbMzJ1pWRsB1FN0HheCL4JCo0mZgu4lXzYUlQV/CJzLGBAq3wo/rrAWbgMWncO+0oIQ02JIoAnokkASj7xcEQJLbRHdFxCbDZWxxrpEw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=N6461PjQ; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="N6461PjQ" Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 63NBwigG009885; Thu, 23 Apr 2026 14:57:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=dKWP3BzwCZ7 DH9txszXX63ggQ7TbNv0YUXlfrhzzdJs=; b=N6461PjQ6aSKrwud81Z4tlKnObp u06Kp7qaogu4vi8Utp80pgq8j+fNaWBeYPmhyqTr+WtNf/t1UkGkH86E8dqYUGHU w/DO4LgEvCmd0GFsU5wYMbP383SxOHgijMKVRnT3/aizhju8G3VfM9Pvb3W6rjjj z5N1MsqmWVYvaj4ffAON/jhDgfJ1C2LKeqTkQk1aToLqhOrTQwteOk1cAibc3t8K m9nUzSyJ6xB7jye46PmO1RqUtZ3g5IEzVdvn0+qFI8wZ7ulouMiWQ6J9P63yOgzS AIVPUDFMUwTm6j+QmfcNQ0DRawsNiLot9AwhhF/3TubQgKwPsvdFiygjq1w== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dqk178p60-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2026 14:57:39 +0000 (GMT) Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.18.1.7/8.18.1.7) with ESMTP id 63NEvUA9011463; Thu, 23 Apr 2026 14:57:30 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 4dm31k24bj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2026 14:57:30 +0000 (GMT) Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.18.1.12/8.18.1.12) with ESMTP id 63NEvU7i011455; Thu, 23 Apr 2026 14:57:30 GMT Received: from hu-devc-hyd-u24-a.qualcomm.com (hu-msavaliy-hyd.qualcomm.com [10.147.246.140]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 63NEvTsT011451 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 23 Apr 2026 14:57:30 +0000 (GMT) Received: by hu-devc-hyd-u24-a.qualcomm.com (Postfix, from userid 429934) id AF69E21C47; Thu, 23 Apr 2026 20:27:28 +0530 (+0530) From: Mukesh Kumar Savaliya To: viken.dadhaniya@oss.qualcomm.com, andi.shyti@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, vkoul@kernel.org, Frank.Li@kernel.org, andersson@kernel.org, konradybcio@kernel.org, dmitry.baryshkov@oss.qualcomm.com, linmq006@gmail.com, quic_jseerapu@quicinc.com, agross@kernel.org, linux-arm-msm@vger.kernel.org, linux-i2c@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org Cc: krzysztof.kozlowski@oss.qualcomm.com, bartosz.golaszewski@oss.qualcomm.com, bjorn.andersson@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, Mukesh Kumar Savaliya Subject: [PATCH v7 4/4] i2c: qcom-geni: Support multi-owner controllers in GPI mode Date: Thu, 23 Apr 2026 20:25:51 +0530 Message-ID: <20260423145705.545552-5-mukesh.savaliya@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com> References: <20260423145705.545552-1-mukesh.savaliya@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-GUID: xpahXvXzHtvYjIgZ8PxySvxbpBjJ0HGd X-Authority-Analysis: v=2.4 cv=R98z39RX c=1 sm=1 tr=0 ts=69ea3363 cx=c_pps a=Ou0eQOY4+eZoSc0qltEV5Q==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=r5MnBgDnrAiVjouRZIUA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIzMDE0OSBTYWx0ZWRfX8iwpSd9tFd8F zxbZ7rJP4V3sMaVsWZDnblxkLhxkNQYFzz0+iZHodA9vh/MGzbCmDlGGWYfaLB9Vmz5JU+Ucve8 NuLGwJ8Lh3xmFccnI2qrSo6RezdSHYEohLl2fTDzP+dw4D7LfvWPc3EgvkUvlQL0JlojqvjCG/E RxIAoQnlibBF9KUDfHK1Wf8GRg9dCwIGC4Vs2kkxsZqMy+P3FmWg2YgF2l80aMRz0E6PFw/08Hs 9wa1IMiTP4AYrtHpSoglQGB/JlbGsE0piuEa14vcufowljWjaSXhJjaD3WpmvLcwWbwQCFwOhrO Yat/pW2ZAc4rto6RavaE9RsaUGKA5RuY939KeZhdn1d0guoPya5cftHf5rR8oYZbmdGPteDnQ/E +x9RxkNt2XY+iuXRW3UbmyBnoZusEPvxjFXZtAat3GSuWuVu/EqzsB3NtsILmyuD8l+fm8tOtnM ZH9jFElxrQVkVE3fzng== X-Proofpoint-ORIG-GUID: xpahXvXzHtvYjIgZ8PxySvxbpBjJ0HGd X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-23_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 clxscore=1015 priorityscore=1501 phishscore=0 malwarescore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604230149 Content-Type: text/plain; charset="utf-8" Some platforms use a QUP-based I2C controller in a configuration where the controller is shared with another system processor. In this setup the operating system must not assume exclusive ownership of the controller or its associated pins. Add support for enabling multi-owner operation when DeviceTree specifies qcom,qup-multi-owner. When enabled, mark the underlying serial engine as shared so the common GENI resource handling avoids selecting the "sleep" pinctrl state, which could disrupt transfers initiated by the other processor. For GPI mode transfers, request lock/unlock TRE sequencing from the GPI driver by setting a single lock_action selector per message, emitting lock before the first message and unlock after the last message (handling the single-message case as well). This serializes access to the shared controller without requiring message-position flags to be passed into the DMA engine layer. Signed-off-by: Mukesh Kumar Savaliya --- drivers/i2c/busses/i2c-qcom-geni.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index ae609bdd2ec4..a396ddc7d8f4 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -815,6 +815,14 @@ static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c= , struct i2c_msg msgs[], i if (i < num - 1) peripheral.stretch =3D 1; =20 + peripheral.lock_action =3D GPI_LOCK_NONE; + if (gi2c->se.multi_owner) { + if (i =3D=3D 0) + peripheral.lock_action =3D GPI_LOCK_ACQUIRE; + else if (i =3D=3D num - 1) + peripheral.lock_action =3D GPI_LOCK_RELEASE; + } + peripheral.addr =3D msgs[i].addr; if (i > 0 && (!(msgs[i].flags & I2C_M_RD))) peripheral.multi_msg =3D false; @@ -1014,6 +1022,11 @@ static int geni_i2c_probe(struct platform_device *pd= ev) gi2c->clk_freq_out =3D I2C_MAX_STANDARD_MODE_FREQ; } =20 + if (of_property_read_bool(pdev->dev.of_node, "qcom,qup-multi-owner")) { + gi2c->se.multi_owner =3D true; + dev_dbg(&pdev->dev, "I2C controller is shared with another system proces= sor\n"); + } + if (has_acpi_companion(dev)) ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev)); =20 @@ -1089,7 +1102,9 @@ static int geni_i2c_probe(struct platform_device *pde= v) } =20 if (fifo_disable) { - /* FIFO is disabled, so we can only use GPI DMA */ + /* FIFO is disabled, so we can only use GPI DMA. + * SE can be shared in GSI mode between subsystems, each SS owns a GPII. + */ gi2c->gpi_mode =3D true; ret =3D setup_gpi_dma(gi2c); if (ret) @@ -1098,6 +1113,11 @@ static int geni_i2c_probe(struct platform_device *pd= ev) dev_dbg(dev, "Using GPI DMA mode for I2C\n"); } else { gi2c->gpi_mode =3D false; + + if (gi2c->se.multi_owner) + return dev_err_probe(dev, -EINVAL, + "I2C sharing not supported in non GSI mode\n"); + tx_depth =3D geni_se_get_tx_fifo_depth(&gi2c->se); =20 /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */ --=20 2.43.0