From nobody Fri Jun 19 19:37:46 2026 Received: from MW6PR02CU001.outbound.protection.outlook.com (mail-westus2azon11012011.outbound.protection.outlook.com [52.101.48.11]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6872F30FC23 for ; Thu, 23 Apr 2026 07:41:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.48.11 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776930118; cv=fail; b=JKlIRXbRQNN8kgj+rrhBIeK8yCpjx2gtq8F19jr6iPNrdR+WxmB72+Q4ByXiRCuwOXYQREKgIlbIvI0GE0lOwXTWFwbquZOfMcaM20LgB8slC7HfTfdWpd+Ih56P0DmxbR6zi63/G+XTfdRU6gQbyMSAOCuLwVsn1oSgETM24Tc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776930118; c=relaxed/simple; bh=Wxs7YN+UKH3ZCiiquU+sxRAgTFXmhOwMZNbeojNZaXU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=Z9Ex/Y7ZZR2dMoXhzImOQ5NV/wU5IX5A7YJNS64q13QudzVROgVUXDFN3szBXAyKRSR2655PMurMlQyXXLaxM9t2pfJfx/tfPPkhIyIkSIdzyOsMw4UxgjdmYgyDEtZ9jPYZORqgX3bMwySgZSbjidewpCrsrRFxUXorhv8HUN0= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=bMgia/Qx; arc=fail smtp.client-ip=52.101.48.11 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="bMgia/Qx" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=uRlFpkzCABlZ2Cwn7M8l/ZNPZLIzJjE25vdMKDbDX+8v1JOz9IwOQqqUdKei3yaUjB00YGq5y72d8L7CFMvAO21ZEzVTeNtkClpnb5n/laSCSb4cS7IwwmHh0yECLL1UgEYVcUWCv0fLehOn6m8/HwYGzwDK2ouPkBRPmfBMZ8CAk4vZJ7f1uX8dOzRNmScH3cCjOg6ghp+durKjj1xp4l1Zyf2CpofM6x+K69JeJOU8/Cwqu8UpuU0rZX2easCV/un/T6gS8Si+wf84lxhN0MlDRM9Y5Nrvtjx9qwrZol2qcVNxI9DNvdhWT/fswNEV1/iEy4eVvqQmPPgCgMHNsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xIzr8bdkeS8xgPpaQMvzqlkHXpIMNq6LXkA342cv/LQ=; b=thHDBSNgIVHD0SzKLpdTFibK8zIdy2Ywi4F9wUdzmnfRYC4YH3gBL/29188/PTVnvbW7pJuAnBG+S8r6hWnAJaBbGnHvmHXbNxAmTn5jikumYtb1QuyLicU9ABtl/Zl5NkQJHD1ONXtRJABx/cSqtinYJK8TBM+iRVRlkABnkt3VzX2FQZTxkmyf2vTF8cpFi0elvaFRx/z4YAZo4ueJ+fILv91NzVR1/kAdva4K2ZR9OQ8O32xsu9Q3ch48M/5bphXjbntbOiEudw4iuZEI4prjw7cX68+XiH2hcxBm10auo/WCV3Xvblq9d1ojC3uNZmKyvIq/qwhG5QGGavoODw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=xIzr8bdkeS8xgPpaQMvzqlkHXpIMNq6LXkA342cv/LQ=; b=bMgia/QxDVppJeWxKCYfOXh/ZrLS3vDT7N7MoMTXq/vcNSHYerxDzMUpatlPEW7C/QF7m6L6eqx4Uzo5HZjapZdgrw/QvnJdrazrIYJa0NnWsM7fZTAc7KdZcs7P8Tud4C2GPVfYK+42fNNPCqYUW73xLowpbCi4yx2AugqB9O1GinyjKDEYrfi/gWCRDkABsYVnOvzQTpYDbSwnlq1t7TZJnce1NJL3DLFKZWTYj42jqxS+TZoDVNvKjtrdwu8o6uiRUAAAJaJAGMgeAl6UJBY6Ggcx0wDtFukV72caOQjXDKyCEURuDGWqhSXki0ddJTx1aKGz5jrkwVhmNghFUw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV8PR12MB9620.namprd12.prod.outlook.com (2603:10b6:408:2a1::19) by BL4PR12MB9534.namprd12.prod.outlook.com (2603:10b6:208:58f::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.21; Thu, 23 Apr 2026 07:41:53 +0000 Received: from LV8PR12MB9620.namprd12.prod.outlook.com ([fe80::299d:f5e0:3550:1528]) by LV8PR12MB9620.namprd12.prod.outlook.com ([fe80::299d:f5e0:3550:1528%5]) with mapi id 15.20.9846.019; Thu, 23 Apr 2026 07:41:53 +0000 From: Andrea Righi To: Ingo Molnar , Peter Zijlstra , Juri Lelli , Vincent Guittot Cc: Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , K Prateek Nayak , Christian Loehle , Koba Ko , Felix Abecassis , Balbir Singh , Joel Fernandes , Shrikanth Hegde , linux-kernel@vger.kernel.org Subject: [PATCH 1/5] sched/fair: Attach sched_domain_shared to sd_asym_cpucapacity Date: Thu, 23 Apr 2026 09:36:45 +0200 Message-ID: <20260423074135.380390-2-arighi@nvidia.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260423074135.380390-1-arighi@nvidia.com> References: <20260423074135.380390-1-arighi@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: BYAPR01CA0051.prod.exchangelabs.com (2603:10b6:a03:94::28) To LV8PR12MB9620.namprd12.prod.outlook.com (2603:10b6:408:2a1::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PR12MB9620:EE_|BL4PR12MB9534:EE_ X-MS-Office365-Filtering-Correlation-Id: 554394ec-b9f1-4a35-a7d3-08dea10bc956 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: mi49edeLtpzgAIuz3MfrolZbPNqUKfc9ToC2jTzYRi5Gb1IfCGsg3zI2CYfpXwMux1yt45sQUvCVtF+q+/EdH4Cy2UE0bg13z8/XAt589cOKFsWrJGy9cDKq6ZPr3J/i7PR3pk5/rI25xqUKLO6kOD+74NZOy+I0OVIEGFHMYw6WPifsMeZtu2IxtB3tOXpECQJDWKFKUYgQ9M0dLv2eoM9Be7tErTDjN8034cJLs0PGbvEV2OG+glqI+3fQYkJzUnGZp/CKWFskXbS4Ot3cDOwoABYVQD/tceBk/NvboyxbK922hRZfgl1q3euO4Yj/VWz3RNAclpY/g66PakUTPfbED1CNmCr/7qlIzEP1bGZE5gC+sOtJgmNwMOJJxGepPzYH3knybqXwive+S/v/O4Ws/zTnoU41yUGt9d7AxvfAravsTXvymZrCyTuMT8saHMGipD5wES5kxPSXUZe3MJ278MGqJ0dEw5JZZR9h/jgnH71kqiNdplw0r6Bz7lLsAdHaDo8Q5PRSYTsJWXSaaJgLe92ijgZ1sEOZUpXyGIzknXxrmt5enat1l9Ue16bnLp3znUKmDvO0+gNEYMb6LsCtifkajs5V8Fb2CXpdo7kNKEhxqrEukIBjki2VoDrpYpgZe+UjHjuYnfOwgfVxt+/9yJ9MLxta5G2HcAKroCl6DqcsoWGnZdpKRY/IGqdkr7K8Vm3eORBtGNXTfzXohHGHVuRjOvop9KYBZxcOWXI= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV8PR12MB9620.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?p7jJGNjnZhoOKsgIhJslXgwvk4G6GjKnml9Khlwq34MRmAcQ2H3zfQG8X8Kj?= =?us-ascii?Q?eqEh42qlgd6G6+StKy/lQKEKms7mWm3Yn5S6EQlrXCm1L+N/h3NHb2Jjw4b1?= =?us-ascii?Q?m+KPvrmxydSm4NVLQ4a8j2Qc0jnGbYC32+enA6KP6Fxp2Ul9xFOQlpyVYQvs?= =?us-ascii?Q?GpyIdLIxTOnTjmHUkyeC/yfbT2QvIIS8u4Qu5E/AJEl0JJsT50IH2dy7RSSv?= =?us-ascii?Q?L6HSEflFiFpg/om+12BpJEWXx6QvXKSqgyzzb0laRHmQlt5+ehIjXHllFLnu?= =?us-ascii?Q?FrSaFZZILTrfP1q3/bSVa9pGFyVfNBcGjgKoT+oBpwYIbh8Ty+1P0BrBSdYN?= =?us-ascii?Q?nnloB/KewsCrC0VNObAcqEwTiT3AFkCIZiN/mh9a71FPZIDr2pzGbHzg8H5t?= =?us-ascii?Q?JRR5xqvXlokIXDy3Fiz2gqHC5C5y68bsQmDg4eP2ovgpbpfxdBl/TCNTvCgt?= =?us-ascii?Q?SQhiAsAVhVjaHaWbHttEnEX0izXu1zBQfZy9tO+T3Hargy6R46ngVLoCmdxJ?= =?us-ascii?Q?fxoVlxO0YGZ7+6ezz02FfCi1GF8iF1eXeQr92MzwiMy1WvmXlZTuOR6gVaYp?= =?us-ascii?Q?1p0SaL3/E7F/Tuxo0a9oSy1b1VVCqwps+5z0U+AyXVYTZJZNOagj6dsfOjz3?= =?us-ascii?Q?M7fud4mxefqaM1EOswnZVm66h+NyO+KjEw6VP5Y6O6nQ+9UccochOK3ywtLa?= =?us-ascii?Q?zNgD+v5j88cPYaKSuB5NxINoLO7LN2IXUS0J+FMx6/tI3O2uVYYIVzvJDT93?= =?us-ascii?Q?qZ8ivWBnEuYJQJtipoDPmA1el67qMUAUUYHkKJfqWb8/uV2Psr1d8S0jLXm3?= =?us-ascii?Q?CKtHT1hpH5WDKhaUO/3xkPftE1XphKDIVnF+YPenn8v2+YIzYcdwJnFoce1y?= =?us-ascii?Q?a4XhC4sI355yMx/l/Yq307GZFXGjZkiJOhT1YN3iXvU5LuXBkw2+M6jldUyY?= =?us-ascii?Q?9h3JpJ2cTOFUdo4JXV9EzU/+oRIWAExVVWF0TN20eOF3Flm6PSP3i+ISUYE6?= =?us-ascii?Q?mc15ZuKyuMdDB1dN9XjH5qYtFFqS9+0c4X/sAwl/r7wRaUH7+de1v5vIjETI?= =?us-ascii?Q?27bC4gYrB5PjKUrpZsCF+UZ7p2s/K25lP6aNc2aEZUVJKMNV0EoCK44+6rQK?= =?us-ascii?Q?4HrphaPPeSs5dTekYQcNri+RWqEjvIf71WD6bxgKT90NQWhuhoNo4C1aquSB?= =?us-ascii?Q?oqabgBJ86reuxrWFHrCmRGtdska/4WkoHtTqEyEle5Nukagt+csMJMbc1AVk?= =?us-ascii?Q?jMLRJC/N2OTTcB+SiMLapajWeU1Aqx0AyDR9Ao1oHuB8828ZEkeswDab3UWO?= =?us-ascii?Q?H/PIpqbQ+9wWzXk/UAEco3vxb8Rdu1vLslgHVqIqj+fEsbpJaUJPflOhFBQ1?= =?us-ascii?Q?0u6JNYmg7pc38V4efeBlsEyRgo5YH7cU8vGb3ivEknL/cTBgB7SqjXJSbAci?= =?us-ascii?Q?iBUkF2XvxhbPL7R56sLfC5zm3bjQabM79wv95ukOB4fdp39Ogf7gpkhfchyZ?= =?us-ascii?Q?qowFYxurR64ZeqZoskKYNbsJ8P2kLCOG7BcmvmCRxeeBghfPUjLjEcvpuWUd?= =?us-ascii?Q?+EdNUJUT3S4DirQVtzwL+YE0o9BGe/d97x6Rra3BYzAEVKvT2xdfZCHBfH84?= =?us-ascii?Q?XoxGprkiZprmAyVRPJPE2S3/GHuhP5oLycceEnQirLW933js4HI2NifRKMP4?= =?us-ascii?Q?zMm/zinUKLpJ0fyC8rv3rH7bNm4oxgY54vu9AjY5pufPiuueJv9wu3MgwZ9U?= =?us-ascii?Q?3o7DLDbgyA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 554394ec-b9f1-4a35-a7d3-08dea10bc956 X-MS-Exchange-CrossTenant-AuthSource: LV8PR12MB9620.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2026 07:41:52.9299 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: p5Q2A1pTyxDaGkIlJadI1gMAqlL8jdKtV9xnyv/j5MO6jkXkxL6d1+fscx3vOcXQDz4qR8kJzT6aw4sSdUBB9g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9534 Content-Type: text/plain; charset="utf-8" From: K Prateek Nayak On asymmetric CPU capacity systems, the wakeup path uses select_idle_capacity(), which scans the span of sd_asym_cpucapacity rather than sd_llc. The has_idle_cores hint however lives on sd_llc->shared, so the wakeup-time read of has_idle_cores operates on an LLC-scoped blob while the actual scan/decision spans the asym domain; nr_busy_cpus also lives in the same shared sched_domain data, but it's never used in the asym CPU capacity scenario. Therefore, move the sched_domain_shared object to sd_asym_cpucapacity whenever the CPU has a SD_ASYM_CPUCAPACITY_FULL ancestor and that ancestor is non-overlapping (i.e., not built from SD_NUMA). In that case the scope of has_idle_cores matches the scope of the wakeup scan. Fall back to attaching the shared object to sd_llc in three cases: 1) plain symmetric systems (no SD_ASYM_CPUCAPACITY_FULL anywhere); 2) CPUs in an exclusive cpuset that carves out a symmetric capacity island: has_asym is system-wide but those CPUs have no SD_ASYM_CPUCAPACITY_FULL ancestor in their hierarchy and follow the symmetric LLC path in select_idle_sibling(); 3) exotic topologies where SD_ASYM_CPUCAPACITY_FULL lands on an SD_NUMA-built domain. init_sched_domain_shared() keys the shared blob off cpumask_first(span), which on overlapping NUMA domains would alias unrelated spans onto the same blob. Keep the shared object on the LLC there; select_idle_capacity() gracefully skips the has_idle_cores preference when sd->shared is NULL. Co-developed-by: Andrea Righi Signed-off-by: Andrea Righi Signed-off-by: K Prateek Nayak --- kernel/sched/fair.c | 8 ++-- kernel/sched/topology.c | 81 +++++++++++++++++++++++++++++++++++------ 2 files changed, 75 insertions(+), 14 deletions(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 69361c63353ad..934eb663f445e 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -7925,7 +7925,7 @@ static int select_idle_cpu(struct task_struct *p, str= uct sched_domain *sd, bool struct cpumask *cpus =3D this_cpu_cpumask_var_ptr(select_rq_mask); int i, cpu, idle_cpu =3D -1, nr =3D INT_MAX; =20 - if (sched_feat(SIS_UTIL)) { + if (sched_feat(SIS_UTIL) && sd->shared) { /* * Increment because !--nr is the condition to stop scan. * @@ -12840,7 +12840,8 @@ static void set_cpu_sd_state_busy(int cpu) goto unlock; sd->nohz_idle =3D 0; =20 - atomic_inc(&sd->shared->nr_busy_cpus); + if (sd->shared) + atomic_inc(&sd->shared->nr_busy_cpus); unlock: rcu_read_unlock(); } @@ -12869,7 +12870,8 @@ static void set_cpu_sd_state_idle(int cpu) goto unlock; sd->nohz_idle =3D 1; =20 - atomic_dec(&sd->shared->nr_busy_cpus); + if (sd->shared) + atomic_dec(&sd->shared->nr_busy_cpus); unlock: rcu_read_unlock(); } diff --git a/kernel/sched/topology.c b/kernel/sched/topology.c index 5847b83d9d552..dc50193b198c6 100644 --- a/kernel/sched/topology.c +++ b/kernel/sched/topology.c @@ -680,19 +680,39 @@ static void update_top_cache_domain(int cpu) int id =3D cpu; int size =3D 1; =20 + sd =3D lowest_flag_domain(cpu, SD_ASYM_CPUCAPACITY_FULL); + /* + * The shared object is attached to sd_asym_cpucapacity only when the + * asym domain is non-overlapping (i.e., not built from SD_NUMA). + * On overlapping (NUMA) asym domains we fall back to letting the + * SD_SHARE_LLC path own the shared object, so sd->shared may be NULL + * here. + */ + if (sd && sd->shared) + sds =3D sd->shared; + + rcu_assign_pointer(per_cpu(sd_asym_cpucapacity, cpu), sd); + sd =3D highest_flag_domain(cpu, SD_SHARE_LLC); if (sd) { id =3D cpumask_first(sched_domain_span(sd)); size =3D cpumask_weight(sched_domain_span(sd)); =20 - /* If sd_llc exists, sd_llc_shared should exist too. */ - WARN_ON_ONCE(!sd->shared); - sds =3D sd->shared; + /* + * If sd_asym_cpucapacity didn't claim the shared object, + * sd_llc must have one linked. + */ + if (!sds) { + WARN_ON_ONCE(!sd->shared); + sds =3D sd->shared; + } } =20 rcu_assign_pointer(per_cpu(sd_llc, cpu), sd); per_cpu(sd_llc_size, cpu) =3D size; per_cpu(sd_llc_id, cpu) =3D id; + + /* TODO: Rename sd_llc_shared to fit the new role. */ rcu_assign_pointer(per_cpu(sd_llc_shared, cpu), sds); =20 sd =3D lowest_flag_domain(cpu, SD_CLUSTER); @@ -711,9 +731,6 @@ static void update_top_cache_domain(int cpu) =20 sd =3D highest_flag_domain(cpu, SD_ASYM_PACKING); rcu_assign_pointer(per_cpu(sd_asym_packing, cpu), sd); - - sd =3D lowest_flag_domain(cpu, SD_ASYM_CPUCAPACITY_FULL); - rcu_assign_pointer(per_cpu(sd_asym_cpucapacity, cpu), sd); } =20 /* @@ -2650,6 +2667,15 @@ static void adjust_numa_imbalance(struct sched_domai= n *sd_llc) } } =20 +static void init_sched_domain_shared(struct s_data *d, struct sched_domain= *sd) +{ + int sd_id =3D cpumask_first(sched_domain_span(sd)); + + sd->shared =3D *per_cpu_ptr(d->sds, sd_id); + atomic_set(&sd->shared->nr_busy_cpus, sd->span_weight); + atomic_inc(&sd->shared->ref); +} + /* * Build sched domains for a given set of CPUs and attach the sched domains * to the individual CPUs @@ -2708,20 +2734,53 @@ build_sched_domains(const struct cpumask *cpu_map, = struct sched_domain_attr *att } =20 for_each_cpu(i, cpu_map) { + struct sched_domain *sd_asym =3D NULL; + bool asym_claimed =3D false; + sd =3D *per_cpu_ptr(d.sd, i); if (!sd) continue; =20 + /* + * In case of ASYM_CPUCAPACITY, attach sd->shared to + * sd_asym_cpucapacity for wakeup stat tracking. + * + * Caveats: + * + * 1) has_asym is system-wide, but a given CPU may still + * lack an SD_ASYM_CPUCAPACITY_FULL ancestor (e.g., an + * exclusive cpuset carving out a symmetric capacity island). + * Such CPUs must fall through to the LLC seeding path below. + * + * 2) Skip the asym attach if the asym ancestor is an + * overlapping domain (SD_NUMA). On those topologies let the + * LLC path own the shared object instead. + * + * XXX: This assumes SD_ASYM_CPUCAPACITY_FULL domain + * always has more than one group else it is prone to + * degeneration. + */ + sd_asym =3D sd; + while (sd_asym && !(sd_asym->flags & SD_ASYM_CPUCAPACITY_FULL)) + sd_asym =3D sd_asym->parent; + + if (sd_asym && !(sd_asym->flags & SD_NUMA)) { + init_sched_domain_shared(&d, sd_asym); + asym_claimed =3D true; + } + /* First, find the topmost SD_SHARE_LLC domain */ + sd =3D *per_cpu_ptr(d.sd, i); while (sd->parent && (sd->parent->flags & SD_SHARE_LLC)) sd =3D sd->parent; =20 if (sd->flags & SD_SHARE_LLC) { - int sd_id =3D cpumask_first(sched_domain_span(sd)); - - sd->shared =3D *per_cpu_ptr(d.sds, sd_id); - atomic_set(&sd->shared->nr_busy_cpus, sd->span_weight); - atomic_inc(&sd->shared->ref); + /* + * Initialize the sd->shared for SD_SHARE_LLC unless + * the asym path above already claimed it. + */ + if (!asym_claimed) + init_sched_domain_shared(&d, sd); =20 /* * In presence of higher domains, adjust the --=20 2.54.0 From nobody Fri Jun 19 19:37:46 2026 Received: from PH7PR06CU001.outbound.protection.outlook.com (mail-westus3azon11010028.outbound.protection.outlook.com [52.101.201.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59FB630BF67 for ; Thu, 23 Apr 2026 07:42:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.201.28 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776930126; cv=fail; b=j/ekuhreofxCo1hVHB/Grtbsrl3WEPkkKdcsh2xu630i/HG4NEKKh9uLog6lV/W4px4nL30G8ufIjdVoyhOtkjoKi/Ht5Iarowc1038kdtAoJf9warYX2glHV9iMuDBga+/c/oFaJq0wPkoFoLOIKc73HZUJYoI8eVRYcE7/edA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776930126; c=relaxed/simple; bh=6mdID9x61rq5owidlfdHOMYtad8VOtKe3nW3TvFIGgw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=Tukcb0lSnDa+iCmrdzw5ivCzF0yFxLUeh3OVqLfjqX2JCN172/OOGivW+dSTZMaJ3SBKot+xheo8PPWDaUMb2LGrQC10lZhT767Ole59/TGM0r1OaEojeMlouV9QN22lRAVpWeF6vXDqzNLQNDiJjFbGJK19C583M1bnc4W2swg= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=n4PQIosM; arc=fail smtp.client-ip=52.101.201.28 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="n4PQIosM" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=BQjxvMHqq/AL64asmueWIKDx/Nr0unEHHfdL59FqnyQ7clbxwfqB1ggBEF+JM4DP+qxVlayx7W3tQizquZEwFsRj7MjYwgxkIJW854TsWegYdlbFR5WpR4noELKCUwkoF9ngxQGGNv+aqUjZYuH18gw/Utmz7K7xP1gwpIVyQMWihx2UqznhgAGVkF2P9ZNApz72En4xnOA0lbr2gh2ZuH2wUwOLrOx79tAkCC5cK9LvJXUP5BOsC3allz5IUC9Jf3XNqH73jEh7X2tMnbAgPttOKf+UT8VJIGbPtvUc6ikbRmKxWwyh5br8H2jenYZI3B0KcE8WmVJO0H3Wj90GQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=zsDw3SZ2yslrmnAfk0oathcYAwlzbtmPmzvinhh8p0Y=; b=or/EHOh94pUWJxH87PIcAsourZMreYyGXuXDFz6cMwAibPQqUSMdm9Nldx7Kc3TxGXzfCo7jjUAecT0uuPFLloIljAZjhltP/XGSvjuIw5jEDxfXy9rYOZ4ACzQrLgjEdBS0DfNCWOBXCGkHgGJQ/ynzdzhT9dLImBQD/g1iQIvZDQrpwIW8S8qafpoaJKwiDR5zft5vxgsKuQYNS7aWrTfznsNqGehryNlmeoZS3rC5OjAKrL+LzZBdRkhsbQSp4hjIu+jVXWKa4izwTIub6GGFpdasA0i1lNVMSFzry85GuhyRpIuewY7wqLNaK8v/IsNb68i0P3ipgbIzlsfAUA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zsDw3SZ2yslrmnAfk0oathcYAwlzbtmPmzvinhh8p0Y=; b=n4PQIosMTqh3fm4H2moUtbdar5ShtZyQsAX3SSq6HJ2QiLFbTNvC3HdQKQwEA5VVKfu0O3vcMleHYEDWfUL9rnJ4+9xW54sItBv0uJ/rXYUI9MJIH8a5OYItCYooqUDB6H9YYuViW+ZRK1iqXXY5Tm+R8Zgz5de5qXboKIhHJVZWi3T5aKy+tNbPdr9lXuZe9p8ZbOuReZ9W0Tz9xv0anmVgRkVARDUTeW2vYjBWCVKqFfErjXiOY7Qrk6glEPATjPJllpSphBy+pcK92p9h7jtY8709kB3h4G7V7/Te1tNOXS8SmfoHVUYD1EnM+IGuBX6ocn6ytOMb071HKf0Llg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV8PR12MB9620.namprd12.prod.outlook.com (2603:10b6:408:2a1::19) by BL4PR12MB9534.namprd12.prod.outlook.com (2603:10b6:208:58f::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.21; Thu, 23 Apr 2026 07:42:02 +0000 Received: from LV8PR12MB9620.namprd12.prod.outlook.com ([fe80::299d:f5e0:3550:1528]) by LV8PR12MB9620.namprd12.prod.outlook.com ([fe80::299d:f5e0:3550:1528%5]) with mapi id 15.20.9846.019; Thu, 23 Apr 2026 07:42:01 +0000 From: Andrea Righi To: Ingo Molnar , Peter Zijlstra , Juri Lelli , Vincent Guittot Cc: Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , K Prateek Nayak , Christian Loehle , Koba Ko , Felix Abecassis , Balbir Singh , Joel Fernandes , Shrikanth Hegde , linux-kernel@vger.kernel.org Subject: [PATCH 2/5] sched/fair: Prefer fully-idle SMT cores in asym-capacity idle selection Date: Thu, 23 Apr 2026 09:36:46 +0200 Message-ID: <20260423074135.380390-3-arighi@nvidia.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260423074135.380390-1-arighi@nvidia.com> References: <20260423074135.380390-1-arighi@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: ZR0P278CA0089.CHEP278.PROD.OUTLOOK.COM (2603:10a6:910:22::22) To LV8PR12MB9620.namprd12.prod.outlook.com (2603:10b6:408:2a1::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PR12MB9620:EE_|BL4PR12MB9534:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ce45cd1-0fca-4449-3a43-08dea10bcea7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: 49XcHcPQGThz7zYRGCkN+mfDvT2izhPLpVbxpCL1OlWyLRZVXjD9FXjMYfgTezU/OinjmKSCC7j3RQtzSIZKpUl9ZA2o4+XDYjYFg3j5MSwPivfClGaWNd814c+ofs/pbMdbu5l/JQS/52AiHjNBuRGis6KGn9AqcmxmUXEjjlWA/chnOyy1djx26PAJKKVRdrpAsT6Fhgr9FgpfmeNiFKc4SYkFcoLtnHX6KW42vPm/zs34hK/yAMhBQTmpbLy8+IWYYbCt52Mr8ayOqdKrm+zJfjhlg5yvWyL4HIXwrbPYs6G38W83Z8q0t30EUwf2PgIZ9cur5JqSdJY6JlM7aZqiO+ilDmu9ER1wh1BHEL9xYOGFglEqeFdYYEwNnDRAf08QbfwKVMkCYOotPw4ffKzrJiZsERVSegLLrCA8kh8rKd5NPwoEof7/snifh1MawQn/E7mts0KVoDcxOTeb9i4ampRi7X9Gk+yOTiCUDQxI9gl3wDhlW+P4wmotxAUILg5G0/RSQeEIA2eMURPS39/FmFdX4+AskcZmjCFzd1ErRZ/HylE/dUw5t5v1ExeSxMB/g4bWp/haeyLGYp3zzFHwbpQeu0zu6AEcQj0IFb0Zs2N67IgZj/EeMZDL/EDtvIdwgyLmq+MGh3SlIs4H696cUX48tjlbEEbldi0grXUh0NWiyRq3+y9s+6bt4ADJQk0EDsLbXZ9icppkZG3SXdu+WIfq/aeafpesq5dYHqg= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV8PR12MB9620.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?p/w2dU1kOso17h01wmetX+faBn0sA0E3Lm37Fgt/kPbEgBIXKbuMi9BaUhpT?= =?us-ascii?Q?krdmGwBPeF5UzQkHgUCH3qkFutqpfHCJZ1PLvxxij10X1Iyx/5qRroQiD7iq?= =?us-ascii?Q?UOQKxdiE0vGH++XjHW2RbKDsc/H0N5FsnNx/jxS1eJ8pizZp4cxozNQYSqDz?= =?us-ascii?Q?oIyVL7PvxtZnhVxf5O7eSq7L/AZ7IndM89w4zd+rn3US5LMVUxJCCdGbVW+1?= =?us-ascii?Q?yYkmMnl9qA51EnxB8JQEvvFXsV49pxZOPAI1QjeWS4qhYwWA/gvbJuyNYWKa?= =?us-ascii?Q?O8N/y10N6WjSbSx08YJNm2maoZVDyKaSeXvNz7eN1BMXPJHTjhZAEJmc5ecp?= =?us-ascii?Q?uqL1B/BamzMrgccheWdB1ltyFsEx7zO1dTiL5GtTuZIgUtDDZ2M6+YlyTCRr?= =?us-ascii?Q?CIlAA4athDLFSaOIwhXy8NmEH5gBXcFC3qSylraGEb0tmTh1Sm8mOWmvMTTI?= =?us-ascii?Q?B9Quw4p4+3NVg+i9fYo/lUISSWS03UN3rVxi7ftnoWU+NNR8lJwoWEuA1cEu?= =?us-ascii?Q?e7ypniea4yQEe7HFB6R21w5OPFqr9SxUDlVDKlUMhZb3ARVLHN1met8OrHSy?= =?us-ascii?Q?k1X1TyjnBLHHFmVHjygO4xMbf6K81USkkmZw1KKiDiNg83hCQW2BCCsKYOZl?= =?us-ascii?Q?deFTh+bArnPMMGMUWBkBqoTOlSUjorAm41rbWnRvG3Jy7G8C3NAcZmdcGd2f?= =?us-ascii?Q?hTirMTXUFnPLXIg7n1gr+lVP1qh5Sy3fsp7GKTbxCO4a2ejIQ01IAI/kkLW6?= =?us-ascii?Q?e0fOR/yFOg6/c0OrESk0xVa89Ih/6M0gBeAHWZzpFGp5KM2DPE02DToKtL4G?= =?us-ascii?Q?CfZ3A7Q+XCNFJ4KesPeHUtVfzghaNB/Rtx9x/kAof8FgDxhKzfkxRp2n+1LQ?= =?us-ascii?Q?pv0L5/d5J3TtOXPGDnjhkN9ctDbwIyFIZQGRj2E7tQLxjdvUxFEhgqCos37E?= =?us-ascii?Q?2qAbsnjnykUaYxTO9cfm7BgSl1YzX0E6+eQbqZDW/8MTx1gFgjwgs0rSU5j8?= =?us-ascii?Q?/cOIhJWPd/vSaA8YZeEVOALyi3r2eK+lFleBzGKJ31SLzSsh55EEbhMeOrAl?= =?us-ascii?Q?V0Bob9YeAKOvOKAYtCnanEu3GSrDULMs0nRQqh3IgEKO55FXeCBDNgDf1CgR?= =?us-ascii?Q?Vhg9gcEDj2w8xApDmOaD7U+Mvtcuug2E9QgCZhkIzU/GfrDniOQFGrhACnDr?= =?us-ascii?Q?mfhilb0/3ztnFj5CIaMEQ1Ruwmn3yWbKNOq+31cD1gpQCzDXUi9+CVcXyIHm?= =?us-ascii?Q?TZIGDYiZPBUHrb1lhz1lwM6EdRINVUZ9rOG2wEluxlb1M1tuq2kg75Tsv9WY?= =?us-ascii?Q?eqIHvh4DN4YSYeqZ9N7bPi7OexnHheOrsYW73giI3/3h2pgwSRthouRN2Tg0?= =?us-ascii?Q?LD07v3RTYzzlYy+WCMdlDiwYQnf7vs2Xo6A1dvmf0xGgAOe6klH1HXig+lfr?= =?us-ascii?Q?9HX7gqUE6Yxk65pO+IwXNlFgBeBTN5htpNNYw37Ndi/LS/PRGk36ccUYAyHj?= =?us-ascii?Q?9MklOn8iEDDk6STthZjMDGZPRz2XrhSbCZpV+VPV0T1eGUkC3NEcCBaKHdT0?= =?us-ascii?Q?4uTOjJwwtDNfLEYDdR1fUvoRsCDa7NfoBEkaRSobatTxakZfRCw4sX9D8E6l?= =?us-ascii?Q?d2lKzfxtUPXi5xeE1d0K9lKho76RHckzYZ2Grw7sWlUoBw4cEYCwuw/Cq/UN?= =?us-ascii?Q?Ez9Z0z6Qe314GMnncPh7ItP+bXHSWcVKE9xSEq4VN5C7KlAF+crlS5lpTfJ6?= =?us-ascii?Q?ypLo8hcu7Q=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1ce45cd1-0fca-4449-3a43-08dea10bcea7 X-MS-Exchange-CrossTenant-AuthSource: LV8PR12MB9620.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2026 07:42:01.9057 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: MdM1Dphzs1GaxTD3Vv/hHIK0jsRdDBpYnC/yLfzq4TlYenWhslG1HjcOkgICEghHGdohQ9d5ydCycvKFaBrUPQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9534 Content-Type: text/plain; charset="utf-8" On systems with asymmetric CPU capacity (e.g., ACPI/CPPC reporting different per-core frequencies), the wakeup path uses select_idle_capacity() and prioritizes idle CPUs with higher capacity for better task placement. However, when those CPUs belong to SMT cores, their effective capacity can be much lower than the nominal capacity when the sibling thread is busy: SMT siblings compete for shared resources, so a "high capacity" CPU that is idle but whose sibling is busy does not deliver its full capacity. This effective capacity reduction cannot be modeled by the static capacity value alone. Introduce SMT awareness in the asym-capacity idle selection policy: when SMT is active, always prefer fully-idle SMT cores over partially-idle ones. Prioritizing fully-idle SMT cores yields better task placement because the effective capacity of partially-idle SMT cores is reduced; always preferring them when available leads to more accurate capacity usage on task wakeup. On an SMT system with asymmetric CPU capacities, SMT-aware idle selection has been shown to improve throughput by around 15-18% for CPU-bound workloads, running an amount of tasks equal to the amount of SMT cores. Cc: Vincent Guittot Cc: Dietmar Eggemann Cc: Christian Loehle Cc: Koba Ko Reported-by: Felix Abecassis Signed-off-by: Andrea Righi Reviewed-by: K Prateek Nayak --- kernel/sched/fair.c | 48 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 934eb663f445e..d0c8bcc0d96a1 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -7997,6 +7997,7 @@ static int select_idle_cpu(struct task_struct *p, str= uct sched_domain *sd, bool static int select_idle_capacity(struct task_struct *p, struct sched_domain *sd, int t= arget) { + bool prefers_idle_core =3D sched_smt_active() && test_idle_cores(target); unsigned long task_util, util_min, util_max, best_cap =3D 0; int fits, best_fits =3D 0; int cpu, best_cpu =3D -1; @@ -8010,6 +8011,7 @@ select_idle_capacity(struct task_struct *p, struct sc= hed_domain *sd, int target) util_max =3D uclamp_eff_value(p, UCLAMP_MAX); =20 for_each_cpu_wrap(cpu, cpus, target) { + bool preferred_core =3D !prefers_idle_core || is_core_idle(cpu); unsigned long cpu_cap =3D capacity_of(cpu); =20 if (!choose_idle_cpu(cpu, p)) @@ -8018,7 +8020,7 @@ select_idle_capacity(struct task_struct *p, struct sc= hed_domain *sd, int target) fits =3D util_fits_cpu(task_util, util_min, util_max, cpu); =20 /* This CPU fits with all requirements */ - if (fits > 0) + if (fits > 0 && preferred_core) return cpu; /* * Only the min performance hint (i.e. uclamp_min) doesn't fit. @@ -8026,9 +8028,30 @@ select_idle_capacity(struct task_struct *p, struct s= ched_domain *sd, int target) */ else if (fits < 0) cpu_cap =3D get_actual_cpu_capacity(cpu); + /* + * fits > 0 implies we are not on a preferred core + * but the util fits CPU capacity. Set fits to -2 so + * the effective range becomes [-2, 0] where: + * 0 - does not fit + * -1 - fits with the exception of UCLAMP_MIN + * -2 - fits with the exception of preferred_core + */ + else if (fits > 0) + fits =3D -2; + + /* + * If we are on a preferred core, translate the range of fits + * of [-1, 0] to [-4, -3]. This ensures that an idle core + * is always given priority over (partially) busy core. + * + * A fully fitting idle core would have returned early and hence + * fits > 0 for preferred_core need not be dealt with. + */ + if (preferred_core) + fits -=3D 3; =20 /* - * First, select CPU which fits better (-1 being better than 0). + * First, select CPU which fits better (lower is more preferred). * Then, select the one with best capacity at same level. */ if ((fits < best_fits) || @@ -8039,6 +8062,18 @@ select_idle_capacity(struct task_struct *p, struct s= ched_domain *sd, int target) } } =20 + /* + * A value in the [-4, -3] range means the chosen CPU is in a fully idle + * SMT core. Values above -3 mean we never ranked such a CPU best. + * + * The asym-capacity wakeup path returns from select_idle_sibling() + * after this function and never runs select_idle_cpu(), so the usual + * select_idle_cpu() tail that clears idle cores must live here when the + * idle-core preference did not win. + */ + if (prefers_idle_core && best_fits > -3) + set_idle_cores(target, false); + return best_cpu; } =20 @@ -8047,12 +8082,17 @@ static inline bool asym_fits_cpu(unsigned long util, unsigned long util_max, int cpu) { - if (sched_asym_cpucap_active()) + if (sched_asym_cpucap_active()) { /* * Return true only if the cpu fully fits the task requirements * which include the utilization and the performance hints. + * + * When SMT is active, also require that the core has no busy + * siblings. */ - return (util_fits_cpu(util, util_min, util_max, cpu) > 0); + return (!sched_smt_active() || is_core_idle(cpu)) && + (util_fits_cpu(util, util_min, util_max, cpu) > 0); + } =20 return true; } --=20 2.54.0 From nobody Fri Jun 19 19:37:46 2026 Received: from BN1PR04CU002.outbound.protection.outlook.com (mail-eastus2azon11010059.outbound.protection.outlook.com [52.101.56.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B944330C63A for ; Thu, 23 Apr 2026 07:42:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.56.59 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776930139; cv=fail; b=k7DrK2bvW/mGB6ivTGLpGiVAFmUFNoI359jasNlTVEYrX3qrpkGzD6IJRBUvRSnvvMRIH8yVZQcastGnNk1YgkXc3fabq46Nb8e7g0BnyccqjuFieTT0u0s7w+qbt3uO4DI2UPKdEJTGhqTKim2mKcg4uo5CaZmdzlMCZpwWFfE= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776930139; c=relaxed/simple; bh=s6X4rkRtgE6Rr4dKwPeOUirjPgpDsnZJBKZWP2zivj0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=UupC5NDZguRlECC8cxf5GprR+dVFlGvPcDqJHaXuFCICLwkyX8nIp+bEMc3NCkX70Y4WsbYCadk6jY3HgiIompiFDsAc5NZRwY7AeeG3iG5MVH4IPtlVVOOsTZHs3qjXycLkp1GTBrBy8mN0tOwHxXip49F9/z1ZYaLDajd0bsM= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=aCTNkReB; arc=fail smtp.client-ip=52.101.56.59 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="aCTNkReB" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=dHdMByvZsNfirfyexCe0r6vy9TF7BVMsymHk6fh1JiC0SmGP0sA0JNvk+INJD8jR4bgFeIpi1XqbwVckdXaKQruuMBe1l4u3eq+IUdcGwYW9rVgG9izjvGvAUSoJuNxInRO/GKoh92+oWnpihTqDsg13J1KlJN/d7E4pQAU/bIpaGzbkh+9bFY2lSgHwRIoOoIwTuI1fPVFXss1y5SHwWZqaGqWXRqWMG2zc162LzwFvkDUSJJPNaH4Hucq6MPkOxP5GKdIV5kiadu+zmumN6ge7iWbiubHWbdL+5VBK+AVuZexstIzGcvrYqIV5hZbFIb8UxAKbg0nzeXPBuQccbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=dw9C/f4IqZhwxyvN7IT6z5FUu5QlG4BkKgSoNiQteKY=; b=IyVXvz1rz7Si1AEdPiozT27+S2Q3gOmDYOYYZM9R9N75SqbzFwALz1yCatDvY+DC+hOiYJdQYhD4q1G6kQcuw0O77POXrxudR7Qq399A4XEe1WA9w9fTFqkaf5W3A84n33utkPlDPjqUId6cIUbgK9KdonqaOpkH8SenS/wLPF6vcP9JDFy6Lz+Y4giwkkDjTsaGiZs6k5sCYhX36z7cUTChY5GYmrFSGCX9tfxjxk/xkApZDKu6r2ODbqe35vmZ8koh6Zkpx4BRqeVPI+7ziobOPe5XaYKWPKfzzFwBt+AuyOC3OaNVSuTWCiTzHik/sg9FY8zGYro1fkd2jZ9xLg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=dw9C/f4IqZhwxyvN7IT6z5FUu5QlG4BkKgSoNiQteKY=; b=aCTNkReBIl3k37ontklQeiByotom297ueugpjyjEBhf+q3TR38pKVyPcEga8AdPWvzo6VSKK4KLoF49AMTYBWnAJ+BfvI/EsvbTgmkj4RC5OfLbYPDMTPw4dhw/8RiBi+w9NNTLQohASkK6jjUfoYzGylKRXGcjRpUavFCGXLsTWM+pGoIXYUKwHLFNQyn1uFhpu/1TftE7dUcE2gXZx7kCnnupYTyfX3d00XnX7bntS+zEhQb47gfpXLJ+aDwu8F/NL9pJq+jvtCAZTytA1P9djoka/s7m0+eWdXIuzdKUhD3KkL1jPjbhar8kJzN06acoj6t0zvS47l9OQrgJmdQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV8PR12MB9620.namprd12.prod.outlook.com (2603:10b6:408:2a1::19) by BL4PR12MB9534.namprd12.prod.outlook.com (2603:10b6:208:58f::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.21; Thu, 23 Apr 2026 07:42:10 +0000 Received: from LV8PR12MB9620.namprd12.prod.outlook.com ([fe80::299d:f5e0:3550:1528]) by LV8PR12MB9620.namprd12.prod.outlook.com ([fe80::299d:f5e0:3550:1528%5]) with mapi id 15.20.9846.019; Thu, 23 Apr 2026 07:42:10 +0000 From: Andrea Righi To: Ingo Molnar , Peter Zijlstra , Juri Lelli , Vincent Guittot Cc: Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , K Prateek Nayak , Christian Loehle , Koba Ko , Felix Abecassis , Balbir Singh , Joel Fernandes , Shrikanth Hegde , linux-kernel@vger.kernel.org Subject: [PATCH 3/5] sched/fair: Reject misfit pulls onto busy SMT siblings on asym-capacity Date: Thu, 23 Apr 2026 09:36:47 +0200 Message-ID: <20260423074135.380390-4-arighi@nvidia.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260423074135.380390-1-arighi@nvidia.com> References: <20260423074135.380390-1-arighi@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: MI2PEPF00000B83.ITAP293.PROD.OUTLOOK.COM (2603:10a6:298:1::419) To LV8PR12MB9620.namprd12.prod.outlook.com (2603:10b6:408:2a1::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PR12MB9620:EE_|BL4PR12MB9534:EE_ X-MS-Office365-Filtering-Correlation-Id: d590ebdd-0d8c-49fa-5f9a-08dea10bd3f6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: Hj/CtHYCRHo3jy7OJ59l+I9P/EZtiiXfzWYSfxiaIf9vGGpD6BuId4d0nUC+ITF6Cw7qZjyNzcjQLsGPehq9PRU9tzDg6H4qXlF6+Q1scCUeJwVQ946wakVAQcA5HTtojy3g4bYtPMMCiGEonXxU289TsoQBKgL7DBoPOxRwkWFzcvOpDxUj9VddKV64WzN5hkH0WSevaQ6sKGlIGulxyvT7WN1UvXNNVxc+7+v43oQJN9U0COEfiL9mNyCoB93ugZnHoAuaM5M6lNbIkJEZZbQA53U2TkBbFp6d9NkQ95J/sTkXfh3XJi2vHyWNFj70DqSrkwHy9FOWxQuZdXh0sAlM8JnYfYoZCpquNdfmKHSg6MuA6Jku6VPRDI5TKPKJY7OwkzAPyfjCmTf5+f+sV3c6RY49DGpiMusq5nw0KxBHP17aMU6trhJGEiAkL40hBm0VkUBiJHOOEUt1Ji2ZoaeRBDr5ygVSsLBSfkakSzFkjCPOVjZxg23ZZuTHtEGuBZlafg27yABIaGOfW4HYYX70ftny1dQY/KHrUMwJhpzc3a0UEOa1vDBUR0E3V9XpHRHufHRGnhJOEpiTIELwVUcFCZXeoesmQK5QAEck98D0Mg5Bb76kyoy1VqIMQFA7g0gGsWX8PmcAvsJChh0i74fn060N2HlrsI3n+seX/A6uEsPL/kf3SXLcH5RtcpYCpgCTKOWVWTBLsrUHIgro/1L7Ph4HnGUwKScJnIJGzd8= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV8PR12MB9620.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?eKHVawEfcVrFf06n0Dqy+Dnj9YmZpVmhgxjzdoAV9YzKvXMRzWzgHxMwXwZE?= =?us-ascii?Q?zHWNurSfg0MgatUxkbR/y0jXuAqAlycaKQiYRmVVyDe/SazVU75Tn+kT/c4L?= =?us-ascii?Q?owNqYnlWThy+y7jRPSMntC5g2kpbEw68CYjKgGoVO4TG0Ax1u16E2Q77D8nr?= =?us-ascii?Q?izq5jlHQnr0VtfYKOO4fajTG91Ft0ALX77AHtL0wsV4CBSgYCf+max3eAZfo?= =?us-ascii?Q?T7hXdNGgAKJ3OlrW1dFyjIiy24Rqnv2TqE7N4UZsm7RH3ovnJS2LOf7BbsHL?= =?us-ascii?Q?kSEn5bCzPysgJqTaeGnIN7YQ0y9Hs7u+xllouvpG6QJp1AKPsVQDz59rBb/j?= =?us-ascii?Q?UAt4w7YJCfPmhO4lFIV70uGEOmDdC/y8vp3rvF9FjMc1RhLejp4QV+tSQG+y?= =?us-ascii?Q?9/F6fz4mzf56DpLTNnULodDHG7tLBOB7qlRz59lilDaGMTEOv+cmN8InEqge?= =?us-ascii?Q?tHJy2uFPXeIonSME0NepTlB5J3H4JZ0ukkkMrVb9j1cPWSzjqp9uNTK6s2TX?= =?us-ascii?Q?pSI+obxYd6gj1Q17cm248O0XEkCBQeKF0DyZ9rIRGYwf9JxMe+G2uH3SRYlR?= =?us-ascii?Q?gdzzVD5p98r/ZiKd+y8Q9fR35p0QS7J7qNLzOBzW94pmUIzZU1vwRtC9BDwp?= =?us-ascii?Q?xV01dvrI3XGwGLN2COyN0DAWq6kf3SvpZIxp0wLdpuirSQiQi01FoCzLZKMY?= =?us-ascii?Q?GdB4qSVH5RZjRXfTWsP5PuG0rLOcMXmzVOm90Go30gRNpnkluKuQVCANS4Zf?= =?us-ascii?Q?C5IsVscUna9C7FfInO1sLyoNsJAbvSuFswUbVp7mfeOEavadL+x/jwXOt2Vi?= =?us-ascii?Q?CmuGY4oocfHlm9Xu1qjijEoy47SsfuwhM9Qk9PWxCak0O2tVC4w3AymVkTYP?= =?us-ascii?Q?bJNkWIres6Wj8duT3WMqoydXY7h2KpHwqH1kHUIxUkpkUgF/oV0SSZk7a06M?= =?us-ascii?Q?WT+D8DesjCONAEUpk0kQfjSm6URd9vS9WDbAiPy4OZg2IL6H5ZlRjk9iEEw7?= =?us-ascii?Q?t0VSAi+zBNLjSEmQeSubdBHljvth3XNLrCqjjcR4i4WbevAXpb/etMlo1PUw?= =?us-ascii?Q?97bvAVojrOacebXo4AXj3qH5/1cBv4MRIvUuz28jA93lZbF4qvNn45hUB4L6?= =?us-ascii?Q?Kp87wdX34Go1SfkLArcoWogJ64j/llERegov68JCZQPwNJTgClJLq9aeU9IW?= =?us-ascii?Q?GKxOB12gq2ddpxUHzbE0pcd8bDXnE5sB+i45ndKaDi02p+v0H8eZ5bZ/Ukxr?= =?us-ascii?Q?0PsDp8JjDt/iHggV+EZAcOjCSC4gfxTi419ilSmkgi6emA5+EQuv0r24HyPq?= =?us-ascii?Q?hWmf/4kCQK3mmAGKGA/7m/Ukt7k+o9YJbZ1M6OPbvAuuBOUrTifZFoJxZ0YZ?= =?us-ascii?Q?N5maNtT4rWrsKD4OR65B3pk3QIPASubE1XNAptYkFJ0Uvr+VCjSfeOMd148U?= =?us-ascii?Q?EUbBqf2PCVBFFR2PnVwH5JuAbGp650nJsL2xRmNxYGUVrxrMccZfTXg6A0dq?= =?us-ascii?Q?1AYH+OeZ2bqzZSweN09uYjhSwez9BweLNpTJYTFFTtkngsxRSmBF4HC9Avvm?= =?us-ascii?Q?yY10x8ubQnv7pRqGyfKzuzD9LWRyFvJKkW55ZWE3MRxRQBfXKQ1YkHk2UITp?= =?us-ascii?Q?3RsnXwmbtkX3DEQXLKKRWXbWYJ99p4jEFbz8Hbr3IxiLU7pFOxBZnYK2a/a4?= =?us-ascii?Q?cFIvjGdsnINgw5czKRLT3rF+ysNey5J4SmnM+cgWTuR/i739UsdwRPbbyFgK?= =?us-ascii?Q?LUPJbB3jxA=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: d590ebdd-0d8c-49fa-5f9a-08dea10bd3f6 X-MS-Exchange-CrossTenant-AuthSource: LV8PR12MB9620.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2026 07:42:10.8050 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TELFiUqlZTaWHR6prnyN1Qk5576SaONgccWDr0kUG3ykppKVcZLt3dZ0noLWpGCajEbSaad7fMuBNaecKnA/eg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9534 Content-Type: text/plain; charset="utf-8" When SD_ASYM_CPUCAPACITY load balancing considers pulling a misfit task, capacity_of(dst_cpu) can overstate available compute if the SMT sibling is busy: the core does not deliver its full nominal capacity. If SMT is active and dst_cpu is not on a fully idle core, skip this destination so we do not migrate a misfit expecting a capacity upgrade we cannot actually provide. Cc: Vincent Guittot Cc: Dietmar Eggemann Cc: Christian Loehle Cc: Koba Ko Reported-by: Felix Abecassis Signed-off-by: Andrea Righi --- kernel/sched/fair.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index d0c8bcc0d96a1..9bd9dc6e0882e 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -10815,10 +10815,16 @@ static bool update_sd_pick_busiest(struct lb_env = *env, * We can use max_capacity here as reduction in capacity on some * CPUs in the group should either be possible to resolve * internally or be covered by avg_load imbalance (eventually). + * + * When SMT is active, only pull a misfit to dst_cpu if it is on a + * fully idle core; otherwise the effective capacity of the core is + * reduced and we may not actually provide more capacity than the + * source. */ if ((env->sd->flags & SD_ASYM_CPUCAPACITY) && (sgs->group_type =3D=3D group_misfit_task) && - (!capacity_greater(capacity_of(env->dst_cpu), sg->sgc->max_capacity) = || + ((sched_smt_active() && !is_core_idle(env->dst_cpu)) || + !capacity_greater(capacity_of(env->dst_cpu), sg->sgc->max_capacity) = || sds->local_stat.group_type !=3D group_has_spare)) return false; =20 --=20 2.54.0 From nobody Fri Jun 19 19:37:46 2026 Received: from PH0PR06CU001.outbound.protection.outlook.com (mail-westus3azon11011010.outbound.protection.outlook.com [40.107.208.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A3FF318EC7 for ; Thu, 23 Apr 2026 07:42:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.208.10 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776930143; cv=fail; b=k57rPJIjePlY2qbwpEBB/VMptOU5XCfLjvHA2vd8GGLhee7u9HWUp7pkUL5kzlt6WAXDiFAj35hxcwGI4WX533NzJzMX7d7tUkBbapg7PhIQ5u4YKI3sHDUu18tTxj9UlPw2u+y6T1aXdDAikyx1a+XKTeFYi/fqUq1n13eWcOk= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776930143; c=relaxed/simple; bh=D0VdJpQvb6kd8tDeUdvs8QeBLKMFQxI991RK+6Mww4w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=M4XJxfhOCzxTf+g6Gl1fu7cO7UHzqFL/t9Ymohqs+p48wYOGh8ej9xnThcM6uZvusZP2gpn0umfPe09w9wvMWESgWtjb07eR6wwokaoppglWnRi5+tJGSH8DD4+nlv9p7gegI0dvl2iQfcGCh3nqdNBEd2NBF7x+IsoX+JTeTRI= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=kkLM9kmi; arc=fail smtp.client-ip=40.107.208.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="kkLM9kmi" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=EIv0XlsIwpOYrsXibVvDVlqg3axs2rUlInYnhTrlMQRsiShKr/73cbnmiHFqCfpV/bYRzFN3waINXeWKwUqSTVfI/F4RJneODYuvIK+y/3Hc7Qe8GAk0/wcmTAiFarkoLX6uIKE5cq+hGmTTEs3cll/RFqVijqaPnHzOr24a59SUVicqco98FxYvPMosu1/W/xKc7jlfLq6cQo6tGQqMLrhaJIMvS01CM0rK5aiFLA4A6Rkb5CWuwB7G1eHA6A45t4CjrDn5308dRcD3h3nPviGjOwd82G/Cv48ua9GSXcXoa5aAZ+qABczXc5dirpQ2EuPghl+GoWhjt/C+0CfKYw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=rnKZCr+CKynR5sVFBMuGcdYlXdi8ckSGT73RYZ7sQlc=; b=n59ZZwU8FWkg1bSEGNmw8fcUJ8vMKB7rCSbZ0Ik8fB6iSe3jFOcB39GgxTMzkwXFiJjMzj0vLJXPU/zSkD4BFcHEvoPnervE/iQtjWtzr6quNFjMEOBZWn6nSjWBVLAFQf6/eYGXIUb/GDkPHhi5ztqsZFhNi7Cuj+4AFPHhx/SdMLJlvaFQhusUX5V1zhC091nJg303IMn9NiY9s/0/HyKW77QfZHaQ14kXabSL+zfRO2h0MGRLmE6a5Pnep9PwyR/dwaoW+CvDZNRGULOnCsFkGfVZu8w69S3EMENHQfeY/kvIFKclDnJi2eq0qdeTexjtV0t/CJI+OkMrPZOzKQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=rnKZCr+CKynR5sVFBMuGcdYlXdi8ckSGT73RYZ7sQlc=; b=kkLM9kmiYHEqPaLshoUxuDOefqgvuI/TcBpQtthQ0vxd30fcDtFEu5+nvTo0nd2cWhGjKmlyjR2rlouirZGyvxovnzvsTuOTxAFY388B+uEGucFIn7q8IcWk0riK9ijeVKv0IqapyPyq7yYkCrt5vzb+vhZ6G1RUnkItF821C2i7sjAWoFArOHheMQqy2yk6WzwEBUfvAOQlDABYApvasaN6oTDxf6sZEm3zuIhDulOxvi/JwwYd25lk9qCQ/dPxWvvZy9Zgw2nxyqsVtHUp3435SH721mH5E8kD7wNL+ijqy8fLcHel2MMPe+zToJ3WUunoteJhVTZcdYPGb+ZF4Q== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV8PR12MB9620.namprd12.prod.outlook.com (2603:10b6:408:2a1::19) by BL4PR12MB9534.namprd12.prod.outlook.com (2603:10b6:208:58f::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.21; Thu, 23 Apr 2026 07:42:18 +0000 Received: from LV8PR12MB9620.namprd12.prod.outlook.com ([fe80::299d:f5e0:3550:1528]) by LV8PR12MB9620.namprd12.prod.outlook.com ([fe80::299d:f5e0:3550:1528%5]) with mapi id 15.20.9846.019; Thu, 23 Apr 2026 07:42:18 +0000 From: Andrea Righi To: Ingo Molnar , Peter Zijlstra , Juri Lelli , Vincent Guittot Cc: Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , K Prateek Nayak , Christian Loehle , Koba Ko , Felix Abecassis , Balbir Singh , Joel Fernandes , Shrikanth Hegde , linux-kernel@vger.kernel.org Subject: [PATCH 4/5] sched/fair: Add SIS_UTIL support to select_idle_capacity() Date: Thu, 23 Apr 2026 09:36:48 +0200 Message-ID: <20260423074135.380390-5-arighi@nvidia.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260423074135.380390-1-arighi@nvidia.com> References: <20260423074135.380390-1-arighi@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: ZR2P278CA0065.CHEP278.PROD.OUTLOOK.COM (2603:10a6:910:52::6) To LV8PR12MB9620.namprd12.prod.outlook.com (2603:10b6:408:2a1::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PR12MB9620:EE_|BL4PR12MB9534:EE_ X-MS-Office365-Filtering-Correlation-Id: 58aa1e32-aaa6-4679-318c-08dea10bd8ac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: Eb9c+1n/ogFPVst7Hye+5JehsXb0fqBvaRfCHBL0NX10Lk06J6a8ZyooOAfHkok3ejL+P9SRt29IiEsGabipV8KCbgbYffNH364t8OLkWwJe7psbWDNsWQC9lgo4GppnpB4ZiHWnoEdJ0jrqq06Aac5/aE8Hmx9PvfYREOqVQAz6+cYC+4M6o3P44g87GV3oP125evJWLyarz0Gc6R9TMJXbC0kZ+ffyszfGx/xV0JbnaSeUht118LrI0Eew/niQD2Whj3vNWdx3ld6AXuMMLtuN0WzA8nMXpUmkJaLM93LJh0egIZRfU4TMD7QLg3JjsxOr/ZGAoD1q8ZhgWOj2hNcgFaPrgz2oWMnmEvv+O1aiQlN4HXuZqEky/yT0r2nEkOpx3LSEd+a1R6XR7sHpDEirlHad7EikJ3eq2l0Uo0RKZPvlrMTug2Ie2j/1PLIdObBUIggAKIIkyDxqngvgNU40qbcWYK1gCv5yxey/KTfAzEpox2JgHR8C26mnrOO+eAzDW2B27XO0RmRmGu1UVnVI6cwsR0dc/GxavqodUwjwjsJ9RUTkwPNr2kjograc5jX73yn+HR/y7Zabj/2kGBCDvYiB+DrfHCzWqKOCg+IbVwPoDIa6Cgyy8N4tMhz6ID532BIyFA75uVm9RGjg2XsYYlI6sh375eMoD85BeT3xjWxZBBaR6pL6DrEyEc8MCA7cK/SjaMU1lvRMNVFsMHjszOekAnEu2OxIgXLuLNI= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV8PR12MB9620.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?Jl0q4VPr/t5IwWiupNdPLITGWBhRGFenZn0MwBHTWHw31DSgRKpS3y+BLj/N?= =?us-ascii?Q?jyCW+Vy2qA0U9SI/KcDZTjUKZB0s5H/NGkt8DvyJ4kODCeiSN3qVo2hv2Rwd?= =?us-ascii?Q?AKHjzR+ihwWYOkadJ10mPIPgAX8QQR+efNNGC1kUqIlmfIoOjUrOkam+dqmr?= =?us-ascii?Q?DxQFjS4MBKcaO2qB610Kmf53AGtMUEKbrwFdX5wW8DM+r+Pow/gtP0gNlz4f?= =?us-ascii?Q?9LhK7I7LMt1Dkg09jol1I7RRdB+GpywQL5mig4TD+tZT/NknqrecupQfVek2?= =?us-ascii?Q?soLRUVDztFAn/T/GebeJXCzw5LC+778ZWtz4ICGnUSPs1+jnfL4Rca34Ma/c?= =?us-ascii?Q?iQOJgx0KwAFC2om1id9jvX0fPuNvTu8VA3w9A7gpwUe6PqTUyoxM4a9WBATC?= =?us-ascii?Q?YPWq5jBUsqTvH/tEtr9SkRgjtQIXDDl24+t5NxncXLDQz9/YQhKm4ND5/wqN?= =?us-ascii?Q?lDcYjxXyz/rDVH44obgklh99d1UIfYrkOcj8ooA6TnFK2CUsSJ8BXns0gzH4?= =?us-ascii?Q?qRd2+brsz1oUntp8ao1uOcAY0Pf535o1hp53eb9ZeaznzU7st2jYFmwoyE8q?= =?us-ascii?Q?HZIjBGr/RULFJ91ZdgoEWbocjtfYo+CdWGX5ri9QNQ55SlW6/Ll4ZLwt1oJc?= =?us-ascii?Q?VUp52tX3APYWWisSVGNwzsiRtrYc+wC6uIN3D54UWZ/1LBJXt3myPGJBmqaA?= =?us-ascii?Q?dsnSAI/pFraWpvQVypkG2i7Zb/12iydHjIqQgJPrxrWuh6t/nMTyWxFi5suO?= =?us-ascii?Q?RH64F0LOjdWVpYxZgw6dj4OX/WkM0aBFi5MQZ1pF6P/w+8IEmHrOZdNyOHJW?= =?us-ascii?Q?35p5zgwrS4kr6HDzEiptVLVb/Rs5RL1USqjMY7lBK9wdBCdjG6JxsILpOq6c?= =?us-ascii?Q?lbvQ1kF/O1Ocd828fUAKyVbvQ+KPsFaIo0JJdDf5cSZX4/MOrUbsPtGvTP3B?= =?us-ascii?Q?HCuNyoKFnzOiw1tFzvucn8omGT/K0yPQjF2/8X2d1d4ueEWYjnDTE/WQC6+B?= =?us-ascii?Q?6/Ac1K/Eu9SUQkOfFyume4Tmphrey/rUVDVmb5qLAkMEg9e2v0cMsUNpVmJX?= =?us-ascii?Q?b5fPhT+85D4vyYU6MfLWvsemhSvsfrBsFb7Tq9vGWrOiQGamrs4BiYq/IAFx?= =?us-ascii?Q?bMTE+sbhuJl8JsqYC4EluJ6kzROygrD7FD5D4jCdVt+Fn2IsoeTxp244l55G?= =?us-ascii?Q?r+QIFemst/Yf5ZpwZPeWMUrLQkhQKFphOv/G0ClNsuO8qlZN3rS7BWr9sY9g?= =?us-ascii?Q?EfCO/y2U0pmvGccv8NdwYeHRuqin71WR8ykqphEgoKe9NTWkpvz2Z3tKSPd4?= =?us-ascii?Q?6SoOYbrjQSLRiTyPKYRiWG4OoXKzjiWmfuwiiywhlbamqq0LybY0VCFntusP?= =?us-ascii?Q?CNXu1Kkmkm+ywI8g1K/uPOs2QNKV3HSQe55TpnuIFVliimQjgncDWbSOXizW?= =?us-ascii?Q?Xm9u8URu2f02C/g3nYwDF9+vq025g6wDDfvtO/K/Px6jsWN1hy9IJQ0B4W7m?= =?us-ascii?Q?DzDffTFNCf+8fZxgozpMLKPe3OH3XfKozsdDGGo0mzMQxetzlCpSJD9q3vKt?= =?us-ascii?Q?VktVMDzNRXKA+lrOfpp2jYrlRHQ7nd/SqC5UzLn/7MifJIj1adkMyyo52oES?= =?us-ascii?Q?aIKotTxAyFG9dHS3zPwYGJ/ZfO2Hlx3S/CxJ2MCyjzlY00WKDO+DsozlOxH1?= =?us-ascii?Q?eZfok9FUfQwYdCOzgEf6kzYV/PaEUQDYBSicfvG2dMzPKkfrSNSpzeIlOdIy?= =?us-ascii?Q?cb0SzsuDHg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 58aa1e32-aaa6-4679-318c-08dea10bd8ac X-MS-Exchange-CrossTenant-AuthSource: LV8PR12MB9620.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2026 07:42:18.7205 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: IX4NQaf3Z16QXWTRIsXXI+kQN/p0RAZGGzWhn4kjNA6pZzWd13yoWgy0sRdpe7H70P2peb4E0VL9i2Ae2dQmaQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9534 Content-Type: text/plain; charset="utf-8" From: K Prateek Nayak Add to select_idle_capacity() the same SIS_UTIL-controlled idle-scan mechanism, already used by select_idle_cpu(): when sched_feat(SIS_UTIL) is enabled and the LLC domain has sched_domain_shared data, derive the per-attempt scan limit from sd->shared->nr_idle_scan. That bounds the walk on large LLCs and allows an early return once the scan limit is reached, if we already picked a sufficiently strong idle-core candidate (best_fits =3D=3D -4). Signed-off-by: K Prateek Nayak --- kernel/sched/fair.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 9bd9dc6e0882e..6b67049f04c3e 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -8002,6 +8002,7 @@ select_idle_capacity(struct task_struct *p, struct sc= hed_domain *sd, int target) int fits, best_fits =3D 0; int cpu, best_cpu =3D -1; struct cpumask *cpus; + int nr =3D INT_MAX; =20 cpus =3D this_cpu_cpumask_var_ptr(select_rq_mask); cpumask_and(cpus, sched_domain_span(sd), p->cpus_ptr); @@ -8010,10 +8011,30 @@ select_idle_capacity(struct task_struct *p, struct = sched_domain *sd, int target) util_min =3D uclamp_eff_value(p, UCLAMP_MIN); util_max =3D uclamp_eff_value(p, UCLAMP_MAX); =20 + if (sched_feat(SIS_UTIL) && sd->shared) { + /* + * Increment because !--nr is the condition to stop scan. + * + * Since "sd" is "sd_llc" for target CPU dereferenced in the + * caller, it is safe to directly dereference "sd->shared". + * Topology bits always ensure it assigned for "sd_llc" and it + * cannot disappear as long as we have a RCU protected + * reference to one the associated "sd" here. + */ + nr =3D READ_ONCE(sd->shared->nr_idle_scan) + 1; + /* overloaded LLC is unlikely to have idle cpu/core */ + if (nr =3D=3D 1) + return -1; + } + for_each_cpu_wrap(cpu, cpus, target) { bool preferred_core =3D !prefers_idle_core || is_core_idle(cpu); unsigned long cpu_cap =3D capacity_of(cpu); =20 + /* We have found a good enough target. Just use it. */ + if (--nr <=3D 0 && best_fits =3D=3D -4) + return best_cpu; + if (!choose_idle_cpu(cpu, p)) continue; =20 --=20 2.54.0 From nobody Fri Jun 19 19:37:46 2026 Received: from BN8PR05CU002.outbound.protection.outlook.com (mail-eastus2azon11011061.outbound.protection.outlook.com [52.101.57.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 115B031E849 for ; Thu, 23 Apr 2026 07:42:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.57.61 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776930149; cv=fail; b=u35Gv2vV/c84d525QXpxJAmcYsCxVWgyD6+kfJ2MdU2uo0qcmy8F77hJMW8t8d/30qICXZnoGKKHJr8CwysAWiUaul/jdhstVemmrUCuGyfF2vTHJxZYutSU2Pw2rotvVbp6B8kJomuVRRRTqXsol/CGWs4iO9xEsAKk2x1nbSM= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776930149; c=relaxed/simple; bh=lrSeSC1H9DMwYqKlzy/ePfMH2oWnVssi+PH5GXB4rRQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: Content-Type:MIME-Version; b=NG14RVxdzTZrrP6MdFCKiyDs8NIYRIR/5Skgy2qvKEE2cAPHyqA6s45U+0TszOAIt73s42M02a0uDgOnVHnFNd+iR5kyJ2QBnxKvz1nhUhvo/Sj5u5VY1jqOdgMNTU0xmtm+CM3B8Ed2ruLvlpFid3mC0/glAlMqrR11CCiGX2I= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=JaoEOknQ; arc=fail smtp.client-ip=52.101.57.61 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="JaoEOknQ" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=S2nsixzZ1+Jo4MWtvk2OVwqn4AhpPP/RPBy321wiVucDoeU5BJkbXBX7fCcsThl0lwEEgiis+ESAsXlhR5tIAs9PGTCEqkd59E2u89jzWvH470mWVY/C3Z58/YgKH4mQflOMv0VjkjBSEyGD1EHhk6Vik2WQxtLXTGnSwOsRo5Y1n62XOCgQKrNnUjcZYat6Psuch3jkIW6PQspIvMmRXlSNeLAVGule6madtFUc3bGKCMsHhMynFGqpelo17eC2yp3+I0wd+1DGVjaLDuqSbQRuCtKB0wRYybA14uy52LBEPZ3JxZjh/BNDF7+duT0HEKl0sTvzGbaZWpOkJUoQJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5GMZgRoNQMeJNjL3E3vke8JFqxIVz/9IJdI61UOogcY=; b=wOyk7+TroPbc70y7gGgqxBtbrvt29kHnRiD8JZL/1+3ljUNKew6fvVnqsGBiHAALaWF4xKqd693Yzt5b7qq1Z/MVl8Ra9Jy+EQ5RVM+0u5cIJUNB+kelmHOxdzamEkIoE/WqgY0jIyhwilw2BVisGA5rH49/6OfXNPITxjbA/5exp42TvTx46c8MvU2Nux8FC12cC4Fp2TOy+/8nHvNUUtdLu6KAZ0KoBNmu5tBjZUu6I8Nm0s+N4RMUUXQXLWIxYUikk2+gQrAC6sv09jMsDECMhKE4HKIvf6ClkwatzYd/P8grMWFPDgBYGt0DHFJ1r4TkF/ySL7KWwPHPtctsIA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5GMZgRoNQMeJNjL3E3vke8JFqxIVz/9IJdI61UOogcY=; b=JaoEOknQdm5V6q8ukqRD2KrX3MHLpIKe9jONMM+VAmoEF12HHwUt5RjJAmsYD1RyVEpdip0JPgsulO3aswu6oqQ+8nuWXZog1oOKUNNsRf5O8vZ+ERXZotPYf6utKiIQyzFrt4hA/7Ni/m2JIygD2V4vSwXPqsjVyJarWIwyEDz7mmUfyedNvkLmfqrJ5t2uNSwM6bdh+9OmRHyfQu+j0aSppENqHfHGe+2ChDx5QCkxo0fGfciyPY13xO1xr4MyMgDr3k3LS0am+9qkf6td0cyQbtjRYx4pu8hSYa2xBHufCj5Uv2qJJxg/J+YNKl4eZvZtZef7r6kixPQU//yCyw== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV8PR12MB9620.namprd12.prod.outlook.com (2603:10b6:408:2a1::19) by BL4PR12MB9534.namprd12.prod.outlook.com (2603:10b6:208:58f::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.21; Thu, 23 Apr 2026 07:42:24 +0000 Received: from LV8PR12MB9620.namprd12.prod.outlook.com ([fe80::299d:f5e0:3550:1528]) by LV8PR12MB9620.namprd12.prod.outlook.com ([fe80::299d:f5e0:3550:1528%5]) with mapi id 15.20.9846.019; Thu, 23 Apr 2026 07:42:24 +0000 From: Andrea Righi To: Ingo Molnar , Peter Zijlstra , Juri Lelli , Vincent Guittot Cc: Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , K Prateek Nayak , Christian Loehle , Koba Ko , Felix Abecassis , Balbir Singh , Joel Fernandes , Shrikanth Hegde , linux-kernel@vger.kernel.org Subject: [PATCH 5/5] sched/fair: Make asym CPU capacity idle rank values self-documenting Date: Thu, 23 Apr 2026 09:36:49 +0200 Message-ID: <20260423074135.380390-6-arighi@nvidia.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260423074135.380390-1-arighi@nvidia.com> References: <20260423074135.380390-1-arighi@nvidia.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SJ0PR05CA0183.namprd05.prod.outlook.com (2603:10b6:a03:330::8) To LV8PR12MB9620.namprd12.prod.outlook.com (2603:10b6:408:2a1::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PR12MB9620:EE_|BL4PR12MB9534:EE_ X-MS-Office365-Filtering-Correlation-Id: e767cc49-6f1a-4838-4a51-08dea10bdbca X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|366016|56012099003|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: RyxCWrecRHL/CvWhqVRmVBY/IY7HbPOro4K2IcpX7Rf7gJzZdUDGsBBW63q64gbDfAQAKTjZskzB3YFHkQVncznrnqaawBeN905my0ekYOv2ubMsjQXdkTI2EIRGK5B8KL7TKewKljPi6HH7rqsE0Pp9bccDqS4QkAKP1TUpvsiJehRQl3ntGF72gyObTlxXliIBmsOgysaTtgyFJWT08hbUE+txTE4PSKFbprL6wTVnYVNvRA5lFr4mJLLAJU2pxi171p5ZHJECNtmO6sE+uA5MyhcMj1tNSxkwOKkXffKPsUuzXB29juB4rERs8v1f62dVOAgk676j2siXwmNJy9OWPn1EHXMzdNK5AfNtcXjZjF3wG3VCB/pr5LH20kx+kN4pyWYlYCPi8ucC0EKJUgRjt0Zdonfq+UB4pengbVnAkNZtOef1y6iJ6HMzIFS1qh5quPdgRdFNMgivGghMz4NT1LOK4aqwGx06djXAa/y7RxEC4st8RcDwQ6+0JOt0K7sPhFM9iazZlkjklVOZ+bsd4TMH2HdssbT1L87snN0fGyYdZSc+TNHSaG7pUCyy31m4X/ZUK9uCRkdb1CgZe8wA2+lnVEWl/oLKxFeYXGbO29zNoWOFuXAGSR5v01aGfCqHnaoHgXkyA1b+hmq+jgdI32ctjnF7WC5BQJKxgz0pcDVL7lF4lvpw5+sAXELhLeFR8xypEgTSrwoEkQdAJmaYVutDITI/WIWa0Ox3U9Q= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV8PR12MB9620.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(366016)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?MFjfLWyEjhnrAG5pF7CjNDisVwWVoq4RkUzVKGD379mh0O7+2mQZ+4ZxYOTz?= =?us-ascii?Q?bwMlGoIw/Mp5OpU7NCIOmNQbXljdkMfg1LozZ+vV8z/+qZ9WZF+cq5EpTepF?= =?us-ascii?Q?6ZgALGdrSA8eiR9F8+XaPvCvM5Gc/7mcNRu2ethpFkMzRW8F2NXo2vAcgNEI?= =?us-ascii?Q?F8G+b/txsn+LXgngQ6iHYams4sztEtjgIw6mvnhHDRhmWs8UiAfwLKet0iD2?= =?us-ascii?Q?RvpGyj+NnKuz7YvC74UBLkN2hSAxr3DEf0KC1Jx4H5kWJDYKDuXsLjYMZHeB?= =?us-ascii?Q?waNgJYDLj/ehatbd2WBcgIcopYSCFid7l1jA7BQlYHcPXfVaPdZdFVSauIcs?= =?us-ascii?Q?T+tV0HPlO6Vn/SxXPdFqZvkEsQ9rX93o53XrhxFRFas0eoLpYvZW8IJ9TYyI?= =?us-ascii?Q?UF6mcPDCkqkFr/iO1z1/Yg2feuCpJ2B7GT3uFMZv859W7mEgLgU+1MOuP1ds?= =?us-ascii?Q?A7YsvPaQdUH0/jiCiX3p49aNXk9NMXvoe6i0ooprno+1wiI+y3K1cF4/2HQQ?= =?us-ascii?Q?gtL4qG7qGxCzYPF5/hvc4sQNxshSZfezBF7nqnDnmZ7yQCwnwUHgHEGGNvWX?= =?us-ascii?Q?QdT4kkIPG76+e+nfqSOVWATAb46ejh3YuWaHHHj6ofwjtPr7zm2AxIpeO3Ty?= =?us-ascii?Q?ZRFINKTA9MisGfi6FlS7Qu4AwQDYYmqNDfnhbf/hwyhGvtkfVxdHMcY0ytHu?= =?us-ascii?Q?QLu5fNlgjyKoetnvUTYLNpxIJP4tbXL1FtF3FDpTkzjeBYGKm9oxa0Z1VT6h?= =?us-ascii?Q?38yO7V9OZ7TsEA+5dTCOByBJGtIpJHdUeG89zDfMwV+tQScbgzDgaCs0/NZe?= =?us-ascii?Q?4KoQ2nXu4Acw30x1O03z8axo2LV/0bWjNbYWSs3Y9cr1euJfe1M9Gmah3yvN?= =?us-ascii?Q?reP2mVxF3PNXVH7VlQpRYOPSHT8t1zYiw4Ufpxoa4zyy3BQ95GCivrzY2Vi+?= =?us-ascii?Q?OxIBtS3j+lAJ16ftDnhqzv1Vu3ZEsP+d5xRIu5d7V7LKfaWzvNEqsQTtrhIY?= =?us-ascii?Q?5sbjj+cFrF82/c8PzqaEnFTdTpZTy/WXbXkiCi4NX+e9kxZMTcoC9pwAFZMA?= =?us-ascii?Q?FaTZLouYSasFIL6dD1KQ1aroDSWlAgMuxZsyIIJv2eHMLd7otNb3fbPLBCdi?= =?us-ascii?Q?LmNm8cuxrT2cuc3lFQa+7Q2GNDa9jj4YXyVmqprPM1YP5gNYVGvY6OKuopZu?= =?us-ascii?Q?rUdlw2fgmVRBpp24pe1K/zDj4hXkc4qWkk5CfZAQtXXVMoImOUBr/D07aqOz?= =?us-ascii?Q?ycodzsiUvJnLuDoHhA9oA8cvsl4dfdtm0693wsGUL12e5nR2pmTg5ImKiVW5?= =?us-ascii?Q?W3WkSMwqVEWSZ6tJZ7W6cOcezTNmQY3iLScrZRXnFym+S02SDF2nAjIUVEi+?= =?us-ascii?Q?0N+Dwr7CetSSJ3DKC3rJlZWjU3wdGePy+VJzqQeGgl6PTyA4FIFmrNuP8oH1?= =?us-ascii?Q?Xntj+8IM4jlcq2D2fhYGDfIJwxoe0jm2lL/QbD2T6wrbM7P8lYjftigclOvR?= =?us-ascii?Q?IVv3NOgDwDkz2mwv9nXIVGP0HtQKrdplD+OcQuh7hl+vdpKwK72jnNXnIdNI?= =?us-ascii?Q?tZ2nnWLF2nAPMELeWyHlJJNMvRlWGRZDT7cPobwh/hmPmB1UeMr1DBI1StVF?= =?us-ascii?Q?yMhgKI6XnPf6UU9acFlT8GCRtiyz/1RS8IwdUKVdxt/oKVHdNnlReYwV49SA?= =?us-ascii?Q?JLn+ksCUNB59Kfflq9XDRPP6oxtBsPCRcvtBnx2pTr+P/NTXDLsBUqjgUFDG?= =?us-ascii?Q?kGHFFe583w=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: e767cc49-6f1a-4838-4a51-08dea10bdbca X-MS-Exchange-CrossTenant-AuthSource: LV8PR12MB9620.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Apr 2026 07:42:23.9374 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 9BEKmq5ljpEchlSR2mgn+lpLUGsBVPkf9I94M0V5m0WqklrHmld5Qeh5zkLYS3EMPxDB/ecMop4ki7WP9PV+5Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL4PR12MB9534 Content-Type: text/plain; charset="utf-8" From: K Prateek Nayak Introduce enum asym_fits_state for select_idle_capacity() scan preferences, instead of using raw constants to improve readability. No functional change. Signed-off-by: K Prateek Nayak --- kernel/sched/fair.c | 48 ++++++++++++++++++++++++++++++++------------- 1 file changed, 34 insertions(+), 14 deletions(-) diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index 6b67049f04c3e..a3ecbed43c34f 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -7989,6 +7989,22 @@ static int select_idle_cpu(struct task_struct *p, st= ruct sched_domain *sd, bool return idle_cpu; } =20 +/* + * Idle-capacity scan ranks transformed util_fits_cpu() outcomes; lower va= lues + * are more preferred (see select_idle_capacity()). + */ +enum asym_fits_state { + /* In descending order of preference */ + ASYM_IDLE_CORE_UCLAMP_MISFIT =3D -4, + ASYM_IDLE_CORE_COMPLETE_MISFIT, + ASYM_IDLE_THREAD_FITS, + ASYM_IDLE_THREAD_UCLAMP_MISFIT, + ASYM_IDLE_COMPLETE_MISFIT, + + /* asym_fits_cpu() bias for an idle core. */ + ASYM_IDLE_CORE_BIAS =3D -3, +}; + /* * Scan the asym_capacity domain for idle CPUs; pick the first idle one on= which * the task fits. If no CPU is big enough, but there are idle ones, try to @@ -7999,7 +8015,7 @@ select_idle_capacity(struct task_struct *p, struct sc= hed_domain *sd, int target) { bool prefers_idle_core =3D sched_smt_active() && test_idle_cores(target); unsigned long task_util, util_min, util_max, best_cap =3D 0; - int fits, best_fits =3D 0; + int fits, best_fits =3D ASYM_IDLE_COMPLETE_MISFIT; int cpu, best_cpu =3D -1; struct cpumask *cpus; int nr =3D INT_MAX; @@ -8032,7 +8048,7 @@ select_idle_capacity(struct task_struct *p, struct sc= hed_domain *sd, int target) unsigned long cpu_cap =3D capacity_of(cpu); =20 /* We have found a good enough target. Just use it. */ - if (--nr <=3D 0 && best_fits =3D=3D -4) + if (--nr <=3D 0 && best_fits =3D=3D ASYM_IDLE_CORE_UCLAMP_MISFIT) return best_cpu; =20 if (!choose_idle_cpu(cpu, p)) @@ -8051,25 +8067,28 @@ select_idle_capacity(struct task_struct *p, struct = sched_domain *sd, int target) cpu_cap =3D get_actual_cpu_capacity(cpu); /* * fits > 0 implies we are not on a preferred core - * but the util fits CPU capacity. Set fits to -2 so - * the effective range becomes [-2, 0] where: - * 0 - does not fit - * -1 - fits with the exception of UCLAMP_MIN - * -2 - fits with the exception of preferred_core + * but the util fits CPU capacity. Set fits to ASYM_IDLE_THREAD_FITS + * so the effective range becomes + * [ASYM_IDLE_THREAD_FITS, ASYM_IDLE_COMPLETE_MISFIT], where: + * ASYM_IDLE_COMPLETE_MISFIT - does not fit + * ASYM_IDLE_THREAD_UCLAMP_MISFIT - fits with the exception of UCLAMP= _MIN + * ASYM_IDLE_THREAD_FITS - fits with the exception of preferred_core */ else if (fits > 0) - fits =3D -2; + fits =3D ASYM_IDLE_THREAD_FITS; =20 /* * If we are on a preferred core, translate the range of fits - * of [-1, 0] to [-4, -3]. This ensures that an idle core - * is always given priority over (partially) busy core. + * of [ASYM_IDLE_THREAD_UCLAMP_MISFIT, ASYM_IDLE_COMPLETE_MISFIT] to + * [ASYM_IDLE_CORE_UCLAMP_MISFIT, ASYM_IDLE_CORE_COMPLETE_MISFIT]. + * This ensures that an idle core is always given priority over + * (partially) busy core. * * A fully fitting idle core would have returned early and hence * fits > 0 for preferred_core need not be dealt with. */ if (preferred_core) - fits -=3D 3; + fits +=3D ASYM_IDLE_CORE_BIAS; =20 /* * First, select CPU which fits better (lower is more preferred). @@ -8084,15 +8103,16 @@ select_idle_capacity(struct task_struct *p, struct = sched_domain *sd, int target) } =20 /* - * A value in the [-4, -3] range means the chosen CPU is in a fully idle - * SMT core. Values above -3 mean we never ranked such a CPU best. + * A value in the [ASYM_IDLE_CORE_UCLAMP_MISFIT, ASYM_IDLE_CORE_BIAS] + * range means the chosen CPU is in a fully idle SMT core. Values above + * ASYM_IDLE_CORE_BIAS mean we never ranked such a CPU best. * * The asym-capacity wakeup path returns from select_idle_sibling() * after this function and never runs select_idle_cpu(), so the usual * select_idle_cpu() tail that clears idle cores must live here when the * idle-core preference did not win. */ - if (prefers_idle_core && best_fits > -3) + if (prefers_idle_core && best_fits > ASYM_IDLE_CORE_BIAS) set_idle_cores(target, false); =20 return best_cpu; --=20 2.54.0