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Thu, 23 Apr 2026 09:50:43 -0700 (PDT) From: William Bright Date: Thu, 23 Apr 2026 17:50:07 +0100 Subject: [PATCH] arm64: dts: qcom: sm8550: add SDHC4 controller node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260423-sm8550-sdhc4-support-v1-1-93fd81fea5d9@imd-tec.com> X-B4-Tracking: v=1; b=H4sIAL5N6mkC/yXMQQqEMAxA0atI1gZqbUW8irjQGscMqKWxw4B4d 6su3+L/A4QCk0CTHRDox8LbmlDkGbi5Xz+EPCaDVrpSRpcoS22tQhlnZ1Ci91vYsbT1MOnKOGU IUuoDTfx/tm33WuLwJbffLzjPCzpZMpl4AAAA X-Change-ID: 20260423-sm8550-sdhc4-support-358bf264c04e To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ram Boukobza , Tendai Makumire , William Bright X-Mailer: b4 0.15.2 Add the SDC4 SDHCI controller node for the SM8550 SoC. SMMU stream ID 0x80 was sourced from the UEFI bootloader IORT tables, as SDCC stream IDs are not documented in the register reference manual. Unlike SDC2, the data path is routed via aggre1_noc, matching MASTER_SDCC_4 in drivers/interconnect/qcom/sm8550.c. Tested on the IMDT QCS8550 SBC at high-speed (HS) mode. UHS modes were masked out as they failed to initialise; the root cause has not yet been determined. This board is not currently supported in-tree. Co-developed-by: Tendai Makumire Signed-off-by: Tendai Makumire Signed-off-by: William Bright Tested-by: William Bright --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 54 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 912525e9bca6..5abbe519781b 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -3280,6 +3280,60 @@ opp-202000000 { }; }; =20 + sdhc_4: mmc@8844000 { + compatible =3D "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; + reg =3D <0 0x08844000 0 0x1000>; + + interrupts =3D , + ; + interrupt-names =3D "hc_irq", "pwr_irq"; + + clocks =3D <&gcc GCC_SDCC4_AHB_CLK>, + <&gcc GCC_SDCC4_APPS_CLK>, + <&bi_tcxo_div2>; + clock-names =3D "iface", "core", "xo"; + iommus =3D <&apps_smmu 0x80 0>; + qcom,dll-config =3D <0x0007642c>; + qcom,ddr-config =3D <0x80040868>; + power-domains =3D <&rpmhpd RPMHPD_CX>; + operating-points-v2 =3D <&sdhc4_opp_table>; + + interconnects =3D <&aggre1_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; + bus-width =3D <4>; + max-sd-hs-hz =3D <37500000>; + dma-coherent; + + status =3D "disabled"; + + sdhc4_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-19200000 { + opp-hz =3D /bits/ 64 <19200000>; + required-opps =3D <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz =3D /bits/ 64 <50000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz =3D /bits/ 64 <100000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz =3D /bits/ 64 <202000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + iris: video-codec@aa00000 { compatible =3D "qcom,sm8550-iris"; =20 --- base-commit: 4f5b4b748ac75683d61c304ee3ee0db235e8f312 change-id: 20260423-sm8550-sdhc4-support-358bf264c04e Best regards, -- =20 William Bright