From nobody Wed Jun 17 05:27:11 2026 Received: from mail-244116.protonmail.ch (mail-244116.protonmail.ch [109.224.244.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54E743CAE88 for ; Thu, 23 Apr 2026 04:43:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776919414; cv=none; b=SnG54/L8iilJJiKLGGlKS4q5uDy4mbbIfaGOdishle+30II3jWQAE8X1akjlD1A28/WTmsxWoXtsncctsKhJ+Yz0iL2rb/3EsZj3RmqEiDMvVjRjj0zzhnU5UfUBby978uuFT1ijnqezBoarS9gjdOFOZ0+N6+QyBIeBSFfaGnI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776919414; c=relaxed/simple; bh=9YTHEvkeFZ+qth4YK9gjEe2ZN9Wcna7fcSLY4EhtMlY=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ShWlQaaRh4A2QEiexeDRu3kytoKCbXVwCrLq7NpPdkcTCH8tQ/Iltjtgb2HYDTvyOAM4jPgWfMb6929fGpA8vVyjas0/cP1zK+GrlbYGWuCD1DNBWVxX7Tq+6B2384t0GZKJAdlbQH8vNzsJcNIAz8Z71A7G9NJys6acitbnFT8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=Upn6giTC; arc=none smtp.client-ip=109.224.244.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="Upn6giTC" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1776919405; x=1777178605; bh=ZpoZxI1iv6Hm6E5vmoDrPM6e7FDQ9kxew8Rq9lidrKs=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=Upn6giTCZAD3/96YqFfm1KwHteTlVNrwXQP7kph1hmJcjkS/J3zUg99u0ecq/kM21 hEk55DcVXD+OV5hoR3Yi4XLRDvsborzTqqWSXKAP1Zj1TgK+xyE6eAyLIMPsIKdyzZ Fwox7xn2T66RHfHwI/1QEPnBnlsHDZt4lu356HIcJrE8MUI3CpFDkIWH+FsNxIf1z9 pQWxlYeHpNaT6s2NMwQOUSbPzHjHrNgw6AmsgOPJGdbpJRFZcbNoexuA8wI6wsgehA s27vQ2RkEZiUPPktyOiJXW5XN9qDL+NPFoM7cBvleQUD2VF42ujohGKOb6EWd43fG/ nH6GokLCMQD6Q== Date: Thu, 23 Apr 2026 04:43:19 +0000 To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa , Konrad Dybcio From: Alexander Koskovich Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich Subject: [PATCH v3 1/4] dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP lane mirror alternates Message-ID: <20260423-fix-eliza-pinctrl-v3-1-68b24893ae63@pm.me> In-Reply-To: <20260423-fix-eliza-pinctrl-v3-0-68b24893ae63@pm.me> References: <20260423-fix-eliza-pinctrl-v3-0-68b24893ae63@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 67941d019ba801c353964fadd296df3f09d47d16 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Several QUP lanes have MIRA/MIRB mirror routings that let the same lane be muxed out on alternative GPIOs. On Eliza these were all collapsed under the base function name (e.g. qup1_se6), which prevented boards from selecting the mirror variants. Add explicit function names for each mirror lane, matching the pattern already established by qcom,sm8550-tlmm and related bindings. Signed-off-by: Alexander Koskovich Acked-by: Krzysztof Kozlowski --- .../bindings/pinctrl/qcom,eliza-tlmm.yaml | 25 +++++++++++++-----= ---- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml= b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml index 282650426487..be7b4680045f 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml @@ -86,16 +86,21 @@ $defs: qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable, qlink_big_request, qlink_little_enable, qlink_little_request, qlink_wmss, qspi0, qspi_clk, - qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, - qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, - qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, - qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2, - sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0, - tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, - tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk, - uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data, - uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1, - vsense_trigger_mirnat, wcn_sw_ctrl ] + qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2_mira, + qup1_se2_l2_mirb, qup1_se2_l3_mira, qup1_se2_l3_mirb, + qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se6_l1_mira, + qup1_se6_l1_mirb, qup1_se6_l3_mira, qup1_se6_l3_mirb, + qup1_se7, qup1_se7_l0_mira, qup1_se7_l0_mirb, + qup1_se7_l1_mira, qup1_se7_l1_mirb, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se3_l0_mira, qup2_se3_l0_mirb, + qup2_se3_l1_mira, qup2_se3_l1_mirb, qup2_se4, qup2_se5, + qup2_se6, qup2_se7, resout_gpio, sd_write_protect, sdc1, + sdc2, sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, + tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, + tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, + uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, + uim1_data, uim1_present, uim1_reset, usb0_hs, usb_phy, + vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw_ctrl ] required: - pins =20 --=20 2.53.0 From nobody Wed Jun 17 05:27:11 2026 Received: from mail-24417.protonmail.ch (mail-24417.protonmail.ch [109.224.244.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 826AA384223; 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arc=none smtp.client-ip=109.224.244.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="htpxUz07" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1776919412; x=1777178612; bh=3YpRMe4eq+9kvVEpuEVq/7OEd+FJoQgZ5KDIdTo0/CI=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=htpxUz0734UtkdhxtKXaYjl+9bJFKpw/Q/Cjm6ljTWHpsAOmG+Hc/LUqiKjK4wmYr YC1HEhk3L9zSPymfamGsBVgmh+liHkNhyPHX0BNMSFRBb026y4c9dgMdCYKp/GF0+J mopJLXs8j2NqasUZf+VK2ydC15eLraC5EjXIP77yC1E7nHliV9wbyWhdit9G3sBnTG QLSxv2IO5aLuP1eZLKAqiA6Pak6ZpJwNNtZACvdH7nI/tPni83KBgtDyeWRzOtSnDB t/BgLD7RxA8MnBIKGiAN1RxHBFO+P4nm0tLMy+w2ZP/5MuDogV8UdzaCgVywX72ojJ 3j9X8+Gop6Enw== Date: Thu, 23 Apr 2026 04:43:27 +0000 To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa , Konrad Dybcio From: Alexander Koskovich Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich Subject: [PATCH v3 2/4] dt-bindings: pinctrl: qcom,eliza-tlmm: Split QUP1_SE4 lanes Message-ID: <20260423-fix-eliza-pinctrl-v3-2-68b24893ae63@pm.me> In-Reply-To: <20260423-fix-eliza-pinctrl-v3-0-68b24893ae63@pm.me> References: <20260423-fix-eliza-pinctrl-v3-0-68b24893ae63@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: b256b5bd831f2ac16de20ce2d769ebd9bc005a43 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the function name cannot be the same or the alternate function cannot be selected. Split them up into individual lane functions so boards can specify. Signed-off-by: Alexander Koskovich Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml= b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml index be7b4680045f..fa0177529277 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml @@ -88,7 +88,8 @@ $defs: qlink_little_request, qlink_wmss, qspi0, qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2_mira, qup1_se2_l2_mirb, qup1_se2_l3_mira, qup1_se2_l3_mirb, - qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se6_l1_mira, + qup1_se3, qup1_se4_l0, qup1_se4_l1, qup1_se4_l2, + qup1_se4_l3, qup1_se5, qup1_se6, qup1_se6_l1_mira, qup1_se6_l1_mirb, qup1_se6_l3_mira, qup1_se6_l3_mirb, qup1_se7, qup1_se7_l0_mira, qup1_se7_l0_mirb, qup1_se7_l1_mira, qup1_se7_l1_mirb, qup2_se0, qup2_se1, --=20 2.53.0 From nobody Wed Jun 17 05:27:11 2026 Received: from mail-106120.protonmail.ch (mail-106120.protonmail.ch [79.135.106.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADEC43CA4A3; Thu, 23 Apr 2026 04:43:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=79.135.106.120 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776919426; cv=none; b=VmK6baP8msfzVr+EAqe/7To0sZrgIkrTX6+v2es2BvqzO0n7uw2P8bLdD/K1IXJVPJitnlv3sFJM8u2V59wE9zWkAVEdrm/mUtH3t8zDSo+YKc/YnJx9Qi7vJbDVuxE4T4isIScbKE9p3WWfzUC51ke67+sobw2G+6pbVy8UD/k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776919426; c=relaxed/simple; bh=EYuIBjNnilK0gp+COq4EHzzvltEapk1OHFuqKc9EuOs=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DSuNQCcHI877K/eQkWkgwDY4vZgVh6/ZYn9+okf2IvTOkwxbHCO8tER231qAVrCveh5aMWsXCU9B2FJc4tAqhs5jvlleXWGhRtfifx6VD6S4mA9A2oH2XrtLc3AASz0yLNLQYQCTs9pJ+vALQuWal0CPOKEZudAjNcLFh6iTXBM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=qOE5wfgo; arc=none smtp.client-ip=79.135.106.120 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="qOE5wfgo" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1776919421; x=1777178621; bh=EYuIBjNnilK0gp+COq4EHzzvltEapk1OHFuqKc9EuOs=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=qOE5wfgoZ6XkYiKUSLX1CSqbZCnXclaOfq8EXxgfrnEHPmtyLcYNhgFcrLx9eB2jq rbtacEaKCxgx9EffwDzey/Row9PGEVDZl8AecfGAexO17gnpU9dljgL2yi4Zxmh43n Ft1hnrIY6QKvIBNlQDNY2/s92AuiVPXSg9e+Z7UpcP5uFxOQ3sG/vlsYckczu55Jyi 6BH3NliK2h4klr+pKRMi3MZ6nhKl6zuCWemMUDCXaLqL7hR64MkdgvQBcOkF0is4Qn 6CHBqiWpXn0VnwFJZHamXHQ+2rwhWDxfDo56wy0o0eQwtXEjA62FCzTPlJP6W9HOqO w5wE1aIOC/H5g== Date: Thu, 23 Apr 2026 04:43:37 +0000 To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa , Konrad Dybcio From: Alexander Koskovich Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich Subject: [PATCH v3 3/4] pinctrl: qcom: eliza: Split QUP lane mirror alternates Message-ID: <20260423-fix-eliza-pinctrl-v3-3-68b24893ae63@pm.me> In-Reply-To: <20260423-fix-eliza-pinctrl-v3-0-68b24893ae63@pm.me> References: <20260423-fix-eliza-pinctrl-v3-0-68b24893ae63@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: ad38e37a1334c1dcecef455f2e4a7a67e19827f7 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Several QUP lanes have MIRA/MIRB mirror routings which are collapsed under a single function name (e.g. qup1_se6). This is an issue because it means there are multiple functions defined for a given pin that share the same name: [42] =3D PINGROUP(42, qup1_se6, qup1_se2, qup1_se6... So when you select pin 42 and request function qup1_se6, it will select the first instance of it in this group, which just happens to be QUP1_SE6_L2, making the second instance (QUP1_SE6_L1_MIRA) effectively unreachable. Split each of these lanes that has an alternative GPIO into their own function so they can actually be selected, following the pattern seen in pinctrl-sm8550.c. Signed-off-by: Alexander Koskovich Reviewed-by: Konrad Dybcio --- drivers/pinctrl/qcom/pinctrl-eliza.c | 132 ++++++++++++++++++++++++++++++-= ---- 1 file changed, 114 insertions(+), 18 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pi= nctrl-eliza.c index c1f756cbcdeb..8f74756771b8 100644 --- a/drivers/pinctrl/qcom/pinctrl-eliza.c +++ b/drivers/pinctrl/qcom/pinctrl-eliza.c @@ -563,15 +563,31 @@ enum eliza_functions { msm_mux_qup1_se0, msm_mux_qup1_se1, msm_mux_qup1_se2, + msm_mux_qup1_se2_l2_mira, + msm_mux_qup1_se2_l2_mirb, + msm_mux_qup1_se2_l3_mira, + msm_mux_qup1_se2_l3_mirb, msm_mux_qup1_se3, msm_mux_qup1_se4, msm_mux_qup1_se5, msm_mux_qup1_se6, + msm_mux_qup1_se6_l1_mira, + msm_mux_qup1_se6_l1_mirb, + msm_mux_qup1_se6_l3_mira, + msm_mux_qup1_se6_l3_mirb, msm_mux_qup1_se7, + msm_mux_qup1_se7_l0_mira, + msm_mux_qup1_se7_l0_mirb, + msm_mux_qup1_se7_l1_mira, + msm_mux_qup1_se7_l1_mirb, msm_mux_qup2_se0, msm_mux_qup2_se1, msm_mux_qup2_se2, msm_mux_qup2_se3, + msm_mux_qup2_se3_l0_mira, + msm_mux_qup2_se3_l0_mirb, + msm_mux_qup2_se3_l1_mira, + msm_mux_qup2_se3_l1_mirb, msm_mux_qup2_se4, msm_mux_qup2_se5, msm_mux_qup2_se6, @@ -978,7 +994,23 @@ static const char *const qup1_se1_groups[] =3D { }; =20 static const char *const qup1_se2_groups[] =3D { - "gpio52", "gpio53", "gpio54", "gpio52", "gpio55", "gpio53", "gpio40", "gp= io42", "gpio30", + "gpio52", "gpio53", "gpio40", "gpio42", "gpio30", +}; + +static const char *const qup1_se2_l2_mira_groups[] =3D { + "gpio54", +}; + +static const char *const qup1_se2_l2_mirb_groups[] =3D { + "gpio52", +}; + +static const char *const qup1_se2_l3_mira_groups[] =3D { + "gpio55", +}; + +static const char *const qup1_se2_l3_mirb_groups[] =3D { + "gpio53", }; =20 static const char *const qup1_se3_groups[] =3D { @@ -994,11 +1026,43 @@ static const char *const qup1_se5_groups[] =3D { }; =20 static const char *const qup1_se6_groups[] =3D { - "gpio40", "gpio42", "gpio54", "gpio42", "gpio40", "gpio55", + "gpio40", "gpio42", +}; + +static const char *const qup1_se6_l1_mira_groups[] =3D { + "gpio42", +}; + +static const char *const qup1_se6_l1_mirb_groups[] =3D { + "gpio54", +}; + +static const char *const qup1_se6_l3_mira_groups[] =3D { + "gpio40", +}; + +static const char *const qup1_se6_l3_mirb_groups[] =3D { + "gpio55", }; =20 static const char *const qup1_se7_groups[] =3D { - "gpio81", "gpio78", "gpio80", "gpio114", "gpio114", "gpio78", + "gpio78", "gpio114", +}; + +static const char *const qup1_se7_l0_mira_groups[] =3D { + "gpio81", +}; + +static const char *const qup1_se7_l0_mirb_groups[] =3D { + "gpio78", +}; + +static const char *const qup1_se7_l1_mira_groups[] =3D { + "gpio80", +}; + +static const char *const qup1_se7_l1_mirb_groups[] =3D { + "gpio114", }; =20 static const char *const qup2_se0_groups[] =3D { @@ -1014,7 +1078,23 @@ static const char *const qup2_se2_groups[] =3D { }; =20 static const char *const qup2_se3_groups[] =3D { - "gpio79", "gpio116", "gpio97", "gpio100", "gpio100", "gpio116", + "gpio100", "gpio116", +}; + +static const char *const qup2_se3_l0_mira_groups[] =3D { + "gpio79", +}; + +static const char *const qup2_se3_l0_mirb_groups[] =3D { + "gpio116", +}; + +static const char *const qup2_se3_l1_mira_groups[] =3D { + "gpio97", +}; + +static const char *const qup2_se3_l1_mirb_groups[] =3D { + "gpio100", }; =20 static const char *const qup2_se4_groups[] =3D { @@ -1236,15 +1316,31 @@ static const struct pinfunction eliza_functions[] = =3D { MSM_PIN_FUNCTION(qup1_se0), MSM_PIN_FUNCTION(qup1_se1), MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se2_l2_mira), + MSM_PIN_FUNCTION(qup1_se2_l2_mirb), + MSM_PIN_FUNCTION(qup1_se2_l3_mira), + MSM_PIN_FUNCTION(qup1_se2_l3_mirb), MSM_PIN_FUNCTION(qup1_se3), MSM_PIN_FUNCTION(qup1_se4), MSM_PIN_FUNCTION(qup1_se5), MSM_PIN_FUNCTION(qup1_se6), + MSM_PIN_FUNCTION(qup1_se6_l1_mira), + MSM_PIN_FUNCTION(qup1_se6_l1_mirb), + MSM_PIN_FUNCTION(qup1_se6_l3_mira), + MSM_PIN_FUNCTION(qup1_se6_l3_mirb), MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup1_se7_l0_mira), + MSM_PIN_FUNCTION(qup1_se7_l0_mirb), + MSM_PIN_FUNCTION(qup1_se7_l1_mira), + MSM_PIN_FUNCTION(qup1_se7_l1_mirb), MSM_PIN_FUNCTION(qup2_se0), MSM_PIN_FUNCTION(qup2_se1), MSM_PIN_FUNCTION(qup2_se2), MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se3_l0_mira), + MSM_PIN_FUNCTION(qup2_se3_l0_mirb), + MSM_PIN_FUNCTION(qup2_se3_l1_mira), + MSM_PIN_FUNCTION(qup2_se3_l1_mirb), MSM_PIN_FUNCTION(qup2_se4), MSM_PIN_FUNCTION(qup2_se5), MSM_PIN_FUNCTION(qup2_se6), @@ -1326,9 +1422,9 @@ static const struct msm_pingroup eliza_groups[] =3D { [37] =3D PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _= ), [38] =3D PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _), [39] =3D PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _), - [40] =3D PINGROUP(40, qup1_se6, qup1_se2, qup1_se6, _, qdss_gpio_tracedat= a, gnss_adc1, ddr_pxi1, _, _, _, _), + [40] =3D PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_= tracedata, gnss_adc1, ddr_pxi1, _, _, _, _), [41] =3D PINGROUP(41, _, _, _, _, _, _, _, _, _, _, _), - [42] =3D PINGROUP(42, qup1_se6, qup1_se2, qup1_se6, qdss_gpio_tracedata, = gnss_adc0, ddr_pxi1, _, _, _, _, _), + [42] =3D PINGROUP(42, qup1_se6, qup1_se2, qup1_se6_l1_mira, qdss_gpio_tra= cedata, gnss_adc0, ddr_pxi1, _, _, _, _, _), [43] =3D PINGROUP(43, _, _, _, _, _, _, _, _, _, _, _), [44] =3D PINGROUP(44, qup1_se3, _, _, _, _, _, _, _, _, _, _), [45] =3D PINGROUP(45, qup1_se3, _, _, _, _, _, _, _, _, _, _), @@ -1338,10 +1434,10 @@ static const struct msm_pingroup eliza_groups[] =3D= { [49] =3D PINGROUP(49, _, _, _, _, _, _, _, _, _, _, _), [50] =3D PINGROUP(50, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _), [51] =3D PINGROUP(51, _, _, _, _, _, _, _, _, _, _, _), - [52] =3D PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2, ddr_bist_compl= ete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _), - [53] =3D PINGROUP(53, qup1_se2, qup1_se2, gcc_gp1, ddr_bist_stop, _, qdss= _gpio_tracedata, _, _, _, _, _), - [54] =3D PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc1,= atest_usb, ddr_pxi0, _, _, _, _, _), - [55] =3D PINGROUP(55, qup1_se2, dp0_hot, qup1_se6, _, gnss_adc0, atest_us= b, ddr_pxi0, _, _, _, _), + [52] =3D PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2_l2_mirb, ddr_bi= st_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _), + [53] =3D PINGROUP(53, qup1_se2, qup1_se2_l3_mirb, gcc_gp1, ddr_bist_stop,= _, qdss_gpio_tracedata, _, _, _, _, _), + [54] =3D PINGROUP(54, qup1_se2_l2_mira, qup1_se6_l1_mirb, qdss_gpio_trace= data, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _), + [55] =3D PINGROUP(55, qup1_se2_l3_mira, dp0_hot, qup1_se6_l3_mirb, _, gns= s_adc0, atest_usb, ddr_pxi0, _, _, _, _), [56] =3D PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tse= nse_pwm4, _, _, _, _, _, _), [57] =3D PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _), [58] =3D PINGROUP(58, _, _, _, _, _, _, _, _, _, _, _), @@ -1364,10 +1460,10 @@ static const struct msm_pingroup eliza_groups[] =3D= { [75] =3D PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _), [76] =3D PINGROUP(76, cci_i2c_sda, cci_timer, prng_rosc2, _, phase_flag, = _, _, _, _, _, _), [77] =3D PINGROUP(77, cci_i2c_scl, jitter_bist, _, _, _, _, _, _, _, _, _= ), - [78] =3D PINGROUP(78, qup1_se7, qup1_se7, _, phase_flag, _, _, _, _, _, _= , _), - [79] =3D PINGROUP(79, qspi0, mdp_vsync, qup2_se3, _, _, _, _, _, _, _, _), - [80] =3D PINGROUP(80, pcie0_clk_req_n, qup1_se7, _, phase_flag, _, _, _, = _, _, _, _), - [81] =3D PINGROUP(81, wcn_sw_ctrl, qup1_se7, dbg_out_clk, _, _, _, _, _, = _, _, _), + [78] =3D PINGROUP(78, qup1_se7, qup1_se7_l0_mirb, _, phase_flag, _, _, _,= _, _, _, _), + [79] =3D PINGROUP(79, qspi0, mdp_vsync, qup2_se3_l0_mira, _, _, _, _, _, = _, _, _), + [80] =3D PINGROUP(80, pcie0_clk_req_n, qup1_se7_l1_mira, _, phase_flag, _= , _, _, _, _, _, _), + [81] =3D PINGROUP(81, wcn_sw_ctrl, qup1_se7_l0_mira, dbg_out_clk, _, _, _= , _, _, _, _, _), [82] =3D PINGROUP(82, _, _, _, _, _, _, _, _, _, _, _), [83] =3D PINGROUP(83, _, _, _, _, _, _, _, _, _, _, _), [84] =3D PINGROUP(84, uim0_data, _, _, _, _, _, _, _, _, _, _), @@ -1383,10 +1479,10 @@ static const struct msm_pingroup eliza_groups[] =3D= { [94] =3D PINGROUP(94, qlink_wmss, _, _, _, _, _, _, _, _, _, _), [95] =3D PINGROUP(95, qlink_big_request, _, _, _, _, _, _, _, _, _, _), [96] =3D PINGROUP(96, qlink_big_enable, _, _, _, _, _, _, _, _, _, _), - [97] =3D PINGROUP(97, uim1_data, qspi0, qup2_se3, _, _, _, _, _, _, _, _), + [97] =3D PINGROUP(97, uim1_data, qspi0, qup2_se3_l1_mira, _, _, _, _, _, = _, _, _), [98] =3D PINGROUP(98, uim1_clk, qspi0, _, _, _, _, _, _, _, _, _), [99] =3D PINGROUP(99, uim1_reset, qspi0, _, _, _, _, _, _, _, _, _), - [100] =3D PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup= 2_se3, mdp_vsync, _, _, _, _, _), + [100] =3D PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup= 2_se3_l1_mirb, mdp_vsync, _, _, _, _, _), [101] =3D PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _), [102] =3D PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _), [103] =3D PINGROUP(103, _, _, _, _, _, _, _, _, _, _, _), @@ -1400,9 +1496,9 @@ static const struct msm_pingroup eliza_groups[] =3D { [111] =3D PINGROUP(111, coex_uart1_tx, _, _, _, _, _, _, _, _, _, _), [112] =3D PINGROUP(112, coex_uart1_rx, _, _, _, _, _, _, _, _, _, _), [113] =3D PINGROUP(113, _, nav_gpio3, _, _, _, _, _, _, _, _, _), - [114] =3D PINGROUP(114, qup1_se7, qup1_se7, _, qdss_gpio_tracedata, _, _,= _, _, _, _, _), + [114] =3D PINGROUP(114, qup1_se7, qup1_se7_l1_mirb, _, qdss_gpio_tracedat= a, _, _, _, _, _, _, _), [115] =3D PINGROUP(115, _, qspi0, cci_async_in, _, _, _, _, _, _, _, _), - [116] =3D PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3, _, _, _= , _, _, _, _), + [116] =3D PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3_l0_mirb,= _, _, _, _, _, _, _), [117] =3D PINGROUP(117, nav_gpio1, _, vfr_1, _, _, _, _, _, _, _, _), [118] =3D PINGROUP(118, nav_gpio2, _, _, _, _, _, _, _, _, _, _), [119] =3D PINGROUP(119, nav_gpio0, _, _, _, _, _, _, _, _, _, _), --=20 2.53.0 From nobody Wed Jun 17 05:27:11 2026 Received: from mail-244116.protonmail.ch (mail-244116.protonmail.ch [109.224.244.116]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C03BA3BBA00 for ; Thu, 23 Apr 2026 04:43:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.116 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776919436; cv=none; b=Th9YvH33Arq3g4HTfe0bQWet//TSnyf+OyiIKW+Y13c3Wy0+O5zYCG+D2ZgsT+tU/0yfoeFcRTFUzHdR2C/QF9NfIzRkwCREBFlwv6shnA6O7ZV2PpTQt0yfiYxcS6fYMfnhXRJKzSwWPTwwSvBmrqtihNk5HSkE8vSmcTeOgQE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776919436; c=relaxed/simple; bh=tsb3VmFovTma25ROmHyZX3mhVbxmykCkGGat9WGW/6o=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CnyRATb5lJsnfawueaqRJtle+cg3q16GrEW14fJu6gyC5XW+u23VSrQqWojtWcl0c1cfrwTS+XMRFp1RikbPcZJ6A4j7WVPSl6XSGwr9lZ3eQkKthVWSHEAJ0vNP+BTWUkenEVO5h+GRw/hRym+ztxIe/oe4R2LjhSauVb3Zexg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=NTkmatSH; arc=none smtp.client-ip=109.224.244.116 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="NTkmatSH" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1776919432; x=1777178632; bh=tsb3VmFovTma25ROmHyZX3mhVbxmykCkGGat9WGW/6o=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=NTkmatSH/yAbQN4EFXiHy7Gbq3936wvC7h13ce3+gSH0BKGqVXthyDKhKW/J/pK4k dFLBQyQ2tJZ2dsEdHNzY5GJijemJWgNMovNFN0lUu0+xSKSaDk9ZM9OaPQvFml+wXa 1cmyWT1mfl0PAUOYTNK+I+tpeGftZks30Z4NuofY71jot7/zCWkNRKvEMofhiGBwRI j6v+0/1bjIBI/oPY+KYCbOCJdZk5r+QK+r7pQH4ZKon5DytP3v3UGqezPKbU6Y2BuR H0+sKxOflXjXqK2F51QdENyDEfXzIRYSGa4WKfKd3Uu4CHwdAwZCYBaGWA90vS0IXT oy/cMRmLydvQw== Date: Thu, 23 Apr 2026 04:43:46 +0000 To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa , Konrad Dybcio From: Alexander Koskovich Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Koskovich Subject: [PATCH v3 4/4] pinctrl: qcom: eliza: Split QUP1_SE4 lanes Message-ID: <20260423-fix-eliza-pinctrl-v3-4-68b24893ae63@pm.me> In-Reply-To: <20260423-fix-eliza-pinctrl-v3-0-68b24893ae63@pm.me> References: <20260423-fix-eliza-pinctrl-v3-0-68b24893ae63@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 6fc27e899e2f21e55cca2b0cf463bea3fc3983cf Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" QUP1_SE4 shares GPIO_36 & GPIO_37 for both L0/L1 and L3/L2 so the function name cannot be the same or the alternate function cannot be selected. Split them up into individual lane functions so boards can specify. Signed-off-by: Alexander Koskovich Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio --- drivers/pinctrl/qcom/pinctrl-eliza.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pi= nctrl-eliza.c index 8f74756771b8..40e263e35b45 100644 --- a/drivers/pinctrl/qcom/pinctrl-eliza.c +++ b/drivers/pinctrl/qcom/pinctrl-eliza.c @@ -568,7 +568,10 @@ enum eliza_functions { msm_mux_qup1_se2_l3_mira, msm_mux_qup1_se2_l3_mirb, msm_mux_qup1_se3, - msm_mux_qup1_se4, + msm_mux_qup1_se4_l0, + msm_mux_qup1_se4_l1, + msm_mux_qup1_se4_l2, + msm_mux_qup1_se4_l3, msm_mux_qup1_se5, msm_mux_qup1_se6, msm_mux_qup1_se6_l1_mira, @@ -1017,8 +1020,20 @@ static const char *const qup1_se3_groups[] =3D { "gpio44", "gpio45", "gpio46", "gpio47", }; =20 -static const char *const qup1_se4_groups[] =3D { - "gpio36", "gpio37", "gpio37", "gpio36", +static const char *const qup1_se4_l0_groups[] =3D { + "gpio36", +}; + +static const char *const qup1_se4_l1_groups[] =3D { + "gpio37", +}; + +static const char *const qup1_se4_l2_groups[] =3D { + "gpio37", +}; + +static const char *const qup1_se4_l3_groups[] =3D { + "gpio36", }; =20 static const char *const qup1_se5_groups[] =3D { @@ -1321,7 +1336,10 @@ static const struct pinfunction eliza_functions[] = =3D { MSM_PIN_FUNCTION(qup1_se2_l3_mira), MSM_PIN_FUNCTION(qup1_se2_l3_mirb), MSM_PIN_FUNCTION(qup1_se3), - MSM_PIN_FUNCTION(qup1_se4), + MSM_PIN_FUNCTION(qup1_se4_l0), + MSM_PIN_FUNCTION(qup1_se4_l1), + MSM_PIN_FUNCTION(qup1_se4_l2), + MSM_PIN_FUNCTION(qup1_se4_l3), MSM_PIN_FUNCTION(qup1_se5), MSM_PIN_FUNCTION(qup1_se6), MSM_PIN_FUNCTION(qup1_se6_l1_mira), @@ -1418,8 +1436,8 @@ static const struct msm_pingroup eliza_groups[] =3D { [33] =3D PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _,= _, _, _, _), [34] =3D PINGROUP(34, qup1_se1, qup1_se5, tb_trig_sdc1, ddr_bist_start, q= dss_gpio_tracedata, _, _, _, _, _, _), [35] =3D PINGROUP(35, qup1_se1, qup1_se5, tb_trig_sdc2, gcc_gp2, qdss_gpi= o_tracedata, _, _, _, _, _, _), - [36] =3D PINGROUP(36, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _= ), - [37] =3D PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _= ), + [36] =3D PINGROUP(36, qup1_se4_l0, qup1_se4_l3, ibi_i3c, _, _, _, _, _, _= , _, _), + [37] =3D PINGROUP(37, qup1_se4_l1, qup1_se4_l2, ibi_i3c, _, _, _, _, _, _= , _, _), [38] =3D PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _), [39] =3D PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _), [40] =3D PINGROUP(40, qup1_se6, qup1_se2, qup1_se6_l3_mira, _, qdss_gpio_= tracedata, gnss_adc1, ddr_pxi1, _, _, _, _), --=20 2.53.0