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charset="utf-8" Document ZT trace bus and ZTR trace clock on the R-Mobile A1. These clock supply the coresight tracing modules, PTM, TPIU, ETB and replicator. Without these clock, the coresight tracing can not be operated. While this does change the ABI, it does so by extending the existing clock-output-names, therefore if an old software is used with new DT, the coresight tracing parts will likely fail to probe, otherwise if new software is used with an old DT, there is no impact. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven --- Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Magnus Damm Cc: Michael Turquette Cc: Rob Herring Cc: Stephen Boyd Cc: devicetree@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: Reorder new clock at the end to match bindings V3: - Clarify why this change has to be done and its impact - Include include/dt-bindings/clock/r8a7740-clock.h change here - Add RB from Krzysztof --- .../devicetree/bindings/clock/renesas,cpg-clocks.yaml | 6 ++++-- include/dt-bindings/clock/r8a7740-clock.h | 2 ++ 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yam= l b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml index a0e09b7002f07..925ed35d6658a 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml @@ -41,7 +41,7 @@ properties: =20 clock-output-names: minItems: 3 - maxItems: 17 + maxItems: 19 =20 renesas,mode: description: Board-specific settings of the MD_CK* bits on R-Mobile A1 @@ -123,6 +123,8 @@ allOf: - const: zb - const: m3 - const: cp + - const: ztr + - const: zt =20 required: - renesas,mode @@ -240,6 +242,6 @@ examples: #clock-cells =3D <1>; clock-output-names =3D "system", "pllc0", "pllc1", "pllc2", "r= ", "usb24s", "i", "zg", "b", "m1", "hp", "hp= p", - "usbp", "s", "zb", "m3", "cp"; + "usbp", "s", "zb", "m3", "cp", "ztr", "zt= "; renesas,mode =3D <0x05>; }; diff --git a/include/dt-bindings/clock/r8a7740-clock.h b/include/dt-binding= s/clock/r8a7740-clock.h index 1b3fdb39cc426..8a8816b2ff6ac 100644 --- a/include/dt-bindings/clock/r8a7740-clock.h +++ b/include/dt-bindings/clock/r8a7740-clock.h @@ -24,6 +24,8 @@ #define R8A7740_CLK_ZB 14 #define R8A7740_CLK_M3 15 #define R8A7740_CLK_CP 16 +#define R8A7740_CLK_ZTR 17 +#define R8A7740_CLK_ZT 18 =20 /* MSTP1 */ #define R8A7740_CLK_CEU21 28 --=20 2.53.0 From nobody Sat Jun 13 11:26:23 2026 Received: from mout-p-201.mailbox.org (mout-p-201.mailbox.org [80.241.56.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EED9B3A4F27; Wed, 22 Apr 2026 23:38:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Implement ZT trace bus and ZTR trace clock on the R-Mobile A1. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven --- Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Magnus Damm Cc: Michael Turquette Cc: Rob Herring Cc: Stephen Boyd Cc: devicetree@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: No change V3: No change --- drivers/clk/renesas/clk-r8a7740.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/clk/renesas/clk-r8a7740.c b/drivers/clk/renesas/clk-r8= a7740.c index 635d59ead499e..31a79674583e8 100644 --- a/drivers/clk/renesas/clk-r8a7740.c +++ b/drivers/clk/renesas/clk-r8a7740.c @@ -37,6 +37,8 @@ static struct div4_clk div4_clks[] =3D { { "zg", CPG_FRQCRA, 16 }, { "b", CPG_FRQCRA, 8 }, { "m1", CPG_FRQCRA, 4 }, + { "ztr", CPG_FRQCRB, 20 }, + { "zt", CPG_FRQCRB, 16 }, { "hp", CPG_FRQCRB, 4 }, { "hpp", CPG_FRQCRC, 20 }, { "usbp", CPG_FRQCRC, 16 }, --=20 2.53.0 From nobody Sat Jun 13 11:26:23 2026 Received: from mout-p-102.mailbox.org (mout-p-102.mailbox.org [80.241.56.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79F313A640A; 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s=mail20150812; t=1776901082; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9eeYPRnU/QJypIfdTFPZeqTjC4sJbxZIBwyOo8+Te6Y=; b=bmm+Ru7o6N9v2YAgW/gLt34gDgdnEgVgZRQXXvx3CGl6yQzlg1+nqIWd1IepZuGyMD8yQ6 UHVb4aCn1IuCO7sx+Pmyqai29SwFwa75Fwl2zkuDprtowlPqQzCmCqoIjp8TzmR+5Ncg8H Qc93NIYHJ+OsYIJy5xp55eMVTMUPQVeCisvCU0Xy/yMl+MNf48SWXgeb5mjwuQ3u10leCW 8EB/Aiw5YvtzGYxxnQxUnpGjzbpqx5Th8WvtwVNJmlfpgKBTJlFMGJ78kSR4gGWGYRXtRD /T598fJ7BndTlftPbLYjlJfV1nQXZ2QC/X80hrt06r0AFbAGHzlemRZbXhWXKw== To: linux-arm-kernel@lists.infradead.org Cc: Marek Vasut , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Magnus Damm , Michael Turquette , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v3 3/4] ARM: dts: renesas: r8a7740: Add ZT/ZTR trace clock on R-Mobile A1 Date: Thu, 23 Apr 2026 01:36:29 +0200 Message-ID: <20260422233744.149872-4-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260422233744.149872-1-marek.vasut+renesas@mailbox.org> References: <20260422233744.149872-1-marek.vasut+renesas@mailbox.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MBO-RS-ID: 426a47f61ea95f5de91 X-MBO-RS-META: eruduow9rsrqtoaz9dnudiniyi1rdh81 X-Rspamd-Queue-Id: 4g1Fyg5d2Hz9v66 Content-Type: text/plain; charset="utf-8" Add ZT trace bus and ZTR trace clock on the R-Mobile A1. These clock supply the coresight tracing modules, PTM, TPIU, ETB and replicator. Without these clock, the coresight tracing can not be operated. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven --- Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Magnus Damm Cc: Michael Turquette Cc: Rob Herring Cc: Stephen Boyd Cc: devicetree@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: Add ztr/zt clock at the end of the list to match bindings V3: Keep only the trace clock DT part here, extend the commit message. --- arch/arm/boot/dts/renesas/r8a7740.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/ren= esas/r8a7740.dtsi index d13ab86c3ab47..f7136db7a2eae 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -553,7 +553,7 @@ cpg_clocks: cpg_clocks@e6150000 { "usb24s", "i", "zg", "b", "m1", "hp", "hpp", "usbp", "s", "zb", "m3", - "cp"; + "cp", "ztr", "zt"; }; =20 /* Variable factor clocks (DIV6) */ --=20 2.53.0 From nobody Sat Jun 13 11:26:23 2026 Received: from mout-p-102.mailbox.org (mout-p-102.mailbox.org [80.241.56.152]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 51B7933B6E3; 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charset="utf-8" Describe coresight topology on R-Mobile A1. Extend the current PTM node with connection funnel, TPIU, ETB and replicator. The coresight on this hardware is clocked from the ZT/ZTR trace clock. Signed-off-by: Marek Vasut Reviewed-by: Geert Uytterhoeven --- Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Magnus Damm Cc: Michael Turquette Cc: Rob Herring Cc: Stephen Boyd Cc: devicetree@vger.kernel.org Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: No change V3: No change --- arch/arm/boot/dts/renesas/r8a7740.dtsi | 114 ++++++++++++++++++++++++- 1 file changed, 111 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/renesas/r8a7740.dtsi b/arch/arm/boot/dts/ren= esas/r8a7740.dtsi index f7136db7a2eae..c7056b96ec0b7 100644 --- a/arch/arm/boot/dts/renesas/r8a7740.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7740.dtsi @@ -18,7 +18,7 @@ / { cpus { #address-cells =3D <1>; #size-cells =3D <0>; - cpu@0 { + cpu0: cpu@0 { compatible =3D "arm,cortex-a9"; device_type =3D "cpu"; reg =3D <0x0>; @@ -59,9 +59,117 @@ pmu { interrupts =3D ; }; =20 - ptm { - compatible =3D "arm,coresight-etm3x"; + replicator { + compatible =3D "arm,coresight-static-replicator"; + clocks =3D <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names =3D "atclk"; power-domains =3D <&pd_d4>; + + out-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* replicator output ports */ + port@0 { + reg =3D <0>; + + replicator_out_port0: endpoint { + remote-endpoint =3D <&tpiu_in_port>; + }; + }; + port@1 { + reg =3D <1>; + + replicator_out_port1: endpoint { + remote-endpoint =3D <&etb_in_port>; + }; + }; + }; + + in-ports { + /* replicator input port */ + port { + replicator_in_port0: endpoint { + remote-endpoint =3D <&funnel_out_port>; + }; + }; + }; + }; + + etb@e6fa1000 { + compatible =3D "arm,coresight-etb10", "arm,primecell"; + reg =3D <0xe6fa1000 0x1000>; + clocks =3D <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names =3D "apb_pclk", "atclk"; + power-domains =3D <&pd_d4>; + + in-ports { + port { + etb_in_port: endpoint { + remote-endpoint =3D <&replicator_out_port1>; + }; + }; + }; + }; + + tpiu@e6fa3000 { + compatible =3D "arm,coresight-tpiu", "arm,primecell"; + reg =3D <0xe6fa3000 0x1000>; + clocks =3D <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names =3D "apb_pclk", "atclk"; + power-domains =3D <&pd_d4>; + + in-ports { + port { + tpiu_in_port: endpoint { + remote-endpoint =3D <&replicator_out_port0>; + }; + }; + }; + }; + + funnel { + compatible =3D "arm,coresight-static-funnel"; + + /* funnel output ports */ + out-ports { + port { + funnel_out_port: endpoint { + remote-endpoint =3D + <&replicator_in_port0>; + }; + }; + }; + + in-ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* funnel input ports */ + port@0 { + reg =3D <0>; + funnel0_in_port0: endpoint { + remote-endpoint =3D <&ptm0_out_port>; + }; + }; + }; + }; + + ptm@e6fbc000 { + compatible =3D "arm,coresight-etm3x", "arm,primecell"; + reg =3D <0xe6fbc000 0x1000>; + clocks =3D <&cpg_clocks R8A7740_CLK_ZT>, <&cpg_clocks R8A7740_CLK_ZTR>; + clock-names =3D "apb_pclk", "atclk"; + cpu =3D <&cpu0>; + power-domains =3D <&pd_d4>; + + out-ports { + port { + ptm0_out_port: endpoint { + remote-endpoint =3D <&funnel0_in_port0>; + }; + }; + }; }; =20 ceu0: ceu@fe910000 { --=20 2.53.0