From nobody Wed Jun 17 03:58:18 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA5BF331203; Wed, 22 Apr 2026 15:16:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776871010; cv=none; b=SCx7l7gf4aEL68VQ3kNkzVCWncXtq6tf20awMNsiKbiI85oY0ST373K5AC/MGcRyv2wsVr148JFp2Ie8YkIq3hHaAyNrYa/BCxTErqyNbUWTjqM342vANYszZFph+jzjsi+/+O5cZJfpX/ynJylzee/KiyZcaVoDWv1KN626F0I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776871010; c=relaxed/simple; bh=R196vWAOeo6tRa5XEJu+I4cYcDIP/RZH8NMiXgF4e4s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=p4zikEsUa6PgC2Eq9Vw1JGtKieG64//+SVvvtVJll7S1N1WmOt/UXPz4MLtvwCLY7a3X/tTZZQAlumwySMyLIWbiUf4jmGaZpC6QI9JZFpbqWKokiXM0Hg0lFukI4vfR3XsbgxdBu/7qoUrH0TVJ3z4vlXOsVUGooRuonq+wnJc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SIR/lsQo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SIR/lsQo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 927B9C2BCAF; Wed, 22 Apr 2026 15:16:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776871010; bh=R196vWAOeo6tRa5XEJu+I4cYcDIP/RZH8NMiXgF4e4s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SIR/lsQoiGxyYSlZlAuZs2lEeDBOitzYWdtnDpJ7jNNFOWh+p49KXF4Tkd9V6ScdC 3xMszvAdxZbZclpJ7VvdJki0J+NlJ9FyzpsrlRJCCiPBtDtezuVb876VHA/oOiQZUG 3DDu5Y0f77o9KzMbb1IiQWHkzm52MphFUHzaph7qdSK+WQNJYCKFUz819s/KrkvDP4 7hcS9GOw/5bgoUVRUwSHapEBg29lljkCRKTjCeesjtokIwhZknb07r759T/MkcVCN3 VfXkke6vOqVL4zbFkMNok3EE6YEUQZQtB7+SMh85abOVqOT5RbQFb3Mf4XkDP+U2lt V6ZdUMHym+h4A== From: Conor Dooley To: broonie@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Cyril Jean , Valentina.FernandezAlanis@microchip.com, linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH v1 1/5] spi: microchip-core-qspi: control built-in cs manually Date: Wed, 22 Apr 2026 16:15:42 +0100 Message-ID: <20260422-yarn-trifle-dae39766fc7c@spud> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260422-foe-strength-a5d8ad650ef4@spud> References: <20260422-foe-strength-a5d8ad650ef4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6872; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=yx7bSPCVW2AoaBkEPEUBQB8MXgtwa7rod5q+DgN49ZM=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkvntlrWLq8ZJn20CA3OOi+6Vq+ZSIV7wMDV+/8HKUrw cDz6E5IRykLgxgXg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACYiy8LI8F2G+Zj7nqiIls3e EQxhzrccNwY+v7L2+lrTn/55909pLWf477x61f1z63RX3/j3fpfRgbD3KtKfXyxPmWXIUXOMcaI xHy8A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The coreQSPI IP supports only a single chip select, which is automagically operated by the hardware - set low when the transmit buffer first gets written to and set high when the number of bytes written to the TOTALBYTES field of the FRAMES register have been sent on the bus. Additional devices must use GPIOs for their chip selects. It was reported to me that if there are two devices attached to this QSPI controller that the in-built chip select is set low while linux tries to access the device attached to the GPIO. This went undetected as the boards that connected multiple devices to the SPI controller all exclusively used GPIOs for chip selects, not relying on the built-in chip select at all. It turns out that this was because the built-in chip select, when controlled automagically, is set low when active and high when inactive, thereby ruling out its use for active-high devices or devices that need to transmit with the chip select disabled. Modify the driver so that it controls chip select directly, retaining the behaviour for mem_ops of setting the chip select active for the entire duration of the transfer in the exec_op callback. For regular transfers, implement the set_cs callback for the core to use. As part of this, the existing setup callback, mchp_coreqspi_setup_op(), is removed. Modifying the CLKIDLE field is not safe to do during operation when there are multiple devices, so this code is removed entirely. Setting the MASTER and ENABLE fields is something that can be done once at probe, it doesn't need to be re-run for each device. Instead the new setup callback sets the built-in chip select to its inactive state for active-low devices, as the reset value of the chip select in software controlled mode is low. Fixes: 8f9cf02c88528 ("spi: microchip-core-qspi: Add regular transfers") Fixes: 8596124c4c1bc ("spi: microchip-core-qspi: Add support for microchip = fpga qspi controllers") CC: stable@vger.kernel.org Signed-off-by: Conor Dooley --- drivers/spi/spi-microchip-core-qspi.c | 82 ++++++++++++++++++++++----- 1 file changed, 67 insertions(+), 15 deletions(-) diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microc= hip-core-qspi.c index aafe6cbf2aea7..0a161727706ef 100644 --- a/drivers/spi/spi-microchip-core-qspi.c +++ b/drivers/spi/spi-microchip-core-qspi.c @@ -74,6 +74,13 @@ #define STATUS_FLAGSX4 BIT(8) #define STATUS_MASK GENMASK(8, 0) =20 +/* + * QSPI Direct Access register defines + */ +#define DIRECT_ACCESS_EN_SSEL BIT(0) +#define DIRECT_ACCESS_OP_SSEL BIT(1) +#define DIRECT_ACCESS_OP_SSEL_SHIFT 1 + #define BYTESUPPER_MASK GENMASK(31, 16) #define BYTESLOWER_MASK GENMASK(15, 0) =20 @@ -158,6 +165,41 @@ static int mchp_coreqspi_set_mode(struct mchp_coreqspi= *qspi, const struct spi_m return 0; } =20 +static void mchp_coreqspi_set_cs(struct spi_device *spi, bool enable) +{ + struct mchp_coreqspi *qspi =3D spi_controller_get_devdata(spi->controller= ); + u32 val; + + val =3D readl(qspi->regs + REG_DIRECT_ACCESS); + + val &=3D ~BIT(1); + if (spi->mode & SPI_CS_HIGH) + val |=3D enable << DIRECT_ACCESS_OP_SSEL_SHIFT; + else + val |=3D !enable << DIRECT_ACCESS_OP_SSEL_SHIFT; + + writel(val, qspi->regs + REG_DIRECT_ACCESS); +} + +static int mchp_coreqspi_setup(struct spi_device *spi) +{ + struct mchp_coreqspi *qspi =3D spi_controller_get_devdata(spi->controller= ); + u32 val; + + /* + * Active low devices need to be specifically set to their inactive + * states during probe. + */ + if (spi->mode & SPI_CS_HIGH) + return 0; + + val =3D readl(qspi->regs + REG_DIRECT_ACCESS); + val |=3D DIRECT_ACCESS_OP_SSEL; + writel(val, qspi->regs + REG_DIRECT_ACCESS); + + return 0; +} + static inline void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi) { u32 control, data; @@ -380,19 +422,6 @@ static int mchp_coreqspi_setup_clock(struct mchp_coreq= spi *qspi, struct spi_devi return 0; } =20 -static int mchp_coreqspi_setup_op(struct spi_device *spi_dev) -{ - struct spi_controller *ctlr =3D spi_dev->controller; - struct mchp_coreqspi *qspi =3D spi_controller_get_devdata(ctlr); - u32 control =3D readl_relaxed(qspi->regs + REG_CONTROL); - - control |=3D (CONTROL_MASTER | CONTROL_ENABLE); - control &=3D ~CONTROL_CLKIDLE; - writel_relaxed(control, qspi->regs + REG_CONTROL); - - return 0; -} - static inline void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, con= st struct spi_mem_op *op) { u32 idle_cycles =3D 0; @@ -483,6 +512,7 @@ static int mchp_coreqspi_exec_op(struct spi_mem *mem, c= onst struct spi_mem_op *o =20 reinit_completion(&qspi->data_completion); mchp_coreqspi_config_op(qspi, op); + mchp_coreqspi_set_cs(mem->spi, true); if (op->cmd.opcode) { qspi->txbuf =3D &opcode; qspi->rxbuf =3D NULL; @@ -523,6 +553,7 @@ static int mchp_coreqspi_exec_op(struct spi_mem *mem, c= onst struct spi_mem_op *o err =3D -ETIMEDOUT; =20 error: + mchp_coreqspi_set_cs(mem->spi, false); mutex_unlock(&qspi->op_lock); mchp_coreqspi_disable_ints(qspi); =20 @@ -686,6 +717,7 @@ static int mchp_coreqspi_probe(struct platform_device *= pdev) struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; int ret; + u32 num_cs, val; =20 ctlr =3D devm_spi_alloc_host(&pdev->dev, sizeof(*qspi)); if (!ctlr) @@ -718,10 +750,18 @@ static int mchp_coreqspi_probe(struct platform_device= *pdev) return ret; } =20 + /* + * The IP core only has a single CS, any more have to be provided via + * gpios + */ + if (of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs)) + num_cs =3D 1; + + ctlr->num_chipselect =3D num_cs; + ctlr->bits_per_word_mask =3D SPI_BPW_MASK(8); ctlr->mem_ops =3D &mchp_coreqspi_mem_ops; ctlr->mem_caps =3D &mchp_coreqspi_mem_caps; - ctlr->setup =3D mchp_coreqspi_setup_op; ctlr->mode_bits =3D SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_DUAL | SPI_TX_QUAD; ctlr->dev.of_node =3D np; @@ -729,9 +769,21 @@ static int mchp_coreqspi_probe(struct platform_device = *pdev) ctlr->prepare_message =3D mchp_coreqspi_prepare_message; ctlr->unprepare_message =3D mchp_coreqspi_unprepare_message; ctlr->transfer_one =3D mchp_coreqspi_transfer_one; - ctlr->num_chipselect =3D 2; + ctlr->setup =3D mchp_coreqspi_setup; + ctlr->set_cs =3D mchp_coreqspi_set_cs; ctlr->use_gpio_descriptors =3D true; =20 + val =3D readl_relaxed(qspi->regs + REG_CONTROL); + val |=3D (CONTROL_MASTER | CONTROL_ENABLE); + writel_relaxed(val, qspi->regs + REG_CONTROL); + + /* + * Put cs into software controlled mode + */ + val =3D readl_relaxed(qspi->regs + REG_DIRECT_ACCESS); + val |=3D DIRECT_ACCESS_EN_SSEL; + writel(val, qspi->regs + REG_DIRECT_ACCESS); + ret =3D devm_spi_register_controller(&pdev->dev, ctlr); if (ret) return dev_err_probe(&pdev->dev, ret, --=20 2.53.0 From nobody Wed Jun 17 03:58:18 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4361833B97F; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NLoKQAUN" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EC670C2BCB2; Wed, 22 Apr 2026 15:16:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776871012; bh=eAMN+EEHmLUF2Ne3S/DRJKeFMCv8/8xTGSnTG+9H6Y0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NLoKQAUNEDVOWOLeP3sSex+01SudFGa+UTqIE9rIa7M8TBAG3m+I7q6Cgp44YXJfo BcT/IkDfdjs8vKvjVw/2VXjyyblnyGkuqdjjlZBTB2FUF/vXWV6Krf5BvfsQQr2dtp 9yV6hJaMI179tzFC4lD7UlJCpcl1Ik4GlBDlbu5Wk/vJCY1fClGTplNCyeUKQalH7G sZB0slFrZ3RFHc/yJzvF4tGY8S/WPcCjtJItsZPUH7H/NJbVGpyYR7NGUT8Kt6yBIv f0GjYc4dc0/8mObQIySIyUzQYEpOgV62OBOP8ykqqPlU8wDi3f1AFfmqFJjAwXGHjz BJOE/1bOfNuZg== From: Conor Dooley To: broonie@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Cyril Jean , Valentina.FernandezAlanis@microchip.com, linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH v1 2/5] spi: microchip-core-qspi: don't attempt to transmit during emulated read-only dual/quad operations Date: Wed, 22 Apr 2026 16:15:43 +0100 Message-ID: <20260422-omit-fancy-ad0bac3d843d@spud> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260422-foe-strength-a5d8ad650ef4@spud> References: <20260422-foe-strength-a5d8ad650ef4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1832; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=xzvGmGWw+PhfUIzGLyaHBy7UzwyYroknqKzAQ1SA4Gk=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkvnjnkbtgnEVX0Lm6hElPZdbZlGWI3dm4vMVvLV/nQg Xduy+b6jlIWBjEuBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzkSTMjw/e7M7dd+3v5O3ul VYhq4rsMVwO3c6L2ItP+mRsVHeoUu83wP2naXAO1yU8WGHOu0pJQN+pzvzpvj++k2M7z/S3LDu+ 4zQ0A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley The core will deal with reads by creating clock cycles itself, there's no need to generate clock cycles by transmitting garbage data at the driver level. Further, transmitting garbage data just bricks the transfer since QSPI doesn't have a dedicated master-out line like MOSI in regular SPI. I'm not entirely sure if the transfer is bricked because of the garbage data being transmitted on the bus or because the core loses track of whether it is supposed to be sending or receiving data. Fixes: 8f9cf02c88528 ("spi: microchip-core-qspi: Add regular transfers") CC: stable@vger.kernel.org Signed-off-by: Conor Dooley --- drivers/spi/spi-microchip-core-qspi.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microc= hip-core-qspi.c index 0a161727706ef..d39b04f9b6b38 100644 --- a/drivers/spi/spi-microchip-core-qspi.c +++ b/drivers/spi/spi-microchip-core-qspi.c @@ -693,18 +693,28 @@ static int mchp_coreqspi_transfer_one(struct spi_cont= roller *ctlr, struct spi_de struct spi_transfer *t) { struct mchp_coreqspi *qspi =3D spi_controller_get_devdata(ctlr); + bool dual_quad =3D false; =20 qspi->tx_len =3D t->len; =20 + if (t->tx_nbits =3D=3D SPI_NBITS_QUAD || t->rx_nbits =3D=3D SPI_NBITS_QUA= D || + t->tx_nbits =3D=3D SPI_NBITS_DUAL || + t->rx_nbits =3D=3D SPI_NBITS_DUAL) + dual_quad =3D true; + if (t->tx_buf) qspi->txbuf =3D (u8 *)t->tx_buf; =20 if (!t->rx_buf) { mchp_coreqspi_write_op(qspi); - } else { + } else if (!dual_quad) { qspi->rxbuf =3D (u8 *)t->rx_buf; qspi->rx_len =3D t->len; mchp_coreqspi_write_read_op(qspi); + } else { + qspi->rxbuf =3D (u8 *)t->rx_buf; + qspi->rx_len =3D t->len; + mchp_coreqspi_read_op(qspi); } =20 return 0; --=20 2.53.0 From nobody Wed Jun 17 03:58:18 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67CAB344044; Wed, 22 Apr 2026 15:16:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776871015; cv=none; b=DetidD++QJTikqhOz+NsJsrNAEWOW0Z+t5Vn89RqhXgxx9FSPuO5188IKyai7vCOkIwTAfEGhOqtGwEOZ8XwPNlFiVDKwdNnjnLDycp/0f0BnreSC3FWmpX8tcJY5eYM8bfQCL5k2bFPDKWoYVXhpCnfItUKe0y8TrWGAVDc6L4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776871015; c=relaxed/simple; bh=mm7l28cn3pCYCLf3GVDEBAVzraqXFwXdDi0avE3W0Dg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EeBA2wtR0DorNUwJ4DBa6o1QNxVyFWiuEiAmWyip7SGqNmIOJvc+NKGFhsCZVlo/X4OgyRxdtg2Sx4zHSMYamz58tWoHUvCe29IWL2UT7DlpR+/e9ud+FzlYr7b+GDQSMrC6+x76Y/9juVYnPb62EUMcDDMQ98qpJGkbLwe5igY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cPRCAYl3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cPRCAYl3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 52B76C2BCAF; Wed, 22 Apr 2026 15:16:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776871015; bh=mm7l28cn3pCYCLf3GVDEBAVzraqXFwXdDi0avE3W0Dg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cPRCAYl3IEqxaXl+anejQi2GVfTs7FdWGaN7t3FXMVHbrX2wFpQXNewX0NF0e3OEu 4lNSuPHaeGt2yObFfzopY93ZcGC1V3s+fNn4d824Si9heoiQpNL3pFVu5z8lUMyXSd YsxqPUmOaU0rqv/1IVxaI4QUVlWnapMuNtsq8kXPC0dZnOBfTf2UEYl5Ik0aehYjSK Wzool//GKVKzocTEcC14O0/8YzN324j3cqWblv8ljCVfy32IBR6yswG3ucUQt0aWY2 DpZNhCdBTsMSlQoFRbYxexqmJBeD0BLgdIvjDEHYYsFI6pkZt5npau92VgwxtHW3Tp nypy/fID2UciA== From: Conor Dooley To: broonie@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Cyril Jean , Valentina.FernandezAlanis@microchip.com, linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 3/5] spi: microchip-core-qspi: report device on which timeout occured instead of which controller Date: Wed, 22 Apr 2026 16:15:44 +0100 Message-ID: <20260422-apricot-wok-76d22d53d5fc@spud> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260422-foe-strength-a5d8ad650ef4@spud> References: <20260422-foe-strength-a5d8ad650ef4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1017; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=qRF8UGHvy5H5R9RLjT10J+zjZQsaD/qbyylMGRr28JU=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkvnjlkBj6e7DNHJePXpJb9jcvkVX8zrT5a6X1E/s+2v rd5Ey6Yd5SyMIhxMciKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAi6X6MDJM/WVmsapYtFVw6 03CF5em87baLS87O+hZz5fC3q/sPlnQy/BWbxiWu9Dxv1Z6odD0rTw3NsCVic2xvnQ+T/HvnuEr EcVYA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley When prepare_message callbacks fail, the SPI core already reports which controller the failure happened on. The corresponding code in the mem_ops portion of the driver already reports the device a timeout occurred on, so make the regular part of the driver do the same. Signed-off-by: Conor Dooley --- drivers/spi/spi-microchip-core-qspi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microc= hip-core-qspi.c index d39b04f9b6b38..629f785bd230b 100644 --- a/drivers/spi/spi-microchip-core-qspi.c +++ b/drivers/spi/spi-microchip-core-qspi.c @@ -635,7 +635,7 @@ static int mchp_coreqspi_prepare_message(struct spi_con= troller *ctlr, struct spi ret =3D mchp_coreqspi_wait_for_ready(qspi); if (ret) { mutex_unlock(&qspi->op_lock); - dev_err(&ctlr->dev, "Timeout waiting on QSPI ready.\n"); + dev_err(&m->spi->dev, "Timeout waiting on QSPI ready.\n"); return ret; } =20 --=20 2.53.0 From nobody Wed Jun 17 03:58:18 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85B23346791; Wed, 22 Apr 2026 15:16:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776871017; cv=none; b=rSGzOrcRYZx2j5hjYAIg9rfGmI08lv1VkL84+F0wHUzhc/6pIu5t8QihIKi525H74VeV9fFFdRgMgG2dC+jw4RymNPz88JQRI+z+hJBL2/8V+tTIoOHKdgAgKBEhYl3pERL7zNEPDnivURXGjpEYW4YriCD0pZ7rUSbfUZ2xbBY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776871017; c=relaxed/simple; bh=7O7XwKYDSIZRgMFfhLYwFoKq7qcfU4DTABqxZTA2LvQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=A3eWzJp96JP7ZJdn+5U0EovT36PzA9CvXGqTMTNm1WD75N8QIjfNm2GVdcbYS5LcgV9+YhZfAPRcuZoGJaJzgzUIVNR4MQEHgJi8Ks8In2L+2uGqEo0OimMO8vWuqlxgNYRvLFIxaHrA2u6ohfnuFapidiUSkpuPtjOZpeW9Xrk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GjPOdUdw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GjPOdUdw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8416BC2BCB2; Wed, 22 Apr 2026 15:16:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776871017; bh=7O7XwKYDSIZRgMFfhLYwFoKq7qcfU4DTABqxZTA2LvQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GjPOdUdwvCnIwij52v9gpXXY/g1jbWUp/bFS3g/eWT6+BqKG69ot8AIHul472r3g1 uXnaot9MGfx+6jFELAUjW/ijgQ8LwLOQEdIHlrLzGQH8nlf8QIVPOy3iJ0+Xgq8abT Aiik7a6VTbVSdKFKEqhxTwGfb0I/Sn9M5OHZm5KqloiviFr65LVQGH+3AdQAdqoVFR RqXtQ0isKey0IJkTMTbv5fETenkr7bc9zKT9m1StPfYbc6ptRXFokF6xCWlt7JchOs H5LJ/6o2xSVpx2PclQtvXuA+FHwfYHNqzb/VbVzARSnBNWb+qj+EdMYK8R+yMconQP 046Oig843ImLA== From: Conor Dooley To: broonie@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Cyril Jean , Valentina.FernandezAlanis@microchip.com, linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 4/5] spi: microchip-core-qspi: remove an unused define Date: Wed, 22 Apr 2026 16:15:45 +0100 Message-ID: <20260422-resilient-pantry-833f1d383a15@spud> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260422-foe-strength-a5d8ad650ef4@spud> References: <20260422-foe-strength-a5d8ad650ef4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=772; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=ZQeTCH4jxeGgUWZk1PzFturjJZpquzfnJzGD8RIaUkw=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkvnjkE/Drd+E5p8tU/l58nRk/mZ1x5Trd98hnlm37vd /ZVfuJd1FHKwiDGxSArpsiSeLuvRWr9H5cdzj1vYeawMoEMYeDiFICJ6H9j+O/G7/Z+v89n/sem ovXNvgGZqY3HbDknxDZrX3lrInrGtZOR4fIHU/Nnz07/0vhrn/PI/fssiZzOs0E6z7c+nsBlUzj lPTsA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley I noticed this define was incorrect, it should be UpperAddress, but in renaming it it became clear there were actually no users. Just get rid of it. Signed-off-by: Conor Dooley --- drivers/spi/spi-microchip-core-qspi.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microc= hip-core-qspi.c index 629f785bd230b..ae1c7ce09b2ed 100644 --- a/drivers/spi/spi-microchip-core-qspi.c +++ b/drivers/spi/spi-microchip-core-qspi.c @@ -99,7 +99,6 @@ #define REG_IEN (0x0c) #define REG_STATUS (0x10) #define REG_DIRECT_ACCESS (0x14) -#define REG_UPPER_ACCESS (0x18) #define REG_RX_DATA (0x40) #define REG_TX_DATA (0x44) #define REG_X4_RX_DATA (0x48) --=20 2.53.0 From nobody Wed Jun 17 03:58:18 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A460C347FCD; Wed, 22 Apr 2026 15:16:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776871019; cv=none; b=Lei3PHVSk86TelOVSJv5KV+gl5Rvyv+d90tsw59pCk5vwTh9dyMzMBI2xZx7JLZRDSWjagUa3KPZrT1y65w+MIV92fWlbRd64+NNufSTZPXboQdxH0xDcbvjilQ9I49adIzyOrcB9amK3lGvmU4/uBDe0NBYJM4QjAU+8JePQRE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776871019; c=relaxed/simple; bh=6ET/frCteaTcrEw4caKHP3nJei7aVUDYuECfByOQKZA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XuCBfdwXy8r2k78zRLV0Nf5hrAAuh4gScqRFi+JWKRpVLAivgl93EHvESMtPTk8pxupTYznJ9KY6Nru4b8/B1Az11rIMPhjRtkXlVAUA6jTrQUMBBt61ITI5p7tO4MNm84isroUEKPSfya7e8UBysFrHUgv2zcEie/CVSsydIy0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pxHwzwf6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pxHwzwf6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BEF38C2BCAF; Wed, 22 Apr 2026 15:16:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1776871019; bh=6ET/frCteaTcrEw4caKHP3nJei7aVUDYuECfByOQKZA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pxHwzwf6JqgqyvJ1OZhj+VC34Cd0D6vupBQKWuZWOX8A05KspypYTPIhtKgsaxcr4 MxI+6c92kOvrVnb0eQvDn4ktGhaLL+1u5oKzj4Pgupi6NsqgOWGTTnmxIVwdNwu3AD 1XwXpXHRV1gcse9qesHmcQXcoT+4R7/hucBCcaoDI0glxQnauNBMf4qEDklnTvvE7o Jz2phloDCSutGlSEEgTpO7pbMDz97FRKUHRW/SIAoWfwiLjbrVO9byQ3dPLgNVMvfJ VBhgZcrw0lA+IBAyrbLk4D6SCziemmknGSV8c29FB3RGa3PMbJafgFfXiisUVg/7Zj AXQJ8b/hkYYcA== From: Conor Dooley To: broonie@kernel.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Cyril Jean , Valentina.FernandezAlanis@microchip.com, linux-riscv@lists.infradead.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 5/5] spi: microchip-core-qspi: remove some inline markings Date: Wed, 22 Apr 2026 16:15:46 +0100 Message-ID: <20260422-cackle-guacamole-d51cc736a4b6@spud> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260422-foe-strength-a5d8ad650ef4@spud> References: <20260422-foe-strength-a5d8ad650ef4@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1848; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=LZMEd4rd4apGWbweXgMgaeSQ0Rz6fCOGsgSVYyBq+ps=; b=owGbwMvMwCVWscWwfUFT0iXG02pJDJkvnjkEWxX4Narxpf043SUqWr9A/tMz1z+x09nOK78v/ rh3U8bFjlIWBjEuBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzk0TmG//6VNy9+m2b/dmHu 5KTGlv2/3DZff/skZqZtYV3znC21dWWMDFetQwvKIuZrRq6sucBSWMr3/NX1dzJ5vCwH32WeWq2 4lhEA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Remove inline markings from a number of functions that are called as part of mem ops callbacks. None of them are either particularly trivial or sensitive to overhead of a function call. Just let the compiler decide what to do with them. Signed-off-by: Conor Dooley --- drivers/spi/spi-microchip-core-qspi.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-microchip-core-qspi.c b/drivers/spi/spi-microc= hip-core-qspi.c index ae1c7ce09b2ed..383d5eef7a2a2 100644 --- a/drivers/spi/spi-microchip-core-qspi.c +++ b/drivers/spi/spi-microchip-core-qspi.c @@ -199,7 +199,7 @@ static int mchp_coreqspi_setup(struct spi_device *spi) return 0; } =20 -static inline void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi) +static void mchp_coreqspi_read_op(struct mchp_coreqspi *qspi) { u32 control, data; =20 @@ -235,7 +235,7 @@ static inline void mchp_coreqspi_read_op(struct mchp_co= reqspi *qspi) } } =20 -static inline void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi) +static void mchp_coreqspi_write_op(struct mchp_coreqspi *qspi) { u32 control, data; =20 @@ -263,7 +263,7 @@ static inline void mchp_coreqspi_write_op(struct mchp_c= oreqspi *qspi) } } =20 -static inline void mchp_coreqspi_write_read_op(struct mchp_coreqspi *qspi) +static void mchp_coreqspi_write_read_op(struct mchp_coreqspi *qspi) { u32 control, data; =20 @@ -421,7 +421,7 @@ static int mchp_coreqspi_setup_clock(struct mchp_coreqs= pi *qspi, struct spi_devi return 0; } =20 -static inline void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, con= st struct spi_mem_op *op) +static void mchp_coreqspi_config_op(struct mchp_coreqspi *qspi, const stru= ct spi_mem_op *op) { u32 idle_cycles =3D 0; int total_bytes, cmd_bytes, frames, ctrl; --=20 2.53.0