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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8ef12122800sm237379985a.18.2026.04.21.23.02.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2026 23:02:13 -0700 (PDT) From: Yongxing Mou Date: Wed, 22 Apr 2026 14:01:51 +0800 Subject: [PATCH v4 1/5] phy: qcom: edp: Unify generic DP/eDP swing and pre-emphasis tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260422-edp_phy-v4-1-c38bef2d027b@oss.qualcomm.com> References: <20260422-edp_phy-v4-0-c38bef2d027b@oss.qualcomm.com> In-Reply-To: <20260422-edp_phy-v4-0-c38bef2d027b@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Stephen Boyd , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Yongxing Mou , stable@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776837726; l=3913; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=ZvT7qgSFLpdex2Ylpf+73VTMqkc/s9oyjE//rNwO4D8=; b=gmbKCn9+ZdWurqtMj/95xmyfSF3k0EhnlaeEItcktX7otzcmwJAqLGkk5szavKagMO9Q0Kq9k fDdOFSiOC2lBtRwaMk6qCTwzBLqw6pi17aLJm8Go1fAY2RYMJPBz5Pd X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Authority-Analysis: v=2.4 cv=OdioyBTY c=1 sm=1 tr=0 ts=69e86467 cx=c_pps a=qKBjSQ1v91RyAK45QCPf5w==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=_hJh01-1qFuxGScrDK8A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=NFOGd7dJGGMPyQGDc5-O:22 X-Proofpoint-ORIG-GUID: 6zQUjasSIXhTWY3iZefkBF2EyIdwbJVh X-Proofpoint-GUID: 6zQUjasSIXhTWY3iZefkBF2EyIdwbJVh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIyMDA1NiBTYWx0ZWRfX6Z/z3JPnYLJI Tc4o5TiMJU2tSrW44qs5rfAwmHWEtPGyK8Se75n9gRxzkVK09ukPrG1MBHA45lfyI32ODgJmWzQ CBeImYyMxdyjdn1FcbBILuWZJfzbqg9fGQDxQQmxw+3q4waExX29f2D5OvMVOn3ByHoGp0f2VPJ K2BnaH7ewenkPCnaml527F9O8pl8HCm0zNhVsfGVTeiOyMSikYolJafWzrMNxWM2zLNF+N5btdd vQMrN6ccyf5vmpv36BdDbzK9oPzXBNVa+8vx32O4IUUHT7bFnP1qwb0MsY9Dcc1C3pJTm+QK1pN w/pxiAFqzu+er/aaD7/vX/YpDRUWvlDUnjQjLL5RQbqn+hCRu+Yk/Dc1Z7tlPHKD1UP1YNxkCRj 6iyQ2piirbX1mTRudVHkOIwZ7RRdGmGoES0Za5nycXazTm7rlCuw35BPixnDl0L8sDdtC5Uncj2 n/iL+n8lPdgWYeNMfxQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-21_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 malwarescore=0 phishscore=0 adultscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604220056 The current eDP and DP swing/pre-emphasis tables do not match the HPG requirements for the supported platforms, correct the table accordingly. The generic tables which can be shared as follows: DP mode=EF=BC=9A -sa8775p/sc7280/sc8280xp/x1e80100 -glymur -sc8180x eDP mode(low vdiff): -glymur/sa8775p/sc8280xp/x1e80100 -sc7280 -sc8180x The proper tables for SC8180X and SC7280 will be added in a later patch, since they need separate table. Cc: stable@vger.kernel.org Fixes: f199223cb490 ("phy: qcom: Introduce new eDP PHY driver") Reviewed-by: Konrad Dybcio Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-edp.c | 41 +++++++++------------------------= ---- 1 file changed, 10 insertions(+), 31 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 7372de05a0b8..2af3fd63832f 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -116,17 +116,17 @@ struct qcom_edp { }; =20 static const u8 dp_swing_hbr_rbr[4][4] =3D { - { 0x08, 0x0f, 0x16, 0x1f }, + { 0x07, 0x0f, 0x16, 0x1f }, { 0x11, 0x1e, 0x1f, 0xff }, { 0x16, 0x1f, 0xff, 0xff }, { 0x1f, 0xff, 0xff, 0xff } }; =20 static const u8 dp_pre_emp_hbr_rbr[4][4] =3D { - { 0x00, 0x0d, 0x14, 0x1a }, + { 0x00, 0x0e, 0x15, 0x1a }, { 0x00, 0x0e, 0x15, 0xff }, { 0x00, 0x0e, 0xff, 0xff }, - { 0x03, 0xff, 0xff, 0xff } + { 0x04, 0xff, 0xff, 0xff } }; =20 static const u8 dp_swing_hbr2_hbr3[4][4] =3D { @@ -158,7 +158,7 @@ static const u8 edp_swing_hbr_rbr[4][4] =3D { }; =20 static const u8 edp_pre_emp_hbr_rbr[4][4] =3D { - { 0x05, 0x12, 0x17, 0x1d }, + { 0x05, 0x11, 0x17, 0x1d }, { 0x05, 0x11, 0x18, 0xff }, { 0x06, 0x11, 0xff, 0xff }, { 0x00, 0xff, 0xff, 0xff } @@ -172,10 +172,10 @@ static const u8 edp_swing_hbr2_hbr3[4][4] =3D { }; =20 static const u8 edp_pre_emp_hbr2_hbr3[4][4] =3D { - { 0x08, 0x11, 0x17, 0x1b }, - { 0x00, 0x0c, 0x13, 0xff }, - { 0x05, 0x10, 0xff, 0xff }, - { 0x00, 0xff, 0xff, 0xff } + { 0x0c, 0x15, 0x19, 0x1e }, + { 0x0b, 0x15, 0x19, 0xff }, + { 0x0e, 0x14, 0xff, 0xff }, + { 0x0d, 0xff, 0xff, 0xff } }; =20 static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= =3D { @@ -193,27 +193,6 @@ static const u8 edp_phy_vco_div_cfg_v4[4] =3D { 0x01, 0x01, 0x02, 0x00, }; =20 -static const u8 edp_pre_emp_hbr_rbr_v5[4][4] =3D { - { 0x05, 0x11, 0x17, 0x1d }, - { 0x05, 0x11, 0x18, 0xff }, - { 0x06, 0x11, 0xff, 0xff }, - { 0x00, 0xff, 0xff, 0xff } -}; - -static const u8 edp_pre_emp_hbr2_hbr3_v5[4][4] =3D { - { 0x0c, 0x15, 0x19, 0x1e }, - { 0x0b, 0x15, 0x19, 0xff }, - { 0x0e, 0x14, 0xff, 0xff }, - { 0x0d, 0xff, 0xff, 0xff } -}; - -static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= _v5 =3D { - .swing_hbr_rbr =3D &edp_swing_hbr_rbr, - .swing_hbr3_hbr2 =3D &edp_swing_hbr2_hbr3, - .pre_emphasis_hbr_rbr =3D &edp_pre_emp_hbr_rbr_v5, - .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3_v5, -}; - static const u8 edp_phy_aux_cfg_v5[DP_AUX_CFG_SIZE] =3D { 0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02, 0= x00, }; @@ -564,7 +543,7 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg= =3D { .is_edp =3D false, .aux_cfg =3D edp_phy_aux_cfg_v5, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, - .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, + .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 @@ -945,7 +924,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v8 =3D= { static struct qcom_edp_phy_cfg glymur_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v8, .vco_div_cfg =3D edp_phy_vco_div_cfg_v8, - .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v5, + .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v8, }; 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[129.46.232.65]) by smtp.gmail.com with ESMTPSA id af79cd13be357-8ef12122800sm237379985a.18.2026.04.21.23.02.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2026 23:02:17 -0700 (PDT) From: Yongxing Mou Date: Wed, 22 Apr 2026 14:01:52 +0800 Subject: [PATCH v4 2/5] phy: qcom: edp: Add eDP/DP mode switch support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260422-edp_phy-v4-2-c38bef2d027b@oss.qualcomm.com> References: <20260422-edp_phy-v4-0-c38bef2d027b@oss.qualcomm.com> In-Reply-To: <20260422-edp_phy-v4-0-c38bef2d027b@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Stephen Boyd , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Yongxing Mou , stable@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776837726; l=5695; i=yongxing.mou@oss.qualcomm.com; s=20250910; h=from:subject:message-id; bh=koMmfDgY6enq9c552pstA8QV5P3AcIvAKR/xucXdwSU=; b=4njF7bVd40+2M5r00zYKejJksd05Hb3dd9BkdXPx3lh83ZcOzqWPg2uzhEvYFLbap3kTFhUIe +gVt4TP5w3lDrqStpudtWi3+eSo02lv3JHRZZOIuLlmSfSBthRoobz2 X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=rAy5J1eP+V7OXqH5FJ7ngMCtUrnHhut30ZTldOj52UM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIyMDA1NiBTYWx0ZWRfX4V9/nNEc/zN2 f/HQNNNMSmPdXJmYoAfr7KKONbPnfDNaJURdfj4Fr/hJm/tzezmHKrzKH1ULL/EIJ/h7M90YQh0 7gYVsQXiPLhpB9tNUUSXQzVMOBzcXV6JVsCB3lAVI4+CLhkMI2D3KIeLlbIINa+09Jcb1ccRK1G bMpYcRajgrHISJaGQ355/Usje0T6J6MzeGvpSv+dHgVobuRwR7amwuKD691WzQG4mT+ny9Zl30W q8bx0CquyTrKCl8GHpswaw7bDRZxLvXx8SXODZKypW3nZXFdIAhm0zgJ/kNz2vDLgZ3NazDs51u OOXzfdDsKDT9LRspgW8p3E77MNZVJjeQ/vc+aEa/ZIhvdfZux/MISiNmvzWv4wdFQUYJH2vokS4 fk/uwAibLz+IgSX6KQmCKYEL/wwN0STjpX5xopeXfAimqmgiJOqO0RLiVlDvV2uHCeJiLWTKgqA NCIZreIwBbOqPSGwMkQ== X-Proofpoint-GUID: jdd9qfLTNun7zSTVdr9WIOjMmb5zy9rG X-Proofpoint-ORIG-GUID: jdd9qfLTNun7zSTVdr9WIOjMmb5zy9rG X-Authority-Analysis: v=2.4 cv=RoT16imK c=1 sm=1 tr=0 ts=69e8646b cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=C3Dk8TwHQYyIj7nOf9RCJw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=se8qGc9sdx2UsIF7nuMA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-21_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 adultscore=0 bulkscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604220056 The eDP PHY supports both eDP/DP modes, each requires a different table. The current driver doesn't support both modes and use either the eDP or DP table when enable the platform. Add a separate set of tables for eDP and DP modes, and select the appropriate table based on the current mode. Glymur's DP mode table differs from the other platforms, add a dedicated table for it. Since both modes are supported, so also fixes the table mismatch for X1E80100(eDP) and SA8775P(DP). Cc: stable@vger.kernel.org Fixes: 3f12bf16213c ("phy: qcom: edp: Add support for eDP PHY on SA8775P") Reviewed-by: Konrad Dybcio Signed-off-by: Yongxing Mou --- drivers/phy/qualcomm/phy-qcom-edp.c | 46 +++++++++++++++++++++++++++------= ---- 1 file changed, 34 insertions(+), 12 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 2af3fd63832f..3266026cfe37 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -87,7 +87,8 @@ struct qcom_edp_phy_cfg { bool is_edp; const u8 *aux_cfg; const u8 *vco_div_cfg; - const struct qcom_edp_swing_pre_emph_cfg *swing_pre_emph_cfg; + const struct qcom_edp_swing_pre_emph_cfg *dp_swing_pre_emph_cfg; + const struct qcom_edp_swing_pre_emph_cfg *edp_swing_pre_emph_cfg; const struct phy_ver_ops *ver_ops; }; =20 @@ -150,6 +151,20 @@ static const struct qcom_edp_swing_pre_emph_cfg dp_phy= _swing_pre_emph_cfg =3D { .pre_emphasis_hbr3_hbr2 =3D &dp_pre_emp_hbr2_hbr3, }; =20 +static const u8 dp_pre_emp_hbr_rbr_v8[4][4] =3D { + { 0x00, 0x0e, 0x15, 0x1a }, + { 0x00, 0x0e, 0x15, 0xff }, + { 0x00, 0x0e, 0xff, 0xff }, + { 0x00, 0xff, 0xff, 0xff } +}; + +static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg_= v8 =3D { + .swing_hbr_rbr =3D &dp_swing_hbr_rbr, + .swing_hbr3_hbr2 =3D &dp_swing_hbr2_hbr3, + .pre_emphasis_hbr_rbr =3D &dp_pre_emp_hbr_rbr_v8, + .pre_emphasis_hbr3_hbr2 =3D &dp_pre_emp_hbr2_hbr3, +}; + static const u8 edp_swing_hbr_rbr[4][4] =3D { { 0x07, 0x0f, 0x16, 0x1f }, { 0x0d, 0x16, 0x1e, 0xff }, @@ -246,7 +261,7 @@ static int qcom_edp_phy_init(struct phy *phy) * when more information becomes available about why this is * even needed. */ - if (edp->cfg->swing_pre_emph_cfg && !edp->is_edp) + if (edp->cfg->dp_swing_pre_emph_cfg && !edp->is_edp) aux_cfg[8] =3D 0xb7; =20 writel(0xfc, edp->edp + DP_PHY_MODE); @@ -270,7 +285,7 @@ static int qcom_edp_phy_init(struct phy *phy) =20 static int qcom_edp_set_voltages(struct qcom_edp *edp, const struct phy_co= nfigure_opts_dp *dp_opts) { - const struct qcom_edp_swing_pre_emph_cfg *cfg =3D edp->cfg->swing_pre_emp= h_cfg; + const struct qcom_edp_swing_pre_emph_cfg *cfg; unsigned int v_level =3D 0; unsigned int p_level =3D 0; u8 ldo_config; @@ -278,12 +293,14 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp= , const struct phy_configur u8 emph; int i; =20 + if (edp->is_edp) + cfg =3D edp->cfg->edp_swing_pre_emph_cfg; + else + cfg =3D edp->cfg->dp_swing_pre_emph_cfg; + if (!cfg) return 0; =20 - if (edp->is_edp) - cfg =3D &edp_phy_swing_pre_emph_cfg; - for (i =3D 0; i < dp_opts->lanes; i++) { v_level =3D max(v_level, dp_opts->voltage[i]); p_level =3D max(p_level, dp_opts->pre[i]); @@ -543,7 +560,8 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg= =3D { .is_edp =3D false, .aux_cfg =3D edp_phy_aux_cfg_v5, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, - .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 @@ -556,7 +574,8 @@ static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = =3D { static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, - .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 @@ -564,7 +583,8 @@ static const struct qcom_edp_phy_cfg sc8280xp_edp_phy_c= fg =3D { .is_edp =3D true, .aux_cfg =3D edp_phy_aux_cfg_v4, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, - .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 @@ -745,7 +765,8 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 =3D= { static struct qcom_edp_phy_cfg x1e80100_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, - .swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v6, }; =20 @@ -924,7 +945,8 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v8 =3D= { static struct qcom_edp_phy_cfg glymur_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v8, .vco_div_cfg =3D edp_phy_vco_div_cfg_v8, - .swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg_v8, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg, .ver_ops =3D &qcom_edp_phy_ops_v8, }; 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Add the corresponding tables for these platforms. Since they have different PHY sub-versions, their eDP/DP mode tables also differ, so move SC8180X to its own cfg instead of reusing the SC7280 one. Signed-off-by: Yongxing Mou --- drivers/phy/qualcomm/phy-qcom-edp.c | 71 +++++++++++++++++++++++++++++++++= +--- 1 file changed, 67 insertions(+), 4 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 3266026cfe37..7ac2f502c7a0 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -165,6 +165,27 @@ static const struct qcom_edp_swing_pre_emph_cfg dp_phy= _swing_pre_emph_cfg_v8 =3D { .pre_emphasis_hbr3_hbr2 =3D &dp_pre_emp_hbr2_hbr3, }; =20 +static const u8 dp_swing_hbr2_hbr3_v2[4][4] =3D { + { 0x27, 0x2f, 0x36, 0xff }, + { 0x31, 0x3e, 0x3f, 0xff }, + { 0x3a, 0x3f, 0xff, 0xff }, + { 0xff, 0xff, 0xff, 0xff } +}; + +static const u8 dp_pre_emp_hbr2_hbr3_v2[4][4] =3D { + { 0x20, 0x2e, 0x35, 0xff }, + { 0x20, 0x2e, 0x35, 0xff }, + { 0x20, 0x2e, 0xff, 0xff }, + { 0xff, 0xff, 0xff, 0xff } +}; + +static const struct qcom_edp_swing_pre_emph_cfg dp_phy_swing_pre_emph_cfg_= v2 =3D { + .swing_hbr_rbr =3D &dp_swing_hbr_rbr, + .swing_hbr3_hbr2 =3D &dp_swing_hbr2_hbr3_v2, + .pre_emphasis_hbr_rbr =3D &dp_pre_emp_hbr_rbr, + .pre_emphasis_hbr3_hbr2 =3D &dp_pre_emp_hbr2_hbr3_v2, +}; + static const u8 edp_swing_hbr_rbr[4][4] =3D { { 0x07, 0x0f, 0x16, 0x1f }, { 0x0d, 0x16, 0x1e, 0xff }, @@ -208,6 +229,41 @@ static const u8 edp_phy_vco_div_cfg_v4[4] =3D { 0x01, 0x01, 0x02, 0x00, }; =20 +static const u8 edp_pre_emp_hbr2_hbr3_v2[4][4] =3D { + { 0x0c, 0x15, 0x19, 0x1e }, + { 0x08, 0x15, 0x19, 0xff }, + { 0x0e, 0x14, 0xff, 0xff }, + { 0x0d, 0xff, 0xff, 0xff } +}; + +static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= _v2 =3D { + .swing_hbr_rbr =3D &edp_swing_hbr_rbr, + .swing_hbr3_hbr2 =3D &edp_swing_hbr2_hbr3, + .pre_emphasis_hbr_rbr =3D &edp_pre_emp_hbr_rbr, + .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3_v2, +}; + +static const u8 edp_swing_hbr2_hbr3_v3[4][4] =3D { + { 0x06, 0x11, 0x16, 0x1b }, + { 0x0b, 0x19, 0x1f, 0xff }, + { 0x18, 0x1f, 0xff, 0xff }, + { 0x1f, 0xff, 0xff, 0xff } +}; + +static const u8 edp_pre_emp_hbr2_hbr3_v3[4][4] =3D { + { 0x0c, 0x15, 0x19, 0x1e }, + { 0x09, 0x14, 0x19, 0xff }, + { 0x0f, 0x14, 0xff, 0xff }, + { 0x0d, 0xff, 0xff, 0xff } +}; + +static const struct qcom_edp_swing_pre_emph_cfg edp_phy_swing_pre_emph_cfg= _v3 =3D { + .swing_hbr_rbr =3D &edp_swing_hbr_rbr, + .swing_hbr3_hbr2 =3D &edp_swing_hbr2_hbr3_v3, + .pre_emphasis_hbr_rbr =3D &edp_pre_emp_hbr_rbr, + .pre_emphasis_hbr3_hbr2 =3D &edp_pre_emp_hbr2_hbr3_v3, +}; + static const u8 edp_phy_aux_cfg_v5[DP_AUX_CFG_SIZE] =3D { 0x00, 0x13, 0xa4, 0x00, 0x0a, 0x26, 0x0a, 0x03, 0x37, 0x03, 0x02, 0x02, 0= x00, }; @@ -298,9 +354,6 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, = const struct phy_configur else cfg =3D edp->cfg->dp_swing_pre_emph_cfg; =20 - if (!cfg) - return 0; - for (i =3D 0; i < dp_opts->lanes; i++) { v_level =3D max(v_level, dp_opts->voltage[i]); p_level =3D max(p_level, dp_opts->pre[i]); @@ -568,6 +621,16 @@ static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cf= g =3D { static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg =3D { .aux_cfg =3D edp_phy_aux_cfg_v4, .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v3, + .ver_ops =3D &qcom_edp_phy_ops_v4, +}; + +static const struct qcom_edp_phy_cfg sc8180x_dp_phy_cfg =3D { + .aux_cfg =3D edp_phy_aux_cfg_v4, + .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, + .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg_v2, + .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v2, .ver_ops =3D &qcom_edp_phy_ops_v4, }; =20 @@ -1348,7 +1411,7 @@ static const struct of_device_id qcom_edp_phy_match_t= able[] =3D { { .compatible =3D "qcom,glymur-dp-phy", .data =3D &glymur_phy_cfg, }, { .compatible =3D "qcom,sa8775p-edp-phy", .data =3D &sa8775p_dp_phy_cfg, = }, { .compatible =3D "qcom,sc7280-edp-phy", .data =3D &sc7280_dp_phy_cfg, }, - { .compatible =3D "qcom,sc8180x-edp-phy", .data =3D &sc7280_dp_phy_cfg, }, + { .compatible =3D "qcom,sc8180x-edp-phy", .data =3D &sc8180x_dp_phy_cfg, = }, { .compatible =3D "qcom,sc8280xp-dp-phy", .data =3D &sc8280xp_dp_phy_cfg,= }, { .compatible =3D "qcom,sc8280xp-edp-phy", .data =3D &sc8280xp_edp_phy_cf= g, }, { .compatible =3D "qcom,x1e80100-dp-phy", .data =3D &x1e80100_phy_cfg, }, --=20 2.43.0 From nobody Wed Jun 17 02:58:20 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EEA371B87C0 for ; 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All supported platforms already have the proper tables, so remove the unnecessary check. Reviewed-by: Konrad Dybcio Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-edp.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index 7ac2f502c7a0..bbd45f709a4b 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -312,12 +312,7 @@ static int qcom_edp_phy_init(struct phy *phy) DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN, edp->edp + DP_PHY_PD_CTL); =20 - /* - * TODO: Re-work the conditions around setting the cfg8 value - * when more information becomes available about why this is - * even needed. - */ - if (edp->cfg->dp_swing_pre_emph_cfg && !edp->is_edp) + if (!edp->is_edp) aux_cfg[8] =3D 0xb7; =20 writel(0xfc, edp->edp + DP_PHY_MODE); --=20 2.43.0 From nobody Wed Jun 17 02:58:20 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74FD42D77E9 for ; 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Introduce a PHY callback to program the correct LDO setting according to the HPG. Since SC7280/SC8180X uses different LDO settings from SA8775P/SC8280XP, introduce qcom_edp_phy_ops_v3 to keep the LDO setting correct. Cc: stable@vger.kernel.org Fixes: f199223cb490 ("phy: qcom: Introduce new eDP PHY driver") Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Tested-by: Konrad Dybcio # SC8280XP X13s --- drivers/phy/qualcomm/phy-qcom-edp.c | 88 ++++++++++++++++++++++++++++++++-= ---- 1 file changed, 77 insertions(+), 11 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy= -qcom-edp.c index bbd45f709a4b..3a5284522bab 100644 --- a/drivers/phy/qualcomm/phy-qcom-edp.c +++ b/drivers/phy/qualcomm/phy-qcom-edp.c @@ -81,6 +81,7 @@ struct phy_ver_ops { int (*com_clk_fwd_cfg)(const struct qcom_edp *edp); int (*com_configure_pll)(const struct qcom_edp *edp); int (*com_configure_ssc)(const struct qcom_edp *edp); + int (*com_ldo_config)(const struct qcom_edp *edp); }; =20 struct qcom_edp_phy_cfg { @@ -339,7 +340,7 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp, = const struct phy_configur const struct qcom_edp_swing_pre_emph_cfg *cfg; unsigned int v_level =3D 0; unsigned int p_level =3D 0; - u8 ldo_config; + int ret; u8 swing; u8 emph; int i; @@ -365,13 +366,13 @@ static int qcom_edp_set_voltages(struct qcom_edp *edp= , const struct phy_configur if (swing =3D=3D 0xff || emph =3D=3D 0xff) return -EINVAL; =20 - ldo_config =3D edp->is_edp ? 0x0 : 0x1; + ret =3D edp->cfg->ver_ops->com_ldo_config(edp); + if (ret) + return ret; =20 - writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); writel(swing, edp->tx0 + TXn_TX_DRV_LVL); writel(emph, edp->tx0 + TXn_TX_EMP_POST1_LVL); =20 - writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); writel(swing, edp->tx1 + TXn_TX_DRV_LVL); writel(emph, edp->tx1 + TXn_TX_EMP_POST1_LVL); =20 @@ -595,6 +596,52 @@ static int qcom_edp_com_configure_pll_v4(const struct = qcom_edp *edp) return 0; } =20 +static int qcom_edp_ldo_config_v3(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 ldo_config; + + if (!edp->is_edp) + ldo_config =3D 0x0; + else if (dp_opts->link_rate <=3D 2700) + ldo_config =3D 0x81; + else + ldo_config =3D 0x41; + + writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); + writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG); + + return 0; +} + +static int qcom_edp_ldo_config_v4(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 ldo_config; + + if (!edp->is_edp) + ldo_config =3D 0x0; + else if (dp_opts->link_rate <=3D 2700) + ldo_config =3D 0xc1; + else + ldo_config =3D 0x81; + + writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); + writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG); + + return 0; +} + +static const struct phy_ver_ops qcom_edp_phy_ops_v3 =3D { + .com_power_on =3D qcom_edp_phy_power_on_v4, + .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v4, + .com_bias_en_clkbuflr =3D qcom_edp_com_bias_en_clkbuflr_v4, + .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v4, + .com_configure_pll =3D qcom_edp_com_configure_pll_v4, + .com_configure_ssc =3D qcom_edp_com_configure_ssc_v4, + .com_ldo_config =3D qcom_edp_ldo_config_v3, +}; + static const struct phy_ver_ops qcom_edp_phy_ops_v4 =3D { .com_power_on =3D qcom_edp_phy_power_on_v4, .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v4, @@ -602,6 +649,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v4 =3D= { .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v4, .com_configure_pll =3D qcom_edp_com_configure_pll_v4, .com_configure_ssc =3D qcom_edp_com_configure_ssc_v4, + .com_ldo_config =3D qcom_edp_ldo_config_v4, }; =20 static const struct qcom_edp_phy_cfg sa8775p_dp_phy_cfg =3D { @@ -618,7 +666,7 @@ static const struct qcom_edp_phy_cfg sc7280_dp_phy_cfg = =3D { .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg, .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v3, - .ver_ops =3D &qcom_edp_phy_ops_v4, + .ver_ops =3D &qcom_edp_phy_ops_v3, }; =20 static const struct qcom_edp_phy_cfg sc8180x_dp_phy_cfg =3D { @@ -626,7 +674,7 @@ static const struct qcom_edp_phy_cfg sc8180x_dp_phy_cfg= =3D { .vco_div_cfg =3D edp_phy_vco_div_cfg_v4, .dp_swing_pre_emph_cfg =3D &dp_phy_swing_pre_emph_cfg_v2, .edp_swing_pre_emph_cfg =3D &edp_phy_swing_pre_emph_cfg_v2, - .ver_ops =3D &qcom_edp_phy_ops_v4, + .ver_ops =3D &qcom_edp_phy_ops_v3, }; =20 static const struct qcom_edp_phy_cfg sc8280xp_dp_phy_cfg =3D { @@ -811,6 +859,24 @@ static int qcom_edp_com_configure_pll_v6(const struct = qcom_edp *edp) return 0; } =20 +static int qcom_edp_ldo_config_v6(const struct qcom_edp *edp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &edp->dp_opts; + u32 ldo_config; + + if (!edp->is_edp) + ldo_config =3D 0x0; + else if (dp_opts->link_rate <=3D 2700) + ldo_config =3D 0x51; + else + ldo_config =3D 0x91; + + writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); + writel(dp_opts->lanes > 2 ? ldo_config : 0x00, edp->tx1 + TXn_LDO_CONFIG); + + return 0; +} + static const struct phy_ver_ops qcom_edp_phy_ops_v6 =3D { .com_power_on =3D qcom_edp_phy_power_on_v6, .com_resetsm_cntrl =3D qcom_edp_phy_com_resetsm_cntrl_v6, @@ -818,6 +884,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v6 =3D= { .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v4, .com_configure_pll =3D qcom_edp_com_configure_pll_v6, .com_configure_ssc =3D qcom_edp_com_configure_ssc_v6, + .com_ldo_config =3D qcom_edp_ldo_config_v6, }; =20 static struct qcom_edp_phy_cfg x1e80100_phy_cfg =3D { @@ -998,6 +1065,7 @@ static const struct phy_ver_ops qcom_edp_phy_ops_v8 = =3D { .com_clk_fwd_cfg =3D qcom_edp_com_clk_fwd_cfg_v8, .com_configure_pll =3D qcom_edp_com_configure_pll_v8, .com_configure_ssc =3D qcom_edp_com_configure_ssc_v8, + .com_ldo_config =3D qcom_edp_ldo_config_v6, }; =20 static struct qcom_edp_phy_cfg glymur_phy_cfg =3D { @@ -1013,7 +1081,6 @@ static int qcom_edp_phy_power_on(struct phy *phy) const struct qcom_edp *edp =3D phy_get_drvdata(phy); u32 bias0_en, drvr0_en, bias1_en, drvr1_en; unsigned long pixel_freq; - u8 ldo_config =3D 0x0; int ret; u32 val; u8 cfg1; @@ -1022,11 +1089,10 @@ static int qcom_edp_phy_power_on(struct phy *phy) if (ret) return ret; =20 - if (edp->cfg->edp_swing_pre_emph_cfg && !edp->is_edp) - ldo_config =3D 0x1; + ret =3D edp->cfg->ver_ops->com_ldo_config(edp); + if (ret) + return ret; =20 - writel(ldo_config, edp->tx0 + TXn_LDO_CONFIG); - writel(ldo_config, edp->tx1 + TXn_LDO_CONFIG); writel(0x00, edp->tx0 + TXn_LANE_MODE_1); writel(0x00, edp->tx1 + TXn_LANE_MODE_1); =20 --=20 2.43.0