From nobody Fri Jun 19 22:16:31 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C0692FFDE3 for ; Tue, 21 Apr 2026 17:54:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776794092; cv=none; b=YyXBHtrAGYLL4gwMaQZqnGVbmJZx4vEvjeYRNAsMa9sBPOOtb+oEFMtvGPLu3KmA0RXjCDZWS5Vv47EZ9UeEAXp/2OjfEo54WRGiepfOhZdMDbTQwjPkw7cKlz6nygmSbNhm90N2hzbwxrNejlxY/7y++KsW5Z0vSLtgyk4REVg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776794092; c=relaxed/simple; bh=7R5KiZVWPGMisYuzQJsEbYOq5Z5KTDBUHJNw2BHSXtQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ZYFYMe9ispw6CMFA92lDdW8Px+0myX51oXaR1b91BbHWi5B3FQ6BKYDoDI+26YILN7AK3bNgXFSYbPkqu2eCCWHCJxW3KwzyxFPJ6dRAdsDjwn+lyVWXkG3xeTJQg3kyhHtcyO4wifPJNZAiejhadcbh6YKhra+YZgJOu+9hXMU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=i4rfSUU7; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="i4rfSUU7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776794090; x=1808330090; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=7R5KiZVWPGMisYuzQJsEbYOq5Z5KTDBUHJNw2BHSXtQ=; b=i4rfSUU7pb9sgUWIk4s5p35iTAEzXxKRh3EKy+UIV8G1G0iQJy8NMKT4 WJXXPp4gMQAh5/EFtcu8BeNZDfSX9r7a8jWaZtC18ec1hiE0N5qzy3fn3 qehv96Ctr2yeer4OJ0WZuBd4IgOufQqhNiA1fBG1Mtp2BAcTRf6xfkhuK EHsrDzvdPU2Z4FuT5R8IvS6+1XjFrQv7uV1/BxyWVKqp7dZe9dvrBl7bn nN4ys++t/uqXIaL6eS0sZAh2ps1T8+PbBEE7F+a7fcPVc8q8ujq2pNrix 83Ylms3Ze2138P304uudLWilZ4Uh8VylpptmAq9T77tC71patfOZWdcB0 g==; X-CSE-ConnectionGUID: KblI7sfOSG6jouUSKhcFiQ== X-CSE-MsgGUID: FMQdfGV7SGukq34KXqWIow== X-IronPort-AV: E=McAfee;i="6800,10657,11763"; a="77651344" X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="77651344" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:54:50 -0700 X-CSE-ConnectionGUID: wGdh/BscRomcQnRPr+Spiw== X-CSE-MsgGUID: GlehnzN7RXWMchg1J5KLhg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="227494836" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.242]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:54:48 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 01/16] i3c: mipi-i3c-hci: Fix suspend behavior when bus disable falls back to software reset Date: Tue, 21 Apr 2026 20:54:20 +0300 Message-ID: <20260421175435.122094-2-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260421175435.122094-1-adrian.hunter@intel.com> References: <20260421175435.122094-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Software reset was introduced as a fallback if bus disable failed. The change was made in 2 places: the cleanup path and the suspend path. For the cleanup path (i3c_hci_bus_cleanup()), after software reset the function continues to do cleanup for the current I/O mode. For the suspend path (i3c_hci_rpm_suspend()), after software reset the function returns early. However software reset does not reset any Ring Headers in the Host Controller, so returning early is not the right thing to do. Instead, continue to call suspend for the current I/O mode, which for DMA mode will reset any Ring Headers. Note, although Ring Headers should not be active at this stage, performing this reset follows the procedure defined by the specification and keeps the suspend path consistent with the cleanup path. Note also, i3c_hci_sync_irq_inactive() is still called via the PIO and DMA hci->io->suspend() callbacks. Always return 0 because the device is quiesced as much as possible and returning a negative error code would unnecessarily prevent system suspend. Fixes: 9a258d1336f7 ("i3c: mipi-i3c-hci: Fallback to software reset when bu= s disable fails") Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V2: Always return 0 from suspend callback Amend commit message drivers/i3c/master/mipi-i3c-hci/core.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index b781dbed2165..afb0764b5e1f 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -762,15 +762,10 @@ static int i3c_hci_reset_and_init(struct i3c_hci *hci) int i3c_hci_rpm_suspend(struct device *dev) { struct i3c_hci *hci =3D dev_get_drvdata(dev); - int ret; =20 - ret =3D i3c_hci_bus_disable(hci); - if (ret) { - /* Fall back to software reset to disable the bus */ - ret =3D i3c_hci_software_reset(hci); - i3c_hci_sync_irq_inactive(hci); - return ret; - } + /* Fall back to software reset to disable the bus */ + if (i3c_hci_bus_disable(hci)) + i3c_hci_software_reset(hci); =20 hci->io->suspend(hci); =20 --=20 2.51.0 From nobody Fri Jun 19 22:16:31 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A884B39E176 for ; Tue, 21 Apr 2026 17:54:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776794093; cv=none; b=YH98+FZ1OtHAX1zGUmIXnSbOUzVsOR+t2CJpDYafg/FWgTjjhjsXyLkN1DwHmlHccWVqH2hFVmjIVavS0NmP9rPgzFUwtCE6yzbIV0R3uGLraew3QeDFWAMdIL2VjfbgHKSj/ecsDli5FCNr9rZpsjd1biojxL8SclA+S/SDwbk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776794093; c=relaxed/simple; bh=SjOF/6kJJSGB4kLdvP4pLaiiXGH1FK07/910HTlSe/4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=l4pfMzrrY9MjxLIw7K3deW9eEwIwyNTrJ9YoPLMoyGqip28Zn1WQ6b9CLsROW4qjVcYygx3gWAUezSyS6i51QInu4Xy9FC69i0XrUzGbGifv/52k+cfCka10rXw7cxqG5szrxa2Z3YH/9w1GU6oK5MRo5UzhbJqQlm5Tl1txLVo= ARC-Authentication-Results: i=1; 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X-CSE-ConnectionGUID: 9J53SMvmQ1SH8BSd0nyvEw== X-CSE-MsgGUID: 9cwNBzhDSdGYvUF1ZDf09g== X-IronPort-AV: E=McAfee;i="6800,10657,11763"; a="77651352" X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="77651352" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:54:51 -0700 X-CSE-ConnectionGUID: gFrRyNQxQd6myaYR/Lmn1Q== X-CSE-MsgGUID: 651dHA4iSlSrfeHmQZV8og== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="227494859" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.242]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:54:50 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 02/16] i3c: mipi-i3c-hci: Preserve RUN bit when aborting DMA ring Date: Tue, 21 Apr 2026 20:54:21 +0300 Message-ID: <20260421175435.122094-3-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260421175435.122094-1-adrian.hunter@intel.com> References: <20260421175435.122094-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MIPI I3C HCI specification does not require the DMA ring RUN bit (RUN_STOP) to be cleared when issuing an ABORT. That allows the DMA ring to continue to receive IBIs, although an IBI is anyway not lost because it can be received once the ring restarts if the I3C device has not given up. Note, currently ABORT is only used on a timeout error path so the change has very little effect in practice. In the more common case of a transfer error, the ring (bundle) operation is halted by the controller anyway. Adjust the RING_CONTROL handling to set ABORT without clearing RUN_STOP, bringing the driver into alignment with the specification. Fixes: b795e68bf3073 ("i3c: mipi-i3c-hci: Correct RING_CTRL_ABORT handling = in DMA dequeue") Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V2: Improve commit message drivers/i3c/master/mipi-i3c-hci/dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index e487ef52f6b4..4cd32e3afa7b 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -554,7 +554,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, if (ring_status & RING_STATUS_RUNNING) { /* stop the ring */ reinit_completion(&rh->op_done); - rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_ABORT); + rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); wait_for_completion_timeout(&rh->op_done, HZ); ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { --=20 2.51.0 From nobody Fri Jun 19 22:16:31 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B78A53A5E6D for ; Tue, 21 Apr 2026 17:54:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776794095; cv=none; b=RXSSQtQ5bOqmJX++E0BiAXuLsF8tDM4g4kppiT+QniVMtNLkZ0OmqiBCqzMZpPwyKrT1ZbG2tTa+dDLcPs51NSRfpIu1Gz8LjLFz8plZW3hAKyFDcnWXwKB495WeXFZ2SW8iieNL0o+quXeP5eN9PzpXzhwW0NGBQ4Itqfqwcpg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776794095; c=relaxed/simple; bh=TcGBdft8ef+1JXeXz1ZtqewxU4mcE8tysfIYbnH8K7o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=en6l9VB4uucZrxsIkT4bzNOZHU2qbHG3MsrgDmprSxY05SJwmTYoxX3ItbMnV0v+P4tu9XTLezRbQBgsg5QR0wnp+WN6s6CPMLGf106kxJHJ9nvV6fs1hGB9SCnqhs8k/qhwNQyE02zb/aJV08SxJ+g4qkv2fAcCmE0FqxHyq8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=CWSloMmh; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="CWSloMmh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776794094; x=1808330094; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TcGBdft8ef+1JXeXz1ZtqewxU4mcE8tysfIYbnH8K7o=; b=CWSloMmhlMiL4dGQ1mpZVb+unNJNfuAjU5ZDTG6PVLCZSWK4mKkZvOgu ujr7cU6eClyJOrWL5IEsU2gSmKt+PpAGMq6js4VIkwsTK80G8L3AD21Lo RKlNAgwa4hvmxc8R3hPII0OwZ1DaE+nD40GneviZLIjJJABi9oRnPCdC9 0zS62SClqXNeCPB/IPgtij6xVxsQMViH+FYABwKA7FEYHle48Toxrmjpe +tsh4QOc37I5hgGY1n0CDxU3sjPai0ubym0mihZGtZaoUBfPU+rkFLO2Q WIzTGqlAn7wwHmltwaE3TjC/L9184kXAVTAJPR01x/zLUafq0comfgEt5 Q==; X-CSE-ConnectionGUID: gkCgaDxWS+ablpp6AJ5f8w== X-CSE-MsgGUID: SwX9ouPjTH+lz1JhxmWqvg== X-IronPort-AV: E=McAfee;i="6800,10657,11763"; a="77651358" X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="77651358" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:54:53 -0700 X-CSE-ConnectionGUID: 1QtFJrveTzWqdrtqb9GWpw== X-CSE-MsgGUID: qiyDLJ+3RI6vDhKPyn9vXg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="227494875" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.242]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:54:52 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 03/16] i3c: mipi-i3c-hci: Prevent DMA enqueue while ring is aborting or in error Date: Tue, 21 Apr 2026 20:54:22 +0300 Message-ID: <20260421175435.122094-4-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260421175435.122094-1-adrian.hunter@intel.com> References: <20260421175435.122094-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Block the DMA enqueue path while a Ring abort is in progress or after an error condition has been detected. Previously, new transfers could be enqueued while the DMA Ring was being aborted or while error handling was underway. This allowed enqueue and error-recovery paths to run concurrently, potentially interfering with each other and corrupting Ring state. Introduce explicit enqueue blocking and a wait queue to serialize access: enqueue operations now wait until abort or error handling has completed before proceeding. Enqueue is unblocked once the Ring is safely restarted. Note, there is only 1 ring bundle configured, and a transfer error causes the controller to halt ring (bundle) operation, so there is only ever 1 outstanding error at a time. Furthermore, a later patch ensures that only the currently active transfer list can time out. Consequently, the DMA queue will not be unblocked while there are outstanding transfer errors or timeouts. Signed-off-by: Adrian Hunter --- Changes in V2: Improve commit message drivers/i3c/master/mipi-i3c-hci/core.c | 1 + drivers/i3c/master/mipi-i3c-hci/dma.c | 25 +++++++++++++++++++++++-- drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index afb0764b5e1f..44617eb3a3f1 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -973,6 +973,7 @@ static int i3c_hci_probe(struct platform_device *pdev) =20 spin_lock_init(&hci->lock); mutex_init(&hci->control_mutex); + init_waitqueue_head(&hci->enqueue_wait_queue); =20 /* * Multi-bus instances share the same MMIO address range, but not diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 4cd32e3afa7b..314635e6e190 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -484,6 +484,12 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, =20 spin_lock_irq(&hci->lock); =20 + while (unlikely(hci->enqueue_blocked)) { + spin_unlock_irq(&hci->lock); + wait_event(hci->enqueue_wait_queue, !READ_ONCE(hci->enqueue_blocked)); + spin_lock_irq(&hci->lock); + } + if (n > rh->xfer_space) { spin_unlock_irq(&hci->lock); hci_dma_unmap_xfer(hci, xfer_list, n); @@ -539,6 +545,14 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, return 0; } =20 +static void hci_dma_unblock_enqueue(struct i3c_hci *hci) +{ + if (hci->enqueue_blocked) { + hci->enqueue_blocked =3D false; + wake_up_all(&hci->enqueue_wait_queue); + } +} + static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, struct hci_xfer *xfer_list, int n) { @@ -550,12 +564,17 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 guard(mutex)(&hci->control_mutex); =20 + spin_lock_irq(&hci->lock); + ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { + hci->enqueue_blocked =3D true; + spin_unlock_irq(&hci->lock); /* stop the ring */ reinit_completion(&rh->op_done); rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); wait_for_completion_timeout(&rh->op_done, HZ); + spin_lock_irq(&hci->lock); ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { /* @@ -567,8 +586,6 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } } =20 - spin_lock_irq(&hci->lock); - for (i =3D 0; i < n; i++) { struct hci_xfer *xfer =3D xfer_list + i; int idx =3D xfer->ring_entry; @@ -604,6 +621,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP); =20 + hci_dma_unblock_enqueue(hci); + spin_unlock_irq(&hci->lock); =20 return did_unqueue; @@ -647,6 +666,8 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, stru= ct hci_rh_data *rh) } if (xfer->completion) complete(xfer->completion); + if (RESP_STATUS(resp)) + hci->enqueue_blocked =3D true; } =20 done_ptr =3D (done_ptr + 1) % rh->xfer_entries; diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index f17f43494c1b..d630400ec945 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -54,6 +54,8 @@ struct i3c_hci { struct mutex control_mutex; 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21 Apr 2026 10:54:53 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 04/16] i3c: mipi-i3c-hci: Wait for DMA ring restart to complete Date: Tue, 21 Apr 2026 20:54:23 +0300 Message-ID: <20260421175435.122094-5-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260421175435.122094-1-adrian.hunter@intel.com> References: <20260421175435.122094-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Although hci_dma_dequeue_xfer() is serialized against itself via control_mutex, this does not guarantee that a DMA ring restart triggered by a previous invocation has fully completed. When the function is called again in rapid succession, the DMA ring may still be transitioning back to the running state, which may confound or disrupt further state changes. Address this by waiting for the DMA ring restart to complete before continuing. Signed-off-by: Adrian Hunter --- Changes in V2: None drivers/i3c/master/mipi-i3c-hci/dma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 314635e6e190..28614fdbf558 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -617,6 +617,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } =20 /* restart the ring */ + reinit_completion(&rh->op_done); mipi_i3c_hci_resume(hci); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP); @@ -625,6 +626,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 spin_unlock_irq(&hci->lock); =20 + wait_for_completion_timeout(&rh->op_done, HZ); + return did_unqueue; } =20 --=20 2.51.0 From nobody Fri Jun 19 22:16:31 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0266C3A257C for ; Tue, 21 Apr 2026 17:54:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776794102; cv=none; b=GXaSpg1m7jRX9usTBwjbjydPAI4Ad7IguMvCMGJGleE0Da09tZ00ntCbFwSHOwXj9zhyl4xPH3vIR/UEqVScb1WPXQV6oAUXYmLrwZ7apH1vj1MMeN3BMwr/X+VCUJTO4LNzDINRwanWmKMJ1aVaHxuUdSl1GZJhQR+Chtimw14= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776794102; c=relaxed/simple; bh=21Nmu5DErPUi5uJFOhMPfpCk7QS82TPLuGrGDAhoejg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nOkCJsoKCw963L8sG4a9rkiOZubVgcTAC3fDLxSfqkFdDn6o2cHkSn6dvkqnTaSdDTJEZl+lhx88aHYGCOZ9LjZDSu58TiD2zX+qlW3ojM507sqjanPHH7NOiAhhQ26UOPQbaDaYPizLhcUm9/JfJs11bsv+p9mPiBEFcGha4xQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mW+dXJW/; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mW+dXJW/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776794097; x=1808330097; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=21Nmu5DErPUi5uJFOhMPfpCk7QS82TPLuGrGDAhoejg=; b=mW+dXJW/9fSjn3jtmkD6QTeexoOWE19fRFgHID+ghbCdUKxxA8nCWJ5U Af5hhddcbyCN8NTUjc2bu2fT999YxFAkeLFigU+n+gWcXxF/+Njx09zFe E1jsc/+bLXhWmmqcyULzn2LfltspA3SqQiXc5U70MnB4iXWV7wNM9Mq3c 4Fpx8R5q+oE8ja8cGmnbqpwY9YdJJG7IlngP1aT5Ez53/IOYKWs8BOhSU R3i+ACwzwS2z9Lst5zwBBNO0kCl6YA+xgZdBKxPug/zRNhqy6vEtA2PF/ o8zCNCSrDtOpQIAnPhxRv3m0Twh0vOxgaSbVGTe44KmQ/MiiZoUtmIDAi A==; X-CSE-ConnectionGUID: cZnhxaTlQ5SypsIpadgLyg== X-CSE-MsgGUID: Dq5qLHHYS6ylaAqtuEK8JA== X-IronPort-AV: E=McAfee;i="6800,10657,11763"; a="77651368" X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="77651368" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:54:57 -0700 X-CSE-ConnectionGUID: Y9af/oA4ScOhSi1oBzVBgA== X-CSE-MsgGUID: 20Bl7tAkSja3/xqUhJ5c/w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="227494897" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.242]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:54:55 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 05/16] i3c: mipi-i3c-hci: Move hci_dma_xfer_done() definition Date: Tue, 21 Apr 2026 20:54:24 +0300 Message-ID: <20260421175435.122094-6-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260421175435.122094-1-adrian.hunter@intel.com> References: <20260421175435.122094-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move hci_dma_xfer_done() earlier in the file to avoid a forward declaration needed by a subsequent change. No functional change. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V2: Added Frank's Rev'd-by drivers/i3c/master/mipi-i3c-hci/dma.c | 98 +++++++++++++-------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 28614fdbf558..c9852b85d6b0 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -545,6 +545,55 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, return 0; } =20 +static void hci_dma_xfer_done(struct i3c_hci *hci, struct hci_rh_data *rh) +{ + u32 op1_val, op2_val, resp, *ring_resp; + unsigned int tid, done_ptr =3D rh->done_ptr; + unsigned int done_cnt =3D 0; + struct hci_xfer *xfer; + + for (;;) { + op2_val =3D rh_reg_read(RING_OPERATION2); + if (done_ptr =3D=3D FIELD_GET(RING_OP2_CR_DEQ_PTR, op2_val)) + break; + + ring_resp =3D rh->resp + rh->resp_struct_sz * done_ptr; + resp =3D *ring_resp; + tid =3D RESP_TID(resp); + dev_dbg(&hci->master.dev, "resp =3D 0x%08x", resp); + + xfer =3D rh->src_xfers[done_ptr]; + if (!xfer) { + dev_dbg(&hci->master.dev, "orphaned ring entry"); + } else { + hci_dma_unmap_xfer(hci, xfer, 1); + rh->src_xfers[done_ptr] =3D NULL; + xfer->ring_entry =3D -1; + xfer->response =3D resp; + if (tid !=3D xfer->cmd_tid) { + dev_err(&hci->master.dev, + "response tid=3D%d when expecting %d\n", + tid, xfer->cmd_tid); + /* TODO: do something about it? */ + } + if (xfer->completion) + complete(xfer->completion); + if (RESP_STATUS(resp)) + hci->enqueue_blocked =3D true; + } + + done_ptr =3D (done_ptr + 1) % rh->xfer_entries; + rh->done_ptr =3D done_ptr; + done_cnt +=3D 1; + } + + rh->xfer_space +=3D done_cnt; + op1_val =3D rh_reg_read(RING_OPERATION1); + op1_val &=3D ~RING_OP1_CR_SW_DEQ_PTR; + op1_val |=3D FIELD_PREP(RING_OP1_CR_SW_DEQ_PTR, done_ptr); + rh_reg_write(RING_OPERATION1, op1_val); +} + static void hci_dma_unblock_enqueue(struct i3c_hci *hci) { if (hci->enqueue_blocked) { @@ -636,55 +685,6 @@ static int hci_dma_handle_error(struct i3c_hci *hci, s= truct hci_xfer *xfer_list, return hci_dma_dequeue_xfer(hci, xfer_list, n) ? -EIO : 0; } =20 -static void hci_dma_xfer_done(struct i3c_hci *hci, struct hci_rh_data *rh) -{ - u32 op1_val, op2_val, resp, *ring_resp; - unsigned int tid, done_ptr =3D rh->done_ptr; - unsigned int done_cnt =3D 0; - struct hci_xfer *xfer; - - for (;;) { - op2_val =3D rh_reg_read(RING_OPERATION2); - if (done_ptr =3D=3D FIELD_GET(RING_OP2_CR_DEQ_PTR, op2_val)) - break; - - ring_resp =3D rh->resp + rh->resp_struct_sz * done_ptr; - resp =3D *ring_resp; - tid =3D RESP_TID(resp); - dev_dbg(&hci->master.dev, "resp =3D 0x%08x", resp); - - xfer =3D rh->src_xfers[done_ptr]; - if (!xfer) { - dev_dbg(&hci->master.dev, "orphaned ring entry"); - } else { - hci_dma_unmap_xfer(hci, xfer, 1); - rh->src_xfers[done_ptr] =3D NULL; - xfer->ring_entry =3D -1; - xfer->response =3D resp; - if (tid !=3D xfer->cmd_tid) { - dev_err(&hci->master.dev, - "response tid=3D%d when expecting %d\n", - tid, xfer->cmd_tid); - /* TODO: do something about it? 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Ensure that state is current by explicitly invoking hci_dma_xfer_done() from the dequeue path. This handles cases where the interrupt handler has not (yet) run. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- Changes in V2: Added Frank's Rev'd-by drivers/i3c/master/mipi-i3c-hci/dma.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index c9852b85d6b0..28e4d38f55d3 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -635,6 +635,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } } =20 + hci_dma_xfer_done(hci, rh); + for (i =3D 0; i < n; i++) { struct hci_xfer *xfer =3D xfer_list + i; int idx =3D xfer->ring_entry; --=20 2.51.0 From nobody Fri Jun 19 22:16:31 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0095339DBF3 for ; Tue, 21 Apr 2026 17:55:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776794102; cv=none; b=KwbjI7XnMsfd2a1Uj+9MD6oQk5zMby2BCYX1h26Nl/OvlI9vLKjHgqEH3peGcNeIWKd4RYQcmCZKZiv3AzREvtDtUzrxU1l6rI0CzS/LqoHNoWpHTHAeCl0ySLUCsHGUe+u+PiyudNnkByLJsLm+0nmFzsg8kJNC8b1JkRNjj30= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776794102; c=relaxed/simple; bh=vIipsx5svp72kwB41kARwQF7UhLQmZOq5LWQKjJv/G4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UOjZXEcrJ95clnbGYBDpa82hOpSPxZ4bidcBHuKZDfAhccnw9fU0p8DsQLE4szEsPeUfD5AzH08iJdvf0H0l1NtURbRwGKZ4+TRLvPPEnaHEyIwtQju37ewhsCb3E5ZdASSvXmx1RIMqqeW0lsOdx9iHXyGYYgPMBapTwOvmb7E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=XzCNPzfJ; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XzCNPzfJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776794101; x=1808330101; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vIipsx5svp72kwB41kARwQF7UhLQmZOq5LWQKjJv/G4=; b=XzCNPzfJrSrdXLJhNxgrFU+hSdZuFui/GwBQwqYl+mXxUhkDh5LXe9ah EeIyVZa3fdmxVHZHKIMtMWa6+Mx0ADEEuwIL9iMQ/+zLpio2cwDYI3tRl TO5fxFCdASUh7fGYf2wq8dLKg1qoBWys23abNltYx5KMIQiMj/7JKmRnZ fR2eAA8RKrfLpUyfjuUHHX872vm2ebN6uwjIZM6rEh6dI2E1UKL9HmlWX VLgU3zd7HNdZtJnawxZDh6bFOxFuDkXwW0+mK+1cFDgO85rtIJUI3lUIA ymC007gEmtpCherr8XjfmJU4ve3RzObDxp5F6aURG8/FYKxQ6ZqzBf6im A==; X-CSE-ConnectionGUID: B/J/6H2HRS6RVMhAFOwCJQ== X-CSE-MsgGUID: lTZ0TjkhRK6ZZP9qEUAujg== X-IronPort-AV: E=McAfee;i="6800,10657,11763"; a="77651378" X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="77651378" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:55:00 -0700 X-CSE-ConnectionGUID: eU1ft4tfTLCQnme+Dw9g1Q== X-CSE-MsgGUID: WMopnoCQSW6wefY8Gr7FMw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="227494921" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.242]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:54:59 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 07/16] i3c: mipi-i3c-hci: Complete transfer lists immediately on error Date: Tue, 21 Apr 2026 20:54:26 +0300 Message-ID: <20260421175435.122094-8-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260421175435.122094-1-adrian.hunter@intel.com> References: <20260421175435.122094-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In DMA mode, transfer lists are currently completed only when the final transfer in the list completes. If an earlier transfer fails, the list is left incomplete and callers wait until timeout. There is no need to wait for a timeout, as the completion path in i3c_hci_process_xfer() already checks for error status. Complete the transfer list as soon as any transfer in the list reports an error. This avoids unnecessary delays and spurious timeouts on error. Complete a transfer list completion immediately there is an error. Signed-off-by: Adrian Hunter --- Changes in V2: Renamed completing_xfer to final_xfer drivers/i3c/master/mipi-i3c-hci/dma.c | 6 ++++-- drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 28e4d38f55d3..899fdf6555a8 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -502,6 +502,8 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, struct hci_xfer *xfer =3D xfer_list + i; u32 *ring_data =3D rh->xfer + rh->xfer_struct_sz * enqueue_ptr; =20 + xfer->final_xfer =3D xfer_list + n - 1; + /* store cmd descriptor */ *ring_data++ =3D xfer->cmd_desc[0]; *ring_data++ =3D xfer->cmd_desc[1]; @@ -576,8 +578,8 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, stru= ct hci_rh_data *rh) tid, xfer->cmd_tid); /* TODO: do something about it? */ } - if (xfer->completion) - complete(xfer->completion); + if (xfer =3D=3D xfer->final_xfer || RESP_STATUS(resp)) + complete(xfer->final_xfer->completion); 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d="scan'208";a="227494932" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.242]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:55:00 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 08/16] i3c: mipi-i3c-hci: Avoid restarting DMA ring after aborting wrong transfer Date: Tue, 21 Apr 2026 20:54:27 +0300 Message-ID: <20260421175435.122094-9-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260421175435.122094-1-adrian.hunter@intel.com> References: <20260421175435.122094-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Software ABORT of the DMA ring is used to recover from transfer list timeouts, but it is inherently racy. The intended transfer list may complete just before the ABORT takes effect, causing the subsequent transfer list to be aborted instead. In this case, an incomplete transfer list may remain in the ring and has not yet been processed by hci_dma_dequeue_xfer(). Restarting the DMA ring at that point can lead to unpredictable results. Detect when the next queued transfer is not the first entry of a transfer list and does not belong to the list currently being dequeued. In that case, skip restarting the DMA ring and defer recovery until a subsequent call to hci_dma_dequeue_xfer(), which will safely restart the ring once the incomplete list is handled. Signed-off-by: Adrian Hunter --- Changes in V2: Renamed completing_xfer to final_xfer drivers/i3c/master/mipi-i3c-hci/dma.c | 15 +++++++++++++++ drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 899fdf6555a8..268f54b32101 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -503,6 +503,7 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, u32 *ring_data =3D rh->xfer + rh->xfer_struct_sz * enqueue_ptr; =20 xfer->final_xfer =3D xfer_list + n - 1; + xfer->xfer_list_pos =3D i; =20 /* store cmd descriptor */ *ring_data++ =3D xfer->cmd_desc[0]; @@ -669,6 +670,20 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } } =20 + /* + * A software ABORT may race with transfer completion and abort the next + * transfer list instead. Detect that case, and do not restart the ring. + * It will be handled by a subsequent dequeue. + */ + if (!did_unqueue) { + struct hci_xfer *xfer =3D rh->src_xfers[rh->done_ptr]; + + if (xfer && xfer->xfer_list_pos && xfer->final_xfer !=3D xfer_list->fina= l_xfer) { + spin_unlock_irq(&hci->lock); + return false; + } + } + /* restart the ring */ reinit_completion(&rh->op_done); mipi_i3c_hci_resume(hci); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index f07fc627d4d2..83d4f13a68a3 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -107,6 +107,7 @@ struct hci_xfer { struct hci_xfer *final_xfer; int ring_number; int ring_entry; + int xfer_list_pos; }; }; }; --=20 2.51.0 From nobody Fri Jun 19 22:16:31 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D8243A5E8C for ; Tue, 21 Apr 2026 17:55:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776794107; cv=none; b=Tzud8pM+msnhszXVJO7Hiq7KBo/Sj4/wioCcf9D7KJyzEW+p+aXNt0TBmv+MQSWuyYtPAN3HtVeOLDnS+b4YXD3KMnKLfa75G5LknH/R5ar5jvC8LG2vgKW9csvSNGd06SgOR5ZrHMmqrgIW/w7OjQyjzvC4+aixHcuxaHCJxKs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776794107; c=relaxed/simple; bh=K6dOnNug2a4OXexytx+m3tQO3BPJVpxhYnRpBusol5c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=THTu+qHAsZPVuwNip0FIawprcu1tXW57xeXuQvQNJiVqFBgk58pV0W3IuVlTW3O87F0/kJdqezXkLOLHU+i2aT9kjManCQFYPWp2vAv8UPw1ytLRrQC6WfsSwGKGS58t0yHs4BariGTrJUJ9BBS03/HK4HCD7FgtfsU43t41+pg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Ir3+SLUc; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Ir3+SLUc" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776794104; x=1808330104; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=K6dOnNug2a4OXexytx+m3tQO3BPJVpxhYnRpBusol5c=; b=Ir3+SLUc2FP13PjApe9NNhbjAYZ/bJl3rnrBwklEy2TVVsG0ZxReYdIZ wNqIm33dKcR3uQIp4TFj9tFH5dC/ArHvO8guYZW4XHAWu3ATEHZfkoCbh yz8Vb4EDYMp4eYoowQ+4CF3m08Xh3iOhSb+1/22Qtju2fdIF+Z6xe3XX1 9oNGEV60vokumXheDJAgwW3pGv1siuU9edpKzJxaBokRaxma32hjwmLan F40WQ8w96e0UxFjPFh3IG5C8C+81NnjJ5aauzA3uuxMrZdsuzWoAqSzmL IPMMDirn88+EnFVx5v6ITvSW962XhCv8/48IYJx7I6PoWrpi7gdY1jWZD w==; X-CSE-ConnectionGUID: WYiEF9XpSS2WQHk+zzXNog== X-CSE-MsgGUID: X6f4ZpwYTBK+DwIv9tk5ig== X-IronPort-AV: E=McAfee;i="6800,10657,11763"; a="77651387" X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="77651387" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:55:04 -0700 X-CSE-ConnectionGUID: EWSca4pHSZu4y/UHR39qFg== X-CSE-MsgGUID: CHPyCqMyTrS9TLEUeBTyvQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="227494943" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.242]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:55:02 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 09/16] i3c: mipi-i3c-hci: Add DMA ring abort/reset quirk for Intel controllers Date: Tue, 21 Apr 2026 20:54:28 +0300 Message-ID: <20260421175435.122094-10-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260421175435.122094-1-adrian.hunter@intel.com> References: <20260421175435.122094-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Intel I3C HCI controllers cannot reliably restart a DMA ring after an ABORT. Additional queue resets are required to recover, and must be performed using PIO reset bits even while operating in DMA mode. This behavior is non-standard. Introduce a controller quirk to opt into the required PIO queue resets after a DMA ring abort, and enable it for Intel LPSS I3C controllers. Signed-off-by: Adrian Hunter --- Changes in V2: None drivers/i3c/master/mipi-i3c-hci/core.c | 15 ++++++++++++++- drivers/i3c/master/mipi-i3c-hci/dma.c | 9 +++++++++ drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 44617eb3a3f1..770235ad6b25 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -240,6 +240,18 @@ void mipi_i3c_hci_pio_reset(struct i3c_hci *hci) reg_write(RESET_CONTROL, RX_FIFO_RST | TX_FIFO_RST | RESP_QUEUE_RST); } =20 +#define ALL_QUEUES_RST (CMD_QUEUE_RST | RESP_QUEUE_RST | RX_FIFO_RST | TX_= FIFO_RST | IBI_QUEUE_RST) + +void mipi_i3c_hci_pio_reset_all_queues(struct i3c_hci *hci) +{ + u32 regval; + + reg_write(RESET_CONTROL, ALL_QUEUES_RST); + if (readx_poll_timeout_atomic(reg_read, RESET_CONTROL, regval, + !(regval & ALL_QUEUES_RST), 0, 20)) + dev_err(&hci->master.dev, "%s: Reset queues failed\n", __func__); +} + /* located here rather than dct.c because needed bits are in core reg spac= e */ void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci) { @@ -1040,7 +1052,8 @@ MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match); static const struct platform_device_id i3c_hci_driver_ids[] =3D { { .name =3D "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED | HCI_QUIRK_RPM_IBI_ALLOWED | - HCI_QUIRK_RPM_PARENT_MANAGED }, + HCI_QUIRK_RPM_PARENT_MANAGED | + HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids); diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 268f54b32101..699c6d523eed 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -597,6 +597,13 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, str= uct hci_rh_data *rh) rh_reg_write(RING_OPERATION1, op1_val); } =20 +static void hci_dma_abort_requires_pio_reset_quirk(struct i3c_hci *hci, st= ruct hci_rh_data *rh) +{ + if ((hci->quirks & HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET) && + (rh_reg_read(RING_STATUS) & RING_STATUS_ABORTED)) + mipi_i3c_hci_pio_reset_all_queues(hci); +} + static void hci_dma_unblock_enqueue(struct i3c_hci *hci) { if (hci->enqueue_blocked) { @@ -638,6 +645,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } } =20 + hci_dma_abort_requires_pio_reset_quirk(hci, rh); + hci_dma_xfer_done(hci, rh); =20 for (i =3D 0; i < n; i++) { diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 83d4f13a68a3..01237b12d32e 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -156,10 +156,12 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ #define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed whil= e runtime suspended */ #define HCI_QUIRK_RPM_PARENT_MANAGED BIT(7) /* Runtime PM managed by pare= nt device */ +#define HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET BIT(8) /* Do PIO queue SW = resets after DMA abort */ =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); 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d="scan'208";a="227494950" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.242]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:55:04 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 10/16] i3c: mipi-i3c-hci: Add DMA ring abort quirk for Intel controllers Date: Tue, 21 Apr 2026 20:54:29 +0300 Message-ID: <20260421175435.122094-11-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260421175435.122094-1-adrian.hunter@intel.com> References: <20260421175435.122094-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DMA rings can be aborted either per-ring via RING_CONTROL or globally via HC_CONTROL_ABORT. The driver currently relies on the per-ring mechanism. Some Intel I3C HCI controllers require HC_CONTROL_ABORT to be asserted before a DMA ring abort is effective. This behavior is non-standard. Introduce a controller quirk to select the required abort method and enable it for Intel LPSS I3C controllers. Signed-off-by: Adrian Hunter --- Changes in V2: None drivers/i3c/master/mipi-i3c-hci/core.c | 18 +++++++++++++++-- drivers/i3c/master/mipi-i3c-hci/dma.c | 27 +++++++++++++++++++++++--- drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ 3 files changed, 42 insertions(+), 5 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 770235ad6b25..8274c84b16be 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -231,7 +231,20 @@ static void i3c_hci_bus_cleanup(struct i3c_master_cont= roller *m) =20 void mipi_i3c_hci_resume(struct i3c_hci *hci) { - reg_set(HC_CONTROL, HC_CONTROL_RESUME); + u32 reg =3D reg_read(HC_CONTROL); + + reg |=3D HC_CONTROL_RESUME; + reg &=3D ~HC_CONTROL_ABORT; + reg_write(HC_CONTROL, reg); +} + +void mipi_i3c_hci_abort(struct i3c_hci *hci) +{ + u32 reg =3D reg_read(HC_CONTROL); + + reg &=3D ~HC_CONTROL_RESUME; /* Do not set resume */ + reg |=3D HC_CONTROL_ABORT; + reg_write(HC_CONTROL, reg); } =20 /* located here rather than pio.c because needed bits are in core reg spac= e */ @@ -1053,7 +1066,8 @@ static const struct platform_device_id i3c_hci_driver= _ids[] =3D { { .name =3D "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED | HCI_QUIRK_RPM_IBI_ALLOWED | HCI_QUIRK_RPM_PARENT_MANAGED | - HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET }, + HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET | + HCI_QUIRK_DMA_REQUIRES_HC_ABORT }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids); diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 699c6d523eed..41bbd912df7f 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -597,6 +597,29 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, str= uct hci_rh_data *rh) rh_reg_write(RING_OPERATION1, op1_val); } =20 +static bool hci_dma_requires_hc_abort_quirk(struct i3c_hci *hci, struct hc= i_rh_data *rh) +{ + if (!(hci->quirks & HCI_QUIRK_DMA_REQUIRES_HC_ABORT)) + return false; + + reinit_completion(&rh->op_done); + mipi_i3c_hci_abort(hci); + wait_for_completion_timeout(&rh->op_done, HZ); + rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); + + return true; +} + +static void hci_dma_abort(struct i3c_hci *hci, struct hci_rh_data *rh) +{ + if (hci_dma_requires_hc_abort_quirk(hci, rh)) + return; + + reinit_completion(&rh->op_done); + rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); + wait_for_completion_timeout(&rh->op_done, HZ); +} + static void hci_dma_abort_requires_pio_reset_quirk(struct i3c_hci *hci, st= ruct hci_rh_data *rh) { if ((hci->quirks & HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET) && @@ -630,9 +653,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, hci->enqueue_blocked =3D true; spin_unlock_irq(&hci->lock); /* stop the ring */ - reinit_completion(&rh->op_done); - rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); - wait_for_completion_timeout(&rh->op_done, HZ); + hci_dma_abort(hci, rh); spin_lock_irq(&hci->lock); ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 01237b12d32e..97c31a315a6e 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -157,9 +157,11 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed whil= e runtime suspended */ #define HCI_QUIRK_RPM_PARENT_MANAGED BIT(7) /* Runtime PM managed by pare= nt device */ #define HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET BIT(8) /* Do PIO queue SW = resets after DMA abort */ +#define HCI_QUIRK_DMA_REQUIRES_HC_ABORT BIT(9) /* Use HC_CONTROL ABORT t= o abort DMA */ =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); +void mipi_i3c_hci_abort(struct i3c_hci *hci); void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); void mipi_i3c_hci_pio_reset_all_queues(struct i3c_hci *hci); void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); 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charset="utf-8" Factor the reset-and-restore sequence out of i3c_hci_rpm_resume() into a separate helper. This allows the same logic to be reused for recovery paths in subsequent changes without duplicating suspend/resume handling. No functional change. Signed-off-by: Adrian Hunter --- Changes in V2: Drop redundant i3c_hci_sync_irq_inactive(hci) from i3c_hci_reset_and_restore() because it is called by hci->io->suspend() anyway drivers/i3c/master/mipi-i3c-hci/core.c | 19 +++++++++++++++++-- drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 8274c84b16be..12a0122fb709 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -798,9 +798,8 @@ int i3c_hci_rpm_suspend(struct device *dev) } EXPORT_SYMBOL_GPL(i3c_hci_rpm_suspend); =20 -int i3c_hci_rpm_resume(struct device *dev) +static int i3c_hci_do_reset_and_restore(struct i3c_hci *hci) { - struct i3c_hci *hci =3D dev_get_drvdata(dev); int ret; =20 ret =3D i3c_hci_reset_and_init(hci); @@ -821,6 +820,22 @@ int i3c_hci_rpm_resume(struct device *dev) =20 return 0; } + +int i3c_hci_reset_and_restore(struct i3c_hci *hci) +{ + i3c_hci_bus_disable(hci); + + hci->io->suspend(hci); + + return i3c_hci_do_reset_and_restore(hci); +} + +int i3c_hci_rpm_resume(struct device *dev) +{ + struct i3c_hci *hci =3D dev_get_drvdata(dev); + + return i3c_hci_do_reset_and_restore(hci); +} EXPORT_SYMBOL_GPL(i3c_hci_rpm_resume); =20 static int i3c_hci_runtime_suspend(struct device *dev) diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 97c31a315a6e..a3151c26827e 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -175,4 +175,6 @@ int i3c_hci_process_xfer(struct i3c_hci *hci, struct hc= i_xfer *xfer, int n); int i3c_hci_rpm_suspend(struct device *dev); int i3c_hci_rpm_resume(struct device *dev); =20 +int i3c_hci_reset_and_restore(struct i3c_hci *hci); + #endif --=20 2.51.0 From nobody Fri Jun 19 22:16:31 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6809A3AC0D8 for ; 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a="77651409" X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="77651409" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:55:09 -0700 X-CSE-ConnectionGUID: DztovP0dR0eiCnIWvH3XRw== X-CSE-MsgGUID: wFtK17WDTi+Wb44leVnqLg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="227495025" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.242]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:55:08 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 12/16] i3c: mipi-i3c-hci: Add DMA-mode recovery for internal controller errors Date: Tue, 21 Apr 2026 20:54:31 +0300 Message-ID: <20260421175435.122094-13-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260421175435.122094-1-adrian.hunter@intel.com> References: <20260421175435.122094-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Handle internal I3C HCI errors when operating in DMA mode by adding a simple recovery mechanism. On detection of an internal controller error, mark recovery as needed and attempt to restore operation by performing a software reset followed by state restore. To keep recovery straightforward on this unlikely error path, all currently queued transfers are terminated and completed with an error. This allows the controller to resume operation after internal failures rather than remaining permanently stuck. Note, internal errors indicated by INTR_HC_INTERNAL_ERR, cause the controller to stop. Signed-off-by: Adrian Hunter --- Changes in V2: Rename completing_xfer to final_xfer Add hci_dma_xfer_done() before checking for an already complete transfer Improve commit message drivers/i3c/master/mipi-i3c-hci/cmd.h | 6 ++ drivers/i3c/master/mipi-i3c-hci/core.c | 1 + drivers/i3c/master/mipi-i3c-hci/dma.c | 91 +++++++++++++++++++++++--- drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + 4 files changed, 90 insertions(+), 9 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/cmd.h b/drivers/i3c/master/mip= i-i3c-hci/cmd.h index b1bf87daa651..7bada7b4b2de 100644 --- a/drivers/i3c/master/mipi-i3c-hci/cmd.h +++ b/drivers/i3c/master/mipi-i3c-hci/cmd.h @@ -65,4 +65,10 @@ struct hci_cmd_ops { extern const struct hci_cmd_ops mipi_i3c_hci_cmd_v1; extern const struct hci_cmd_ops mipi_i3c_hci_cmd_v2; =20 +static inline void hci_cmd_set_resp_err(u32 *response, int resp_err) +{ + *response &=3D ~RESP_ERR_FIELD; + *response |=3D FIELD_PREP(RESP_ERR_FIELD, resp_err); +} + #endif diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 12a0122fb709..69dcf5dad3a5 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -668,6 +668,7 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *d= ev_id) if (val & INTR_HC_INTERNAL_ERR) { dev_err(&hci->master.dev, "Host Controller Internal Error\n"); val &=3D ~INTR_HC_INTERNAL_ERR; + hci->recovery_needed =3D true; } =20 if (val) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 41bbd912df7f..4ea623dbed52 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -9,6 +9,7 @@ */ =20 #include +#include #include #include #include @@ -258,6 +259,10 @@ static void hci_dma_init_rh(struct i3c_hci *hci, struc= t hci_rh_data *rh, int i) rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP); =20 + /* + * Do not clear the entries of rh->src_xfers because the recovery uses + * them. In other cases they should be NULL anyway. + */ rh->done_ptr =3D 0; rh->ibi_chunk_ptr =3D 0; rh->xfer_space =3D rh->xfer_entries; @@ -362,7 +367,7 @@ static int hci_dma_init(struct i3c_hci *hci) rh->resp =3D dma_alloc_coherent(rings->sysdev, resps_sz, &rh->resp_dma, GFP_KERNEL); rh->src_xfers =3D - kmalloc_objs(*rh->src_xfers, rh->xfer_entries); + kzalloc_objs(*rh->src_xfers, rh->xfer_entries); ret =3D -ENOMEM; if (!rh->xfer || !rh->resp || !rh->src_xfers) goto err_out; @@ -572,13 +577,15 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, st= ruct hci_rh_data *rh) hci_dma_unmap_xfer(hci, xfer, 1); rh->src_xfers[done_ptr] =3D NULL; xfer->ring_entry =3D -1; - xfer->response =3D resp; if (tid !=3D xfer->cmd_tid) { dev_err(&hci->master.dev, "response tid=3D%d when expecting %d\n", tid, xfer->cmd_tid); - /* TODO: do something about it? */ + hci->recovery_needed =3D true; + if (!RESP_STATUS(resp)) + hci_cmd_set_resp_err(&resp, RESP_ERR_HC_TERMINATED); } + xfer->response =3D resp; if (xfer =3D=3D xfer->final_xfer || RESP_STATUS(resp)) complete(xfer->final_xfer->completion); if (RESP_STATUS(resp)) @@ -635,6 +642,58 @@ static void hci_dma_unblock_enqueue(struct i3c_hci *hc= i) } } =20 +static void hci_dma_error_out_rh(struct i3c_hci *hci, struct hci_rh_data *= rh) +{ + /* + * The entries of rh->src_xfers are not cleared by + * i3c_hci_reset_and_restore(), so can be used here. + */ + for (int i =3D 0; i < rh->xfer_entries; i++) { + struct hci_xfer *xfer =3D rh->src_xfers[i]; + + if (!xfer) + continue; + hci_dma_unmap_xfer(hci, xfer, 1); + rh->src_xfers[i] =3D NULL; + xfer->ring_entry =3D -1; + hci_cmd_set_resp_err(&xfer->response, RESP_ERR_HC_TERMINATED); + if (xfer =3D=3D xfer->final_xfer) + complete(xfer->final_xfer->completion); + } +} + +static void hci_dma_error_out_all(struct i3c_hci *hci) +{ + struct hci_rings_data *rings =3D hci->io_data; + + for (int i =3D 0; i < rings->total; i++) + hci_dma_error_out_rh(hci, &rings->headers[i]); +} + +static void hci_dma_recovery(struct i3c_hci *hci) +{ + int ret; + + dev_err(&hci->master.dev, "Attempting to recover from internal errors\n"); + + for (int i =3D 0; i < 3; i++) { + ret =3D i3c_hci_reset_and_restore(hci); + if (!ret) + break; + dev_err(&hci->master.dev, "Reset and restore failed, error %d\n", ret); + /* Just in case the controller is busy, give it some time */ + msleep(1000); + } + + spin_lock_irq(&hci->lock); + hci_dma_error_out_all(hci); + hci_dma_unblock_enqueue(hci); + hci->recovery_needed =3D false; + spin_unlock_irq(&hci->lock); + + dev_err(&hci->master.dev, "Recovery %s\n", ret ? "failed!" : "done"); +} + static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, struct hci_xfer *xfer_list, int n) { @@ -650,6 +709,17 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { + /* + * The transfer may have already completed, especially + * if recovery has just run. Do nothing in that case. + */ + hci_dma_xfer_done(hci, rh); + if (xfer_list->final_xfer->ring_entry < 0 && + !hci->recovery_needed && !hci->enqueue_blocked && + ring_status =3D=3D (RING_STATUS_ENABLED | RING_STATUS_RUNNING)) { + spin_unlock_irq(&hci->lock); + return false; + } hci->enqueue_blocked =3D true; spin_unlock_irq(&hci->lock); /* stop the ring */ @@ -657,12 +727,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, spin_lock_irq(&hci->lock); ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { - /* - * We're deep in it if ever this condition is ever met. - * Hardware might still be writing to memory, etc. - */ - dev_crit(&hci->master.dev, "unable to abort the ring\n"); - WARN_ON(1); + dev_err(&hci->master.dev, "Unable to abort the DMA ring\n"); + hci->recovery_needed =3D true; } } =20 @@ -670,6 +736,13 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 hci_dma_xfer_done(hci, rh); =20 + if (hci->recovery_needed) { + hci->enqueue_blocked =3D true; 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charset="utf-8" When a transfer list is only partially completed due to an error, hci_dma_dequeue_xfer() overwrites the remaining DMA ring entries with NoOp commands and restarts the ring to flush them out. While NoOp commands are expected to complete successfully, they may still fail to complete if the DMA ring is stuck. Explicitly wait for the NoOp commands to finish, and trigger controller recovery if they do not complete or report an error. This ensures that partially completed transfer lists are reliably resolved and that a stuck ring is recovered promptly. Signed-off-by: Adrian Hunter --- Changes in V2: Rename completing_xfer to final_xfer Add missing reinit_completion() drivers/i3c/master/mipi-i3c-hci/dma.c | 39 ++++++++++++++++++++++----- 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 4ea623dbed52..dfc91de66ba5 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -694,11 +694,33 @@ static void hci_dma_recovery(struct i3c_hci *hci) dev_err(&hci->master.dev, "Recovery %s\n", ret ? "failed!" : "done"); } =20 +static bool hci_dma_wait_for_noop(struct i3c_hci *hci, struct hci_xfer *xf= er_list, int n, + int noop_pos) +{ + struct completion *done =3D xfer_list->final_xfer->completion; + bool timeout =3D !wait_for_completion_timeout(done, HZ); + u32 error =3D timeout; + + for (int i =3D noop_pos; i < n && !error; i++) + error =3D RESP_STATUS(xfer_list[i].response); + + if (!error) + return true; + + if (timeout) + dev_err(&hci->master.dev, "NoOp timeout error\n"); + else + dev_err(&hci->master.dev, "NoOp error %u\n", error); + + return false; +} + static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, struct hci_xfer *xfer_list, int n) { struct hci_rings_data *rings =3D hci->io_data; struct hci_rh_data *rh =3D &rings->headers[xfer_list[0].ring_number]; + int noop_pos =3D -1; unsigned int i; bool did_unqueue =3D false; u32 ring_status; @@ -706,7 +728,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, guard(mutex)(&hci->control_mutex); =20 spin_lock_irq(&hci->lock); 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charset="utf-8" Transfer timeouts are currently measured from the point where a transfer list is queued to the controller. This can cause transfers to time out before they have actually started, if earlier queued transfers consume the timeout interval. Fix this by recording when a transfer reaches the head of the queue and adjusting the timeout calculation to start from that point. The existing low-overhead completion-based timeout mechanism is preserved, but care is taken to ensure the transfer start time is consistently recorded for both PIO and DMA paths. This prevents premature timeouts while retaining efficient timeout handling. Signed-off-by: Adrian Hunter --- Changes in V2: Do not flag the next transfer as started when there is an error which halts the controller Instead flag it started at the end of hci_dma_dequeue_xfer() Use hci_start_xfer() in pio.c drivers/i3c/master/mipi-i3c-hci/core.c | 19 ++++++++++++++++++- drivers/i3c/master/mipi-i3c-hci/dma.c | 19 ++++++++++++++++++- drivers/i3c/master/mipi-i3c-hci/hci.h | 11 +++++++++++ drivers/i3c/master/mipi-i3c-hci/pio.c | 1 + 4 files changed, 48 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 69dcf5dad3a5..2866d599612a 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -275,13 +275,30 @@ int i3c_hci_process_xfer(struct i3c_hci *hci, struct = hci_xfer *xfer, int n) { struct completion *done =3D xfer[n - 1].completion; unsigned long timeout =3D xfer[n - 1].timeout; + unsigned long remaining_timeout =3D timeout; + long time_taken; + bool started; int ret; =20 + xfer[0].started =3D false; + ret =3D hci->io->queue_xfer(hci, xfer, n); if (ret) return ret; =20 - if (!wait_for_completion_timeout(done, timeout)) { + while (!wait_for_completion_timeout(done, remaining_timeout)) { + scoped_guard(spinlock_irqsave, &hci->lock) { + started =3D xfer[0].started; + time_taken =3D jiffies - xfer[0].start_time; + } + /* Keep waiting if xfer has not started */ + if (!started) + continue; + /* Recalculate timeout based on actual start time */ + if (time_taken < timeout) { + remaining_timeout =3D timeout - time_taken; + continue; + } if (hci->io->dequeue_xfer(hci, xfer, n)) { dev_err(&hci->master.dev, "%s: timeout error\n", __func__); return -ETIMEDOUT; diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index dfc91de66ba5..e169f20608a0 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -543,6 +543,9 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, enqueue_ptr =3D (enqueue_ptr + 1) % rh->xfer_entries; } =20 + if (rh->xfer_space =3D=3D rh->xfer_entries) + hci_start_xfer(xfer_list); + rh->xfer_space -=3D n; =20 op1_val &=3D ~RING_OP1_CR_ENQ_PTR; @@ -558,6 +561,7 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, stru= ct hci_rh_data *rh) u32 op1_val, op2_val, resp, *ring_resp; unsigned int tid, done_ptr =3D rh->done_ptr; unsigned int done_cnt =3D 0; + bool start_next =3D false; struct hci_xfer *xfer; =20 for (;;) { @@ -588,8 +592,14 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, str= uct hci_rh_data *rh) xfer->response =3D resp; if (xfer =3D=3D xfer->final_xfer || RESP_STATUS(resp)) complete(xfer->final_xfer->completion); - if (RESP_STATUS(resp)) + else + hci_start_xfer(xfer); + if (RESP_STATUS(resp)) { hci->enqueue_blocked =3D true; + start_next =3D false; + } else { + start_next =3D true; + } } =20 done_ptr =3D (done_ptr + 1) % rh->xfer_entries; @@ -598,6 +608,10 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, str= uct hci_rh_data *rh) } =20 rh->xfer_space +=3D done_cnt; + if (start_next && rh->xfer_space < rh->xfer_entries) { + xfer =3D rh->src_xfers[done_ptr]; + hci_start_xfer(xfer); + } op1_val =3D rh_reg_read(RING_OPERATION1); op1_val &=3D ~RING_OP1_CR_SW_DEQ_PTR; op1_val |=3D FIELD_PREP(RING_OP1_CR_SW_DEQ_PTR, done_ptr); @@ -816,6 +830,9 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 hci_dma_unblock_enqueue(hci); =20 + if (rh->xfer_space < rh->xfer_entries) + hci_start_xfer(rh->src_xfers[rh->done_ptr]); + spin_unlock_irq(&hci->lock); =20 wait_for_completion_timeout(&rh->op_done, HZ); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 4bf2c66c97b4..243d7a67f6f6 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -11,6 +11,7 @@ #define HCI_H =20 #include +#include =20 /* 32-bit word aware bit and mask macros */ #define W0_MASK(h, l) GENMASK((h) - 0, (l) - 0) @@ -88,11 +89,13 @@ struct hci_xfer { u32 cmd_desc[4]; u32 response; bool rnw; + bool started; void *data; unsigned int data_len; unsigned int cmd_tid; struct completion *completion; unsigned long timeout; + unsigned long start_time; union { struct { /* PIO specific */ @@ -123,6 +126,14 @@ static inline void hci_free_xfer(struct hci_xfer *xfer= , unsigned int n) kfree(xfer); } =20 +static inline void hci_start_xfer(struct hci_xfer *xfer) +{ + if (!xfer->started) { + xfer->started =3D true; + xfer->start_time =3D jiffies; + } +} + /* This abstracts PIO vs DMA operations */ struct hci_io_ops { bool (*irq_handler)(struct i3c_hci *hci); diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mip= i-i3c-hci/pio.c index 8f48a81e65ab..6b8cc5f2b4d2 100644 --- a/drivers/i3c/master/mipi-i3c-hci/pio.c +++ b/drivers/i3c/master/mipi-i3c-hci/pio.c @@ -605,6 +605,7 @@ static bool hci_pio_process_cmd(struct i3c_hci *hci, st= ruct hci_pio_data *pio) * Finally send the command. */ hci_pio_write_cmd(hci, pio->curr_xfer); + hci_start_xfer(pio->curr_xfer); /* * And move on. */ --=20 2.51.0 From nobody Fri Jun 19 22:16:31 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0CD03D5649 for ; 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charset="utf-8" dma_alloc_coherent() allocates memory in whole pages, which can waste space when command and response queues are allocated separately. Allocate the DMA command and response queues from a single coherent allocation instead, while preserving the required 4-byte alignment. This reduces memory overhead without changing behavior. Signed-off-by: Adrian Hunter --- Changes in V2: Check for failed allocation before assignments to avoid doing arithmetic with NULL pointers drivers/i3c/master/mipi-i3c-hci/dma.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index e169f20608a0..73fd86b6fb17 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -186,14 +186,12 @@ static void hci_dma_free(void *data) for (int i =3D 0; i < rings->total; i++) { rh =3D &rings->headers[i]; =20 - if (rh->xfer) - dma_free_coherent(rings->sysdev, - rh->xfer_struct_sz * rh->xfer_entries, - rh->xfer, rh->xfer_dma); - if (rh->resp) - dma_free_coherent(rings->sysdev, - rh->resp_struct_sz * rh->xfer_entries, - rh->resp, rh->resp_dma); + if (rh->xfer) { + size_t sz =3D round_up(rh->xfer_struct_sz * rh->xfer_entries, 4); + + sz +=3D rh->resp_struct_sz * rh->xfer_entries; + dma_free_coherent(rings->sysdev, sz, rh->xfer, rh->xfer_dma); + } kfree(rh->src_xfers); if (rh->ibi_status) dma_free_coherent(rings->sysdev, @@ -359,18 +357,18 @@ static int hci_dma_init(struct i3c_hci *hci) dev_dbg(&hci->master.dev, "xfer_struct_sz =3D %d, resp_struct_sz =3D %d", rh->xfer_struct_sz, rh->resp_struct_sz); - xfers_sz =3D rh->xfer_struct_sz * rh->xfer_entries; + xfers_sz =3D round_up(rh->xfer_struct_sz * rh->xfer_entries, 4); resps_sz =3D rh->resp_struct_sz * rh->xfer_entries; =20 - rh->xfer =3D dma_alloc_coherent(rings->sysdev, xfers_sz, + rh->xfer =3D dma_alloc_coherent(rings->sysdev, xfers_sz + resps_sz, &rh->xfer_dma, GFP_KERNEL); - rh->resp =3D dma_alloc_coherent(rings->sysdev, resps_sz, - &rh->resp_dma, GFP_KERNEL); rh->src_xfers =3D kzalloc_objs(*rh->src_xfers, rh->xfer_entries); ret =3D -ENOMEM; - if (!rh->xfer || !rh->resp || !rh->src_xfers) + if (!rh->xfer || !rh->src_xfers) goto err_out; + rh->resp =3D rh->xfer + xfers_sz; + rh->resp_dma =3D rh->xfer_dma + xfers_sz; =20 /* IBIs */ =20 --=20 2.51.0 From nobody Fri Jun 19 22:16:31 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BACA3D6CC1 for ; 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a="77651441" X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="77651441" Received: from fmviesa006.fm.intel.com ([10.60.135.146]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:55:16 -0700 X-CSE-ConnectionGUID: IOJwsHPMSp+vghN35tFTuA== X-CSE-MsgGUID: cm5wJJnhS1Cr0nQslXuHkQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,192,1770624000"; d="scan'208";a="227495095" Received: from hrotuna-mobl2.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.242]) by fmviesa006-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2026 10:55:15 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 16/16] i3c: mipi-i3c-hci: Increase DMA transfer ring size to maximum Date: Tue, 21 Apr 2026 20:54:35 +0300 Message-ID: <20260421175435.122094-17-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260421175435.122094-1-adrian.hunter@intel.com> References: <20260421175435.122094-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The DMA transfer ring is currently limited to 16 entries, despite the MIPI I3C HCI supporting up to 32 devices. When the ring lacks space for a new transfer list, the driver returns -EBUSY, which can be unexpected for clients. Increase the DMA transfer ring size to the maximum supported value of 255 entries. This effectively eliminates ring-space exhaustion in practice and avoids the complexity of adding secondary queuing mechanisms. Even at the maximum size, the memory overhead remains small (approximately 24 bytes per entry by default). Signed-off-by: Adrian Hunter --- Changes in V2: None drivers/i3c/master/mipi-i3c-hci/dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 73fd86b6fb17..3d8fa0e5ed67 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -27,7 +27,7 @@ */ =20 #define XFER_RINGS 1 /* max: 8 */ -#define XFER_RING_ENTRIES 16 /* max: 255 */ +#define XFER_RING_ENTRIES 255 /* max: 255 */ =20 #define IBI_RINGS 1 /* max: 8 */ #define IBI_STATUS_RING_ENTRIES 32 /* max: 255 */ --=20 2.51.0