From nobody Wed Jun 10 21:44:24 2026 Received: from canpmsgout02.his.huawei.com (canpmsgout02.his.huawei.com [113.46.200.217]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC9EE3D647A; Tue, 21 Apr 2026 13:04:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.217 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776776658; cv=none; b=AxWlkvc2q/F3Y5er4t7I3E018NNey7QPqQ5D/DJjk6soh1kuaqGVnza8QwqTIO/4sV8iJJdYKAjYtnt7E21JXWug0vyacGJWMdLJCKKUHk/rycVwLYVKp0Hs4PQpi49g3oLyQpZ8CcSVQ6cQWvtd8zleO/yOp1c/p0UT+rf+vqM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776776658; c=relaxed/simple; bh=Bf/AhHeVs+Mz693A7hDBd/4LAGXIKwEt5koD61JfULc=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=GPUAYZ+wPJ0fohXTfP5gFgDp4gTuHyTIOgwXgEtmn0EQ6D3sGAiNqq7PKyCZNrnaRLxXCYub+pzRX+yjpyzkRpKdq/n2gKWWJkfH+f3Ew2nCEkN/YhRBxYMglGiMFCv68hy4FlLRWMppW78LMjX5KtfZgN95JjlXg6ETehQ5P2U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=TVuwBa/P; arc=none smtp.client-ip=113.46.200.217 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="TVuwBa/P" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=Og64l9mq/6QYoXZ5oj3+y+6KjT13Ec3Oh9cGPi7dA2E=; b=TVuwBa/PyuGmFd8O96VXi5OJ5B6jwR6sQuoE6Nlnw0hqzh/R/cnWX+CVtNLDx3JpaPWOPssRf c7YvnOZWTu/JDlZhsTSAbOyHH7ewUCbDwEDhjPVaMuU/3ZOShVnoeu5UTs0l0/hojvKEUnYgj/q bIjOKd/I+ApqoGdjqPkOtTs= Received: from mail.maildlp.com (unknown [172.19.163.0]) by canpmsgout02.his.huawei.com (SkyGuard) with ESMTPS id 4g0Mnw4v8ZzcZyv; Tue, 21 Apr 2026 20:57:24 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 06BF840537; Tue, 21 Apr 2026 21:04:06 +0800 (CST) Received: from huawei.com (10.90.53.73) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Tue, 21 Apr 2026 21:04:04 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , Subject: [PATCH v5 1/3] lib/bitrev: Introduce GENERIC_BITREVERSE and cleanup Kconfig Date: Tue, 21 Apr 2026 21:07:50 +0800 Message-ID: <20260421130752.607500-2-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260421130752.607500-1-ruanjinjie@huawei.com> References: <20260421130752.607500-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" Currently, the bit reversal lookup table is controlled by !HAVE_ARCH_BITREVERSE. This makes it difficult for architectures to provide a hardware-accelerated implementation while still falling back to the generic table for specific configurations. Introduce CONFIG_GENERIC_BITREVERSE to explicitly manage the generic lookup table implementation. By using 'def_bool !HAVE_ARCH_BITREVERSE' with a dependency on 'BITREVERSE', we ensure that: 1. The table is only compiled when needed. 2. The .config is not polluted with useless options when BITREVERSE is disabled. 3. Avoids bloating the .data section for architectures that have full hardware bit-reverse support and don't need the table. Update lib/bitrev.c to use CONFIG_GENERIC_BITREVERSE instead of checking the absence of HAVE_ARCH_BITREVERSE. This provides a cleaner interface for architectures like RISC-V that may want to selectively use the generic implementation as a fallback. Suggested-by: David Laight Suggested-by: Yury Norov Signed-off-by: Jinjie Ruan --- lib/Kconfig | 18 ++++++++++++++++++ lib/bitrev.c | 4 ++-- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/lib/Kconfig b/lib/Kconfig index 0f2fb9610647..e3f9719a4d6f 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -62,6 +62,24 @@ config HAVE_ARCH_BITREVERSE This option enables the use of hardware bit-reversal instructions on architectures which support such operations. =20 +config GENERIC_BITREVERSE + def_bool !HAVE_ARCH_BITREVERSE + depends on BITREVERSE + help + This option provides the standard software-based bit reversal + implementation using a lookup table. + + Architecture-specific implementations (HAVE_ARCH_BITREVERSE) + and this generic version are not necessarily mutually exclusive + at the configuration level, but selecting this ensures that + the generic `bitrev8/16/32` functions are available when the + CPU does not provide native instructions (like RISC-V's ZBKB + extension). + + If you are an architecture maintainer and your CPU has native + bit-reversal instructions, you should select HAVE_ARCH_BITREVERSE + to skip this table-based implementation. + config ARCH_HAS_STRNCPY_FROM_USER bool =20 diff --git a/lib/bitrev.c b/lib/bitrev.c index 81b56e0a7f32..3a53ff67aeba 100644 --- a/lib/bitrev.c +++ b/lib/bitrev.c @@ -1,5 +1,5 @@ // SPDX-License-Identifier: GPL-2.0-only -#ifndef CONFIG_HAVE_ARCH_BITREVERSE +#ifdef CONFIG_GENERIC_BITREVERSE #include #include #include @@ -44,4 +44,4 @@ const u8 byte_rev_table[256] =3D { }; EXPORT_SYMBOL_GPL(byte_rev_table); =20 -#endif /* CONFIG_HAVE_ARCH_BITREVERSE */ +#endif /* CONFIG_GENERIC_BITREVERSE */ --=20 2.34.1 From nobody Wed Jun 10 21:44:24 2026 Received: from canpmsgout10.his.huawei.com (canpmsgout10.his.huawei.com [113.46.200.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 834F83D667C; Tue, 21 Apr 2026 13:04:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.225 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776776655; cv=none; b=ntBRrih/HJ4j2AM1q5U4Io3IQHHiOZsH3yiiv7sVb0nFBVdxGZGOE9iwhJUO6GO+DrFP5uxcR0Qt0VadplTynNUAuzTATspR9S1rXiKx49wQam2SK8yxtMKwdsVLYi3KZm8gkKWQvTeW4+D7BC09y7aL3uA0ZA9hu4aZ68y0Y84= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776776655; c=relaxed/simple; bh=RRwAlN6IpmxPkOxgImIXnsn9WxAITqIcBSOxnOP0Inw=; h=From:To:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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charset="utf-8" Define generic __bitrev8/16/32 using the implementation in , so they can be reused in , such as RISCV. Reviewed-by: Yury Norov Signed-off-by: Jinjie Ruan --- include/asm-generic/bitops/__bitrev.h | 25 +++++++++++++++++++++++++ include/linux/bitrev.h | 20 ++++---------------- 2 files changed, 29 insertions(+), 16 deletions(-) create mode 100644 include/asm-generic/bitops/__bitrev.h diff --git a/include/asm-generic/bitops/__bitrev.h b/include/asm-generic/bi= tops/__bitrev.h new file mode 100644 index 000000000000..f06af929678d --- /dev/null +++ b/include/asm-generic/bitops/__bitrev.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ASM_GENERIC_BITOPS___BITREV_H_ +#define _ASM_GENERIC_BITOPS___BITREV_H_ + +#ifdef CONFIG_GENERIC_BITREVERSE +#include + +extern u8 const byte_rev_table[256]; +static __always_inline __attribute_const__ u8 generic___bitrev8(u8 byte) +{ + return byte_rev_table[byte]; +} + +static __always_inline __attribute_const__ u16 generic___bitrev16(u16 x) +{ + return (generic___bitrev8(x & 0xff) << 8) | generic___bitrev8(x >> 8); +} + +static __always_inline __attribute_const__ u32 generic___bitrev32(u32 x) +{ + return (generic___bitrev16(x & 0xffff) << 16) | generic___bitrev16(x >> 1= 6); +} +#endif /* CONFIG_GENERIC_BITREVERSE */ + +#endif /* _ASM_GENERIC_BITOPS___BITREV_H_ */ diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h index d35b8ec1c485..11620a70e776 100644 --- a/include/linux/bitrev.h +++ b/include/linux/bitrev.h @@ -12,22 +12,10 @@ #define __bitrev8 __arch_bitrev8 =20 #else -extern u8 const byte_rev_table[256]; -static inline u8 __bitrev8(u8 byte) -{ - return byte_rev_table[byte]; -} - -static inline u16 __bitrev16(u16 x) -{ - return (__bitrev8(x & 0xff) << 8) | __bitrev8(x >> 8); -} - -static inline u32 __bitrev32(u32 x) -{ - return (__bitrev16(x & 0xffff) << 16) | __bitrev16(x >> 16); -} - +#include +#define __bitrev32 generic___bitrev32 +#define __bitrev16 generic___bitrev16 +#define __bitrev8 generic___bitrev8 #endif /* CONFIG_HAVE_ARCH_BITREVERSE */ =20 #define __bitrev8x4(x) (__bitrev32(swab32(x))) --=20 2.34.1 From nobody Wed Jun 10 21:44:24 2026 Received: from canpmsgout07.his.huawei.com (canpmsgout07.his.huawei.com [113.46.200.222]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AC453D6474; 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Tue, 21 Apr 2026 21:04:06 +0800 From: Jinjie Ruan To: , , , , , , , , , , , , , , Subject: [PATCH v5 3/3] arch/riscv: Add bitrev.h file to support rev8 and brev8 Date: Tue, 21 Apr 2026 21:07:52 +0800 Message-ID: <20260421130752.607500-4-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260421130752.607500-1-ruanjinjie@huawei.com> References: <20260421130752.607500-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" The RISC-V Bit-manipulation Extension for Cryptography (Zbkb) provides the 'brev8' instruction, which reverses the bits within each byte. Combined with the 'rev8' instruction (from Zbb or Zbkb), which reverses the byte order of a register, we can efficiently implement 16-bit, 32-bit, and (on RV64) 64-bit bit reversal. This is significantly faster than the default software table-lookup implementation in lib/bitrev.c, as it replaces memory accesses and multiple arithmetic operations with just two or three hardware instructions. Select HAVE_ARCH_BITREVERSE as well as GENERIC_BITREVERSE, and provide to utilize these instructions when the Zbkb extension is available at runtime via the alternatives mechanism. Link: https://docs.riscv.org/reference/isa/unpriv/b-st-ext.html Suggested-by: David Laight Signed-off-by: Jinjie Ruan --- arch/riscv/Kconfig | 2 ++ arch/riscv/include/asm/bitrev.h | 51 +++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 arch/riscv/include/asm/bitrev.h diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 90c531e6abf5..4f9e1caee5f9 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -105,6 +105,7 @@ config RISCV select FUNCTION_ALIGNMENT_8B if DYNAMIC_FTRACE_WITH_CALL_OPS select GENERIC_ARCH_TOPOLOGY select GENERIC_ATOMIC64 if !64BIT + select GENERIC_BITREVERSE select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_CPU_DEVICES select GENERIC_CPU_VULNERABILITIES @@ -128,6 +129,7 @@ config RISCV select HAS_IOPORT if MMU select HAVE_ALIGNED_STRUCT_PAGE select HAVE_ARCH_AUDITSYSCALL + select HAVE_ARCH_BITREVERSE if RISCV_ISA_ZBKB select HAVE_ARCH_HUGE_VMALLOC if HAVE_ARCH_HUGE_VMAP select HAVE_ARCH_HUGE_VMAP if MMU && 64BIT select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL diff --git a/arch/riscv/include/asm/bitrev.h b/arch/riscv/include/asm/bitre= v.h new file mode 100644 index 000000000000..4b9b8d34cc3b --- /dev/null +++ b/arch/riscv/include/asm/bitrev.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __ASM_BITREV_H +#define __ASM_BITREV_H + +#include +#include +#include +#include + +static __always_inline __attribute_const__ u32 __arch_bitrev32(u32 x) +{ + unsigned long result; + + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBKB)) + return generic___bitrev32(x); + + asm volatile( + ".option push\n" + ".option arch,+zbkb\n" + "rev8 %0, %1\n" + "brev8 %0, %0\n" + ".option pop" + : "=3Dr" (result) : "r" ((long)x) + ); + + return result >> (__riscv_xlen - 32); +} + +static __always_inline __attribute_const__ u16 __arch_bitrev16(u16 x) +{ + return __arch_bitrev32(x) >> 16; +} + +static __always_inline __attribute_const__ u8 __arch_bitrev8(u8 x) +{ + unsigned long result; + + if (!riscv_has_extension_likely(RISCV_ISA_EXT_ZBKB)) + return generic___bitrev8(x); + + asm volatile( + ".option push\n" + ".option arch,+zbkb\n" + "brev8 %0, %1\n" + ".option pop" + : "=3Dr" (result) : "r" ((long)x) + ); + + return result; +} +#endif --=20 2.34.1