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charset="utf-8" Add devicetree document for UFS Host Controller StarFive JHB100 SoC. The UFS controller is based on the Synopsys DesignWare UFS controller. Signed-off-by: Minda Chen --- .../devicetree/bindings/ufs/starfive,ufs.yaml | 76 +++++++++++++++++++ MAINTAINERS | 5 ++ 2 files changed, 81 insertions(+) create mode 100644 Documentation/devicetree/bindings/ufs/starfive,ufs.yaml diff --git a/Documentation/devicetree/bindings/ufs/starfive,ufs.yaml b/Docu= mentation/devicetree/bindings/ufs/starfive,ufs.yaml new file mode 100644 index 000000000000..c408973dd0ce --- /dev/null +++ b/Documentation/devicetree/bindings/ufs/starfive,ufs.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ufs/starfive,ufs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Starfive Universal Flash Storage (UFS) Controller + +maintainers: + - Minda Chen + +allOf: + - $ref: ufs-common.yaml + +properties: + compatible: + const: starfive,jhb100-ufs + + reg: + maxItems: 1 + + clocks: + items: + - description: UFS reference clock + - description: UFS main enable clock + + clock-names: + items: + - const: ref_clk + - const: ufs + + resets: + items: + - description: UFS main reset + - description: UFS PHY reset + + reset-names: + items: + - const: main + - const: phy + + interrupts: + maxItems: 1 + + starfive,syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + The phandle to System Register Controller syscon node. + +required: + - compatible + - reg + - clocks + - resets + - reset-names + - interrupts + - starfive,syscon + +unevaluatedProperties: false + +examples: + - | + ufs@11b10000 { + compatible =3D "starfive,jhb100-ufs"; + reg =3D <0x11b10000 0x20000>; + interrupts =3D <105>; + clocks =3D <&syscrg 4>, + <&syscrg 5>; + clock-names =3D "ref_clk", "ufs"; + freq-table-hz =3D <26000000 26000000>, + <100000000 100000000>; + resets =3D <&syscrg 10>, + <&syscrg 7>; + reset-names =3D "main", "phy"; + starfive,syscon =3D <&syscon>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 32bd94a0b94c..3792c51da63c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27190,6 +27190,11 @@ L: linux-scsi@vger.kernel.org S: Maintained F: drivers/ufs/host/ufs-renesas.c =20 +UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER STARFIVE +M: Minda Chen +S: Maintained +F: Documentation/devicetree/bindings/ufs/starfive,ufs.yaml + UNIWILL LAPTOP DRIVER M: Armin Wolf L: platform-driver-x86@vger.kernel.org --=20 2.17.1 From nobody Wed Jun 17 01:32:58 2026 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2112.outbound.protection.partner.outlook.cn [139.219.17.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A6863A4F36; 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Petersen" , Pedro Sousa , Arnd Bergmann , AngeloGioacchino Del Regno , Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-scsi@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Minda Chen Subject: [PATCH v1 2/3] scsi: ufs: dwc: Rename amd-versal2 read/write PHY API and move to dwc common file Date: Tue, 21 Apr 2026 17:12:14 +0800 Message-Id: <20260421091215.120632-3-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260421091215.120632-1-minda.chen@starfivetech.com> References: <20260421091215.120632-1-minda.chen@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0030.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:c::18) To BJXPR01MB0855.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:18::12) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BJXPR01MB0855:EE_|BJXPR01MB0519:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ca94f7e-1005-49cc-f524-08de9f861b8e X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|376014|52116014|921020|56012099003|18002099003|22082099003|38350700014; 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charset="utf-8" AMD versal2 UFS using designware ufs mipi PHY. The read/write PHY register API are common functions for designware ufs PHY. For other vendors reuse the code, move to common ufshcd-dwc.c file. Signed-off-by: Minda Chen --- drivers/ufs/host/ufs-amd-versal2.c | 85 ++++++------------------------ drivers/ufs/host/ufshcd-dwc.c | 53 +++++++++++++++++++ drivers/ufs/host/ufshcd-dwc.h | 2 + 3 files changed, 72 insertions(+), 68 deletions(-) diff --git a/drivers/ufs/host/ufs-amd-versal2.c b/drivers/ufs/host/ufs-amd-= versal2.c index 6c454ae8a9c8..0727b5e58be6 100644 --- a/drivers/ufs/host/ufs-amd-versal2.c +++ b/drivers/ufs/host/ufs-amd-versal2.c @@ -43,57 +43,6 @@ struct ufs_versal2_host { u8 ctlecompval1; }; =20 -static int ufs_versal2_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 va= l) -{ - static struct ufshcd_dme_attr_val phy_write_attrs[] =3D { - { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGWRLSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGWRMSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL }, - { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } - }; - - phy_write_attrs[0].mib_val =3D (u8)addr; - phy_write_attrs[1].mib_val =3D (u8)(addr >> 8); - phy_write_attrs[2].mib_val =3D (u8)val; - phy_write_attrs[3].mib_val =3D (u8)(val >> 8); - - return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs, ARRAY_SIZE(phy_writ= e_attrs)); -} - -static int ufs_versal2_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *va= l) -{ - u32 mib_val; - int ret; - static struct ufshcd_dme_attr_val phy_read_attrs[] =3D { - { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, - { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL }, - { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } - }; - - phy_read_attrs[0].mib_val =3D (u8)addr; - phy_read_attrs[1].mib_val =3D (u8)(addr >> 8); - - ret =3D ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs, ARRAY_SIZE(phy_read= _attrs)); - if (ret) - return ret; - - ret =3D ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val); - if (ret) - return ret; - - *val =3D mib_val; - ret =3D ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val); - if (ret) - return ret; - - *val |=3D (mib_val << 8); - - return 0; -} - static int ufs_versal2_enable_phy(struct ufs_hba *hba) { u32 offset, reg; @@ -162,64 +111,64 @@ static int ufs_versal2_setup_phy(struct ufs_hba *hba) u32 reg; =20 /* Bypass RX-AFE offset calibrations (ATT/CTLE) */ - ret =3D ufs_versal2_phy_reg_read(hba, FAST_FLAGS(0), ®); + ret =3D ufs_dwc_phy_reg_read(hba, FAST_FLAGS(0), ®); if (ret) return ret; =20 reg |=3D MPHY_FAST_RX_AFE_CAL; - ret =3D ufs_versal2_phy_reg_write(hba, FAST_FLAGS(0), reg); + ret =3D ufs_dwc_phy_reg_write(hba, FAST_FLAGS(0), reg); if (ret) return ret; =20 - ret =3D ufs_versal2_phy_reg_read(hba, FAST_FLAGS(1), ®); + ret =3D ufs_dwc_phy_reg_read(hba, FAST_FLAGS(1), ®); if (ret) return ret; =20 reg |=3D MPHY_FAST_RX_AFE_CAL; - ret =3D ufs_versal2_phy_reg_write(hba, FAST_FLAGS(1), reg); + ret =3D ufs_dwc_phy_reg_write(hba, FAST_FLAGS(1), reg); if (ret) return ret; =20 /* Program ATT and CTLE compensation values */ if (host->attcompval0) { - ret =3D ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcomp= val0); + ret =3D ufs_dwc_phy_reg_write(hba, RX_AFE_ATT_IDAC(0), host->attcompval0= ); if (ret) return ret; } =20 if (host->attcompval1) { - ret =3D ufs_versal2_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcomp= val1); + ret =3D ufs_dwc_phy_reg_write(hba, RX_AFE_ATT_IDAC(1), host->attcompval1= ); if (ret) return ret; } =20 if (host->ctlecompval0) { - ret =3D ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctleco= mpval0); + ret =3D ufs_dwc_phy_reg_write(hba, RX_AFE_CTLE_IDAC(0), host->ctlecompva= l0); if (ret) return ret; } =20 if (host->ctlecompval1) { - ret =3D ufs_versal2_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctleco= mpval1); + ret =3D ufs_dwc_phy_reg_write(hba, RX_AFE_CTLE_IDAC(1), host->ctlecompva= l1); if (ret) return ret; } =20 - ret =3D ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(0), ®); + ret =3D ufs_dwc_phy_reg_read(hba, FW_CALIB_CCFG(0), ®); if (ret) return ret; =20 reg |=3D MPHY_FW_CALIB_CFG_VAL; - ret =3D ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(0), reg); + ret =3D ufs_dwc_phy_reg_write(hba, FW_CALIB_CCFG(0), reg); if (ret) return ret; =20 - ret =3D ufs_versal2_phy_reg_read(hba, FW_CALIB_CCFG(1), ®); + ret =3D ufs_dwc_phy_reg_read(hba, FW_CALIB_CCFG(1), ®); if (ret) return ret; =20 reg |=3D MPHY_FW_CALIB_CFG_VAL; - return ufs_versal2_phy_reg_write(hba, FW_CALIB_CCFG(1), reg); + return ufs_dwc_phy_reg_write(hba, FW_CALIB_CCFG(1), reg); } =20 static int ufs_versal2_phy_init(struct ufs_hba *hba) @@ -406,7 +355,7 @@ static int ufs_versal2_phy_ratesel(struct ufs_hba *hba,= u32 activelanes, u32 rx_ =20 for (lane =3D 0; lane < activelanes; lane++) { time_left =3D TIMEOUT_MICROSEC; - ret =3D ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); + ret =3D ufs_dwc_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); if (ret) return ret; =20 @@ -416,12 +365,12 @@ static int ufs_versal2_phy_ratesel(struct ufs_hba *hb= a, u32 activelanes, u32 rx_ else reg &=3D ~MPHY_RX_OVRD_VAL; =20 - ret =3D ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); + ret =3D ufs_dwc_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); if (ret) return ret; =20 do { - ret =3D ufs_versal2_phy_reg_read(hba, RX_PCS_OUT(lane), ®); + ret =3D ufs_dwc_phy_reg_read(hba, RX_PCS_OUT(lane), ®); if (ret) return ret; =20 @@ -486,12 +435,12 @@ static int ufs_versal2_pwr_change_notify(struct ufs_h= ba *hba, enum ufs_notify_ch =20 /* Remove rx_req override */ for (lane =3D 0; lane < dev_req_params->lane_tx; lane++) { - ret =3D ufs_versal2_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); + ret =3D ufs_dwc_phy_reg_read(hba, RX_OVRD_IN_1(lane), ®); if (ret) return ret; =20 reg &=3D ~MPHY_RX_OVRD_EN; - ret =3D ufs_versal2_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); + ret =3D ufs_dwc_phy_reg_write(hba, RX_OVRD_IN_1(lane), reg); if (ret) return ret; } diff --git a/drivers/ufs/host/ufshcd-dwc.c b/drivers/ufs/host/ufshcd-dwc.c index 21b1cf912dcc..b057a78e151c 100644 --- a/drivers/ufs/host/ufshcd-dwc.c +++ b/drivers/ufs/host/ufshcd-dwc.c @@ -15,6 +15,59 @@ #include "ufshcd-dwc.h" #include "ufshci-dwc.h" =20 +int ufs_dwc_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val) +{ + static struct ufshcd_dme_attr_val phy_write_attrs[] =3D { + { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGWRLSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGWRMSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGRDWRSEL), 1, DME_LOCAL }, + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } + }; + + phy_write_attrs[0].mib_val =3D (u8)addr; + phy_write_attrs[1].mib_val =3D (u8)(addr >> 8); + phy_write_attrs[2].mib_val =3D (u8)val; + phy_write_attrs[3].mib_val =3D (u8)(val >> 8); + + return ufshcd_dwc_dme_set_attrs(hba, phy_write_attrs, ARRAY_SIZE(phy_writ= e_attrs)); +} +EXPORT_SYMBOL(ufs_dwc_phy_reg_write); + +int ufs_dwc_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val) +{ + u32 mib_val; + int ret; + static struct ufshcd_dme_attr_val phy_read_attrs[] =3D { + { UIC_ARG_MIB(CBCREGADDRLSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGADDRMSB), 0, DME_LOCAL }, + { UIC_ARG_MIB(CBCREGRDWRSEL), 0, DME_LOCAL }, + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 1, DME_LOCAL } + }; + + phy_read_attrs[0].mib_val =3D (u8)addr; + phy_read_attrs[1].mib_val =3D (u8)(addr >> 8); + + ret =3D ufshcd_dwc_dme_set_attrs(hba, phy_read_attrs, ARRAY_SIZE(phy_read= _attrs)); + if (ret) + return ret; + + ret =3D ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDLSB), &mib_val); + if (ret) + return ret; + + *val =3D mib_val; + ret =3D ufshcd_dme_get(hba, UIC_ARG_MIB(CBCREGRDMSB), &mib_val); + if (ret) + return ret; + + *val |=3D (mib_val << 8); + + return 0; +} +EXPORT_SYMBOL(ufs_dwc_phy_reg_read); + int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba, const struct ufshcd_dme_attr_val *v, int n) { diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h index c618bb914904..8091f186a9b3 100644 --- a/drivers/ufs/host/ufshcd-dwc.h +++ b/drivers/ufs/host/ufshcd-dwc.h @@ -68,4 +68,6 @@ int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba, enum ufs_notify_change_status status); int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba, const struct ufshcd_dme_attr_val *v, int n); +int ufs_dwc_phy_reg_write(struct ufs_hba *hba, u32 addr, u32 val); +int ufs_dwc_phy_reg_read(struct ufs_hba *hba, u32 addr, u32 *val); #endif /* End of Header */ --=20 2.17.1 From nobody Wed Jun 17 01:32:58 2026 Received: from CHN02-BJS-obe.outbound.protection.partner.outlook.cn (mail-bjschn02on2112.outbound.protection.partner.outlook.cn [139.219.17.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C73D33A451F; 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J . Bottomley" , "Martin K . Petersen" , Pedro Sousa , Arnd Bergmann , AngeloGioacchino Del Regno , Conor Dooley , Rob Herring , Krzysztof Kozlowski , linux-scsi@vger.kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Minda Chen Subject: [PATCH v1 3/3] scsi: ufs: starfive: Add UFS support for StarFive JHB100 SoC Date: Tue, 21 Apr 2026 17:12:15 +0800 Message-Id: <20260421091215.120632-4-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20260421091215.120632-1-minda.chen@starfivetech.com> References: <20260421091215.120632-1-minda.chen@starfivetech.com> X-ClientProxiedBy: NT0PR01CA0030.CHNPR01.prod.partner.outlook.cn (2406:e500:c510:c::18) To BJXPR01MB0855.CHNPR01.prod.partner.outlook.cn (2406:e500:c211:18::12) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BJXPR01MB0855:EE_|BJXPR01MB0519:EE_ X-MS-Office365-Filtering-Correlation-Id: 4ae20e48-3052-4265-0165-08de9f861c5b X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|376014|52116014|921020|56012099003|18002099003|22082099003|38350700014; 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charset="utf-8" Add support for the UFS host controller on JHB100 SoC, built on the Synopsys DWC UFS controller and using UFSHCD platform driver. This controller requires specific configurations like M-PHY/RMMI/UniPro Signed-off-by: Minda Chen --- MAINTAINERS | 1 + drivers/ufs/host/Kconfig | 13 ++ drivers/ufs/host/Makefile | 1 + drivers/ufs/host/ufs-starfive.c | 279 ++++++++++++++++++++++++++++++++ drivers/ufs/host/ufshcd-dwc.h | 17 ++ 5 files changed, 311 insertions(+) create mode 100644 drivers/ufs/host/ufs-starfive.c diff --git a/MAINTAINERS b/MAINTAINERS index 3792c51da63c..658f65c78482 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -27194,6 +27194,7 @@ UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER STAR= FIVE M: Minda Chen S: Maintained F: Documentation/devicetree/bindings/ufs/starfive,ufs.yaml +F: drivers/ufs/host/ufs-starfive.c =20 UNIWILL LAPTOP DRIVER M: Armin Wolf diff --git a/drivers/ufs/host/Kconfig b/drivers/ufs/host/Kconfig index 964ae70e7390..b742f7a2b0b6 100644 --- a/drivers/ufs/host/Kconfig +++ b/drivers/ufs/host/Kconfig @@ -168,3 +168,16 @@ config SCSI_UFS_AMD_VERSAL2 =20 Select this if you have UFS controller on AMD Versal Gen 2 SoC. If unsure, say N. + +config SCSI_UFS_STARFIVE + tristate "Starfive UFS controller platform driver" + depends on OF && SCSI_UFSHCD_PLATFORM + depends on ARCH_STARFIVE || COMPILE_TEST + help + This selects the StarFive specific additions to UFSHCD platform driver. + UFS host on StarFive needs some vendor specific configuration before + accessing the hardware which includes PHY configuration and vendor + specific registers. + + Select this if you have UFS controller on StarFive chipset. + If unsure, say N. diff --git a/drivers/ufs/host/Makefile b/drivers/ufs/host/Makefile index 65d8bb23ab7b..adfee2ae3b48 100644 --- a/drivers/ufs/host/Makefile +++ b/drivers/ufs/host/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_SCSI_UFS_ROCKCHIP) +=3D ufs-rockchip.o obj-$(CONFIG_SCSI_UFS_SPRD) +=3D ufs-sprd.o obj-$(CONFIG_SCSI_UFS_TI_J721E) +=3D ti-j721e-ufs.o obj-$(CONFIG_SCSI_UFS_AMD_VERSAL2) +=3D ufs-amd-versal2.o ufshcd-dwc.o +obj-$(CONFIG_SCSI_UFS_STARFIVE) +=3D ufs-starfive.o ufshcd-dwc.o diff --git a/drivers/ufs/host/ufs-starfive.c b/drivers/ufs/host/ufs-starfiv= e.c new file mode 100644 index 000000000000..cdd5f9264cdb --- /dev/null +++ b/drivers/ufs/host/ufs-starfive.c @@ -0,0 +1,279 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Starfive UFS host platform driver + * + * Copyright (C) 2026 Starfive, Inc. + * + * Authors: Minda Chen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ufshcd-pltfrm.h" +#include "ufshcd-dwc.h" +#include "ufshci-dwc.h" + +struct ufs_starfive_host { + struct ufs_hba *hba; + struct regmap *syscon; + struct reset_control *core_reset; + struct reset_control *phy_reset; + struct clk *ufs_clk; +}; + +#define SRAM_STATUS 0x38 +#define SRAM_EXT_LD_DONE BIT(1) +#define SRAM_INIT_DONE BIT(2) +#define UFS_REFCLK 0x3c +#define REFCLK_OEN BIT(8) +#define RESET_I BIT(9) +#define RESET_OEN BIT(10) + +#define MPHY_POLL_INTERVAL_US 100 +#define MPHY_POLL_TIMEOUT_US 10000 + +static int ufs_starfive_phy_config(struct ufs_hba *hba, struct ufs_starfiv= e_host *host) +{ + static struct ufs_dwc_phy_pair_data phy_data[] =3D { + { MPLL_SKIPCAL_COARSE_TUNE, 0}, + { RX_AFE_ATT_IDAC(0), 0x8a}, + { RX_AFE_ATT_IDAC(1), 0xc2}, + { RX_AFE_CTLE_IDAC(0), 0x8e}, + { RX_AFE_CTLE_IDAC(1), 0x8b}, + { FAST_FLAGS(0), 0x0004 }, + { FAST_FLAGS(1), 0x0004 }, + { RX_ADAPT_DFE(0), 0xa00}, + { RX_ADAPT_DFE(1), 0xa00}, + }; + struct ufs_dwc_phy_pair_data *data; + int ret, i; + + for (i =3D 0; i < ARRAY_SIZE(phy_data); i++) { + data =3D &phy_data[i]; + ret =3D ufs_dwc_phy_reg_write(hba, data->addr, data->value); + if (ret) + return ret; + } + + ret =3D ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYDISABLE), 0); + if (ret) + return ret; + + ret =3D ufshcd_dme_set(hba, UIC_ARG_MIB(VS_MPHYCFGUPDT), 1); + if (ret) + return ret; + + return 0; +} + +static int ufs_starfive_phy_init(struct ufs_hba *hba) +{ + struct ufs_starfive_host *host =3D ufshcd_get_variant(hba); + static struct ufshcd_dme_attr_val rmmi_config[] =3D { + { UIC_ARG_MIB(CBRATESEL), 0x1, + DME_LOCAL }, + { UIC_ARG_MIB(CBREFCLKCTRL2), CBREFREFCLK_GATE_OVR_EN, + DME_LOCAL }, + { UIC_ARG_MIB_SEL(RXSQCONTROL, SELIND_LN0_RX), 0x01, + DME_LOCAL }, + { UIC_ARG_MIB_SEL(RXRHOLDCTRLOPT, SELIND_LN0_RX), 0x02, + DME_LOCAL }, + { UIC_ARG_MIB_SEL(RXSQCONTROL, SELIND_LN1_RX), 0x01, + DME_LOCAL }, + { UIC_ARG_MIB_SEL(RXRHOLDCTRLOPT, SELIND_LN1_RX), 0x02, + DME_LOCAL }, + { UIC_ARG_MIB(EXT_COARSE_TUNE_RATEA), 0x25, + DME_LOCAL }, + { UIC_ARG_MIB(EXT_COARSE_TUNE_RATEB), 0x51, + DME_LOCAL }, + { UIC_ARG_MIB(CBCRCTRL), 0x01, DME_LOCAL }, + { UIC_ARG_MIB(VS_MPHYCFGUPDT), 0x1, + DME_LOCAL }, + }; + int ret, val; + + ret =3D ufshcd_dwc_dme_set_attrs(hba, rmmi_config, + ARRAY_SIZE(rmmi_config)); + if (ret) { + dev_err(hba->dev, "set rmmi config failed\n"); + return ret; + } + + ret =3D reset_control_deassert(host->phy_reset); + if (ret) { + dev_err(hba->dev, "Failed to reset phy\n"); + return ret; + } + + ret =3D regmap_read_poll_timeout(host->syscon, + SRAM_STATUS, val, + (val & SRAM_INIT_DONE), + MPHY_POLL_INTERVAL_US, + MPHY_POLL_TIMEOUT_US); + if (ret) { + dev_err(hba->dev, "wait sram init done timeout\n"); + return ret; + } + + regmap_update_bits(host->syscon, SRAM_STATUS, + SRAM_EXT_LD_DONE, SRAM_EXT_LD_DONE); + + ret =3D ufs_starfive_phy_config(hba, host); + if (ret) { + dev_err(hba->dev, "configure phy failed\n"); + return ret; + } + + return 0; +} + +static int ufs_starfive_init(struct ufs_hba *hba) +{ + struct ufs_starfive_host *host; + struct device *dev =3D hba->dev; + struct platform_device *pdev; + int ret; + + pdev =3D container_of(dev, struct platform_device, dev); + host =3D devm_kzalloc(dev, sizeof(*host), GFP_KERNEL); + if (!host) + return dev_err_probe(dev, -ENOMEM, + "no memory for starfive ufs host\n"); + + host->syscon =3D syscon_regmap_lookup_by_phandle(dev->of_node, + "starfive,syscon"); + + if (IS_ERR(host->syscon)) + return dev_err_probe(dev, PTR_ERR(host->syscon), "getting the regmap fai= led\n"); + + host->core_reset =3D devm_reset_control_get_exclusive(hba->dev, "main"); + if (IS_ERR(host->core_reset)) + return dev_err_probe(dev, PTR_ERR(host->core_reset), + "Failed to get core clock resets"); + + host->phy_reset =3D devm_reset_control_get_exclusive(hba->dev, "phy"); + if (IS_ERR(host->phy_reset)) + return dev_err_probe(dev, PTR_ERR(host->phy_reset), + "Failed to get phy clk reset\n"); + + host->ufs_clk =3D devm_clk_get_enabled(&pdev->dev, "ufs"); + if (IS_ERR(host->ufs_clk)) + return dev_err_probe(dev, PTR_ERR(host->ufs_clk), + "Failed to get ufs clock\n"); + + regmap_update_bits(host->syscon, UFS_REFCLK, + REFCLK_OEN | RESET_OEN, 0); + usleep_range(2, 3); + regmap_update_bits(host->syscon, UFS_REFCLK, RESET_I, RESET_I); + + ret =3D reset_control_deassert(host->core_reset); + if (ret) + return dev_err_probe(dev, ret, + "Failed to reset core clock"); + + host->hba =3D hba; + ufshcd_set_variant(hba, host); + hba->caps |=3D UFSHCD_CAP_WB_EN; + + return 0; +} + +static int ufs_starfive_link_startup_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + int ret; + + if (status =3D=3D PRE_CHANGE) { + ret =3D ufshcd_vops_phy_initialization(hba); + if (ret) { + dev_err(hba->dev, "Phy setup failed (%d)\n", ret); + return ret; + } + } else { /* POST_CHANGE */ + return ufshcd_dwc_link_startup_notify(hba, status); + } + + return 0; +} + +static int ufs_starfive_hce_enable_notify(struct ufs_hba *hba, + enum ufs_notify_change_status status) +{ + u32 val; + + if (status !=3D POST_CHANGE) + return 0; + + /* Disable Gating clock. Auto hibernation quirk */ + val =3D ufshcd_readl(hba, REG_BUSTHRTL); + val &=3D ~(LP_AH8_POWER_GATING_EN + | LP_POWER_GATING_EN + | CLK_GATING_EN); + ufshcd_writel(hba, val, REG_BUSTHRTL); + + return 0; +} + +static struct ufs_hba_variant_ops ufs_hba_vops =3D { + .name =3D "ufs_starfive_platform", + .init =3D ufs_starfive_init, + .link_startup_notify =3D ufs_starfive_link_startup_notify, + .phy_initialization =3D ufs_starfive_phy_init, + .hce_enable_notify =3D ufs_starfive_hce_enable_notify, +}; + +static int ufs_starfive_probe(struct platform_device *pdev) +{ + int err; + + /* Perform generic probe */ + err =3D ufshcd_pltfrm_init(pdev, &ufs_hba_vops); + if (err) + dev_err(&pdev->dev, "ufshcd_pltfrm_init() failed %d\n", err); + + return err; +} + +static void ufs_starfive_remove(struct platform_device *pdev) +{ + struct ufs_hba *hba =3D platform_get_drvdata(pdev); + + pm_runtime_get_sync(&(pdev)->dev); + ufshcd_remove(hba); +} + +static const struct dev_pm_ops ufs_starfive_pm_ops =3D { + SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume) + SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) +}; + +static const struct of_device_id ufs_starfive_pltfm_match[] =3D { + { .compatible =3D "starfive,jhb100-ufs", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ufs_starfive_pltfm_match); + +static struct platform_driver ufs_starfive_driver =3D { + .probe =3D ufs_starfive_probe, + .remove =3D ufs_starfive_remove, + .driver =3D { + .name =3D "ufs-starfive", + .pm =3D &ufs_starfive_pm_ops, + .of_match_table =3D of_match_ptr(ufs_starfive_pltfm_match), + }, +}; + +module_platform_driver(ufs_starfive_driver); + +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:ufs-starfive"); +MODULE_DESCRIPTION("Starfive UFS host platform glue driver"); diff --git a/drivers/ufs/host/ufshcd-dwc.h b/drivers/ufs/host/ufshcd-dwc.h index 8091f186a9b3..ab8728f92b22 100644 --- a/drivers/ufs/host/ufshcd-dwc.h +++ b/drivers/ufs/host/ufshcd-dwc.h @@ -12,7 +12,15 @@ =20 #include =20 +/* ufshcd vendor specific register */ +#define REG_BUSTHRTL 0xc0 +#define LP_AH8_POWER_GATING_EN BIT(17) +#define LP_POWER_GATING_EN BIT(16) +#define CLK_GATING_EN BIT(12) + /* RMMI Attributes */ +#define RXSQCONTROL 0x8009 +#define RXRHOLDCTRLOPT 0x8013 #define CBREFCLKCTRL2 0x8132 #define CBCRCTRL 0x811F #define CBC10DIRECTCONF2 0x810E @@ -24,6 +32,8 @@ #define CBCREGRDLSB 0x811A #define CBCREGRDMSB 0x811B #define CBCREGRDWRSEL 0x811C +#define EXT_COARSE_TUNE_RATEA 0x814D +#define EXT_COARSE_TUNE_RATEB 0x814E =20 #define CBREFREFCLK_GATE_OVR_EN BIT(7) =20 @@ -32,9 +42,11 @@ #define MRX_FSM_STATE 0xC1 =20 /* M-PHY registers */ +#define MPLL_SKIPCAL_COARSE_TUNE 0x28 #define RX_OVRD_IN_1(n) (0x3006 + ((n) * 0x100)) #define RX_PCS_OUT(n) (0x300F + ((n) * 0x100)) #define FAST_FLAGS(n) (0x401C + ((n) * 0x100)) +#define RX_ADAPT_DFE(n) (0x401E + ((n) * 0x100)) #define RX_AFE_ATT_IDAC(n) (0x4000 + ((n) * 0x100)) #define RX_AFE_CTLE_IDAC(n) (0x4001 + ((n) * 0x100)) #define FW_CALIB_CCFG(n) (0x404D + ((n) * 0x100)) @@ -64,6 +76,11 @@ struct ufshcd_dme_attr_val { u8 peer; }; =20 +struct ufs_dwc_phy_pair_data { + u32 addr; + u32 value; +}; + int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba, enum ufs_notify_change_status status); int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba, --=20 2.17.1