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The port number is crucial for the CTCU device to identify which ETR it serves. With the port number we can correctly get required parameters of the CTCU device in TMC module. Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-core.c | 24 +++++++++++++++++++= ++++ drivers/hwtracing/coresight/coresight-ctcu-core.c | 19 +----------------- drivers/hwtracing/coresight/coresight-priv.h | 2 ++ 3 files changed, 27 insertions(+), 18 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 46f247f73cf6..221de57ca57b 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -588,6 +588,30 @@ struct coresight_device *coresight_get_sink(struct cor= esight_path *path) } EXPORT_SYMBOL_GPL(coresight_get_sink); =20 +/** + * coresight_get_in_port: Find the input port number at @remote where the = @csdev + * device is connected to. + * + * @csdev: csdev of the device. + * @remote: csdev of the remote device which is connected to @csdev. + * + * Return: port number upon success or -EINVAL for fail. + */ +int coresight_get_in_port(struct coresight_device *csdev, + struct coresight_device *remote) +{ + struct coresight_platform_data *pdata =3D remote->pdata; + int i; + + for (i =3D 0; i < pdata->nr_inconns; ++i) { + if (pdata->in_conns[i]->src_dev =3D=3D csdev) + return pdata->in_conns[i]->dest_port; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(coresight_get_in_port); + u32 coresight_get_sink_id(struct coresight_device *csdev) { if (!csdev->ea) diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index 9043cad42f01..e8720026c9e3 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -116,23 +116,6 @@ static int __ctcu_set_etr_traceid(struct coresight_dev= ice *csdev, u8 traceid, in return 0; } =20 -/* - * Searching the sink device from helper's view in case there are multiple= helper devices - * connected to the sink device. - */ -static int ctcu_get_active_port(struct coresight_device *sink, struct core= sight_device *helper) -{ - struct coresight_platform_data *pdata =3D helper->pdata; - int i; - - for (i =3D 0; i < pdata->nr_inconns; ++i) { - if (pdata->in_conns[i]->src_dev =3D=3D sink) - return pdata->in_conns[i]->dest_port; - } - - return -EINVAL; -} - static int ctcu_set_etr_traceid(struct coresight_device *csdev, struct cor= esight_path *path, bool enable) { @@ -145,7 +128,7 @@ static int ctcu_set_etr_traceid(struct coresight_device= *csdev, struct coresight return -EINVAL; } =20 - port_num =3D ctcu_get_active_port(sink, csdev); + port_num =3D coresight_get_in_port(sink, csdev); if (port_num < 0) return -EINVAL; =20 diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index 1ea882dffd70..5532ec82e82c 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -155,6 +155,8 @@ void coresight_remove_links(struct coresight_device *or= ig, u32 coresight_get_sink_id(struct coresight_device *csdev); void coresight_path_assign_trace_id(struct coresight_path *path, enum cs_mode mode); +int coresight_get_in_port(struct coresight_device *csdev, + struct coresight_device *remote); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f8e982fd3sm17077339b3a.10.2026.04.21.03.56.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2026 03:56:32 -0700 (PDT) From: Jie Gan Date: Tue, 21 Apr 2026 18:55:51 +0800 Subject: [PATCH v17 2/7] coresight: tmc: add create/clean functions for etr_buf_list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260421-enable-byte-cntr-for-ctcu-v17-2-9cf36ff55fc0@oss.qualcomm.com> References: <20260421-enable-byte-cntr-for-ctcu-v17-0-9cf36ff55fc0@oss.qualcomm.com> In-Reply-To: <20260421-enable-byte-cntr-for-ctcu-v17-0-9cf36ff55fc0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan , Mike Leach X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776768975; l=6212; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=Pfl2LKxPOQb/ac7N9QZFTXlGhGaac/cCYyoTMz4qpIo=; b=DgDOejqKQhCI2nwimlAlmoNygLDk2TZVQ29ul84szOehWNh96uLe+mHzGpAcgz5HP0r4TksCu /bm0DZ7g1uDC6NaKIk1GMN8vB2kMPqEdGI/CdBi6njNx9wEMhQbUrCz X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIxMDEwOCBTYWx0ZWRfX4HjaTtC54+NI 5f8YrON54mgZ5DBdvOzZVPbWMsFMFeHsHRS6MBY3fruYNWOgN27bmSW7fVH5NNnID5k2VBgRBnQ Z3Z6Vz9t6lDXF/xENem/w7S5uqp/WgRlq7BenMO/9fKqK59+lSFt3XlK7zMgYBEgVESsN5usFOo oKH1tnD6r2Sbh7KJDUCSe2udhajYCDvf9TYi71qRE7GYYoNK4an9YO3IyUzla9NzfxDCwXjP6I1 1VvukvK1xAMrHqLKNAm8x4MkJwzW/she8/ogWJTjDR42sR7emvjZRPvYQw0Ss0WIAQtVdciiQUO /VC65KgWMPmVT95yBOihDqSNCP3prf/1bdfdP20VxycN7XoviVvS3lRVuci15TICFbm7vHn9Fm7 oT5it+mIj2gTTHxYKrXAk0hpjX8iSCvlK9eEK8aDx7gdgAVGAQpSKLx8dK29rGJ0LFJ4TLeWC9b 6WeomPbTwOMEDchrSdg== X-Proofpoint-ORIG-GUID: T1p8uJfj2pF4Byhp1qksh5xKnrnxonIZ X-Authority-Analysis: v=2.4 cv=YOSvDxGx c=1 sm=1 tr=0 ts=69e757e3 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=AScg1gZdVb1XvqdcXssA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-GUID: T1p8uJfj2pF4Byhp1qksh5xKnrnxonIZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-21_02,2026-04-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 bulkscore=0 adultscore=0 clxscore=1015 spamscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604210108 Introduce functions for creating and inserting or removing the etr_buf_node to/from the etr_buf_list. The byte-cntr functionality requires two etr_buf to receive trace data. The active etr_buf collects the trace data from source device, while the byte-cntr reading function accesses the deactivated etr_buf after is has been filled and synced, transferring data to the userspace. Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-tmc-core.c | 1 + drivers/hwtracing/coresight/coresight-tmc-etr.c | 99 ++++++++++++++++++++= ++++ drivers/hwtracing/coresight/coresight-tmc.h | 17 ++++ 3 files changed, 117 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index c89fe996af23..bac3278ef4dd 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -835,6 +835,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) idr_init(&drvdata->idr); mutex_init(&drvdata->idr_mutex); dev_list =3D "tmc_etr"; + INIT_LIST_HEAD(&drvdata->etr_buf_list); break; case TMC_CONFIG_TYPE_ETF: desc.groups =3D coresight_etf_groups; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 4dc1defe27a5..ac704617097c 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1918,6 +1918,105 @@ const struct coresight_ops tmc_etr_cs_ops =3D { .panic_ops =3D &tmc_etr_sync_ops, }; =20 +/** + * tmc_clean_etr_buf_list - clean the etr_buf_list. + * @drvdata: driver data of the TMC device. + * + * Remove unused buffers from @drvdata->etr_buf_list and free them. + */ +void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata) +{ + struct etr_buf_node *nd, *next; + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, link) { + if (nd->sysfs_buf =3D=3D drvdata->sysfs_buf) { + if (coresight_get_mode(drvdata->csdev) !=3D CS_MODE_DISABLED) { + /* + * Dont free the sysfs_buf, just remove it from the list. + * drvdata->sysfs_buf will hold the buffer and free it later. + */ + nd->sysfs_buf =3D NULL; + list_del(&nd->link); + kfree(nd); + continue; + } + /* Free the sysfs_buf in coming steps through nd->sysfs_buf */ + drvdata->sysfs_buf =3D NULL; + } + /* Free allocated buffers which are not utilized by ETR */ + tmc_etr_free_sysfs_buf(nd->sysfs_buf); + nd->sysfs_buf =3D NULL; + list_del(&nd->link); + kfree(nd); + } +} +EXPORT_SYMBOL_GPL(tmc_clean_etr_buf_list); + +/** + * tmc_create_etr_buf_list - create a list to manage the etr_buf_node. + * @drvdata: driver data of the TMC device. + * @num_nodes: number of nodes want to create with the list. + * + * Return 0 upon success and return the error number if fail. + */ +int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes) +{ + struct etr_buf_node *new_node; + struct etr_buf *sysfs_buf; + int i =3D 0, ret =3D 0; + + /* We dont need a list if there is only one node */ + if (num_nodes < 2) + return -EINVAL; + + /* We expect that sysfs_buf in drvdata has already been allocated. */ + if (drvdata->sysfs_buf) { + /* Directly insert the allocated sysfs_buf into the list first */ + new_node =3D kzalloc_obj(*new_node, GFP_KERNEL); + if (!new_node) + return -ENOMEM; + + new_node->sysfs_buf =3D drvdata->sysfs_buf; + new_node->is_free =3D false; + list_add(&new_node->link, &drvdata->etr_buf_list); + i++; + } + + while (i < num_nodes) { + new_node =3D kzalloc_obj(*new_node, GFP_KERNEL); + if (!new_node) { + ret =3D -ENOMEM; + break; + } + + sysfs_buf =3D tmc_alloc_etr_buf(drvdata, drvdata->size, 0, cpu_to_node(0= ), NULL); + if (!sysfs_buf) { + kfree(new_node); + ret =3D -ENOMEM; + break; + } + + /* We dont have a available sysfs_buf in drvdata, setup one */ + if (!drvdata->sysfs_buf) { + drvdata->sysfs_buf =3D sysfs_buf; + new_node->is_free =3D false; + } else { + new_node->is_free =3D true; + } + + new_node->sysfs_buf =3D sysfs_buf; + list_add_tail(&new_node->link, &drvdata->etr_buf_list); + i++; + } + + /* Clean the list if there is an error */ + if (ret) + tmc_clean_etr_buf_list(drvdata); + + return ret; +} +EXPORT_SYMBOL_GPL(tmc_create_etr_buf_list); + int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) { int ret =3D 0; diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 319a354ede9f..6e994678f926 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -208,6 +208,19 @@ struct tmc_resrv_buf { s64 len; }; =20 +/** + * @sysfs_buf: Allocated sysfs_buf. + * @is_free: Indicates whether the buffer is free to choose. + * @pos: Offset to the start of the buffer. + * @link: list_head of the node. + */ +struct etr_buf_node { + struct etr_buf *sysfs_buf; + bool is_free; + loff_t pos; + struct list_head link; +}; + /** * struct tmc_drvdata - specifics associated to an TMC component * @atclk: optional clock for the core parts of the TMC. @@ -245,6 +258,7 @@ struct tmc_resrv_buf { * (after crash) by default. * @crash_mdata: Reserved memory for storing tmc crash metadata. * Used by ETR/ETF. + * @etr_buf_list: List that is used to manage allocated etr_buf. */ struct tmc_drvdata { struct clk *atclk; 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Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-tmc-core.c | 51 ++++++++++----------= ---- drivers/hwtracing/coresight/coresight-tmc.h | 15 +++++++ 2 files changed, 37 insertions(+), 29 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index bac3278ef4dd..110eedde077f 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -228,17 +228,10 @@ static int tmc_read_prepare(struct tmc_drvdata *drvda= ta) { int ret =3D 0; =20 - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - ret =3D tmc_read_prepare_etb(drvdata); - break; - case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_prepare_etr(drvdata); - break; - default: + if (drvdata->sysfs_ops) + ret =3D drvdata->sysfs_ops->read_prepare(drvdata); + else ret =3D -EINVAL; - } =20 if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read start\n"); @@ -250,17 +243,10 @@ static int tmc_read_unprepare(struct tmc_drvdata *drv= data) { int ret =3D 0; =20 - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - ret =3D tmc_read_unprepare_etb(drvdata); - break; - case TMC_CONFIG_TYPE_ETR: - ret =3D tmc_read_unprepare_etr(drvdata); - break; - default: + if (drvdata->sysfs_ops) + ret =3D drvdata->sysfs_ops->read_unprepare(drvdata); + else ret =3D -EINVAL; - } =20 if (!ret) dev_dbg(&drvdata->csdev->dev, "TMC read end\n"); @@ -287,15 +273,7 @@ static int tmc_open(struct inode *inode, struct file *= file) static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos= , size_t len, char **bufpp) { - switch (drvdata->config_type) { - case TMC_CONFIG_TYPE_ETB: - case TMC_CONFIG_TYPE_ETF: - return tmc_etb_get_sysfs_trace(drvdata, pos, len, bufpp); - case TMC_CONFIG_TYPE_ETR: - return tmc_etr_get_sysfs_trace(drvdata, pos, len, bufpp); - } - - return -EINVAL; + return drvdata->sysfs_ops->get_trace_data(drvdata, pos, len, bufpp); } =20 static ssize_t tmc_read(struct file *file, char __user *data, size_t len, @@ -764,6 +742,18 @@ static void register_crash_dev_interface(struct tmc_dr= vdata *drvdata, "Valid crash tracedata found\n"); } =20 +static const struct tmc_sysfs_ops etb_sysfs_ops =3D { + .read_prepare =3D tmc_read_prepare_etb, + .read_unprepare =3D tmc_read_unprepare_etb, + .get_trace_data =3D tmc_etb_get_sysfs_trace, +}; + +static const struct tmc_sysfs_ops etr_sysfs_ops =3D { + .read_prepare =3D tmc_read_prepare_etr, + .read_unprepare =3D tmc_read_unprepare_etr, + .get_trace_data =3D tmc_etr_get_sysfs_trace, +}; + static int __tmc_probe(struct device *dev, struct resource *res) { int ret =3D 0; @@ -823,6 +813,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) desc.subtype.sink_subtype =3D CORESIGHT_DEV_SUBTYPE_SINK_BUFFER; desc.ops =3D &tmc_etb_cs_ops; dev_list =3D "tmc_etb"; + drvdata->sysfs_ops =3D &etb_sysfs_ops; break; case TMC_CONFIG_TYPE_ETR: desc.groups =3D coresight_etr_groups; @@ -835,6 +826,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) idr_init(&drvdata->idr); mutex_init(&drvdata->idr_mutex); dev_list =3D "tmc_etr"; + drvdata->sysfs_ops =3D &etr_sysfs_ops; INIT_LIST_HEAD(&drvdata->etr_buf_list); break; case TMC_CONFIG_TYPE_ETF: @@ -844,6 +836,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_FIFO; desc.ops =3D &tmc_etf_cs_ops; dev_list =3D "tmc_etf"; + drvdata->sysfs_ops =3D &etb_sysfs_ops; break; default: pr_err("%s: Unsupported TMC config\n", desc.name); diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index 6e994678f926..a14645b04624 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -259,6 +259,7 @@ struct etr_buf_node { * @crash_mdata: Reserved memory for storing tmc crash metadata. * Used by ETR/ETF. * @etr_buf_list: List that is used to manage allocated etr_buf. + * @sysfs_ops: Read operations for the sysfs mode. */ struct tmc_drvdata { struct clk *atclk; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f8e982fd3sm17077339b3a.10.2026.04.21.03.56.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2026 03:56:42 -0700 (PDT) From: Jie Gan Date: Tue, 21 Apr 2026 18:55:53 +0800 Subject: [PATCH v17 4/7] coresight: etr: add a new function to retrieve the CTCU device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260421-enable-byte-cntr-for-ctcu-v17-4-9cf36ff55fc0@oss.qualcomm.com> References: <20260421-enable-byte-cntr-for-ctcu-v17-0-9cf36ff55fc0@oss.qualcomm.com> In-Reply-To: <20260421-enable-byte-cntr-for-ctcu-v17-0-9cf36ff55fc0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776768976; l=2348; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=5Mt5/XsGHOSDEOG0ISFiVsCUEFGP0erIeLzDLMDtZnM=; b=WhXCZV5up4hdp1qBnIeS6UhdzvfhCV2dG1U5NQe17LczbTvQE4hMGeRKNMx/5suR89AWCGg5l q9Y/hhLWvOYARKtSAz+lUS/Arcee3oXJQ8LgYBAzkS91RTI8cIJiIjQ X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIxMDEwOCBTYWx0ZWRfX2UjYNunpVt/E bEsEw2FKDE726EIY0IQdYJ14o5KrwQFl+BIzrub1VP7X9eyw2vuKpeZILs/XCbNn12omA+gcOG0 t9swRyFwlNpRLWVWHLG6rxEufQ5NaQ5bggOXOt/uXUxj5sFJ2L5kOI1qq+Vpa4D+rUHgrMi8iqa cGthircupBKmeujoct9SsLGZ6nmtgbDhVHiYH3xwYqNGilAoisyqC6zNyKwhkQ14HcaJZTp198U H2auYoWfi7VAuf9IythTN7JkAIy0ybKVpe/pfZVLM709Qfy7z1b/qs/Nj5PptPQFjtdJaRetJ6n BotkbB2RtanqA3C8AtRIJXntRc1JaCFCGhNbpl63Gs78ssW86OubobShZR7bVe0BK9IzOWoyuxQ xQutaDBjoUHCuz2BtPkPqw8wnr0mW7tM5MqXkdoXuDqzPUtC2lk7t3Tp/58YZT5Ahz0GFI7VRQC TD8eR6RBXHVvIwYrHFA== X-Proofpoint-ORIG-GUID: _C83SH0qjxUy1D7HwiaERBlFfto3f3q0 X-Authority-Analysis: v=2.4 cv=YOSvDxGx c=1 sm=1 tr=0 ts=69e757ed cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=FuIWbRVyn4pKkvqW11oA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: _C83SH0qjxUy1D7HwiaERBlFfto3f3q0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-21_02,2026-04-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 bulkscore=0 adultscore=0 clxscore=1015 spamscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604210108 Add tmc_etr_get_ctcu_device function to find the ptr of the coresight_device of the CTCU device if the CTCU device is connected to the TMC ETR device. Signed-off-by: Jie Gan --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 24 +++++++++++++++++++++= +++ drivers/hwtracing/coresight/coresight-tmc.h | 1 + 2 files changed, 25 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index ac704617097c..bb76e7e37874 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -865,6 +865,30 @@ tmc_etr_get_catu_device(struct tmc_drvdata *drvdata) } EXPORT_SYMBOL_GPL(tmc_etr_get_catu_device); =20 +/* + * TMC ETR could be connected to a CTCU device, which can provide ATID fil= ter + * and byte-cntr service. This is represented by the output port of the TMC + * (ETR) connected to the input port of the CTCU. + * + * Returns : coresight_device ptr for the CTCU device if a CTCU is found. + * : NULL otherwise. + */ +struct coresight_device * +tmc_etr_get_ctcu_device(struct tmc_drvdata *drvdata) +{ + struct coresight_device *etr =3D drvdata->csdev; + union coresight_dev_subtype ctcu_subtype =3D { + .helper_subtype =3D CORESIGHT_DEV_SUBTYPE_HELPER_CTCU + }; + + if (!IS_ENABLED(CONFIG_CORESIGHT_CTCU)) + return NULL; + + return coresight_find_output_type(etr->pdata, CORESIGHT_DEV_TYPE_HELPER, + ctcu_subtype); +} +EXPORT_SYMBOL_GPL(tmc_etr_get_ctcu_device); + static const struct etr_buf_operations *etr_buf_ops[] =3D { [ETR_MODE_FLAT] =3D &etr_flat_buf_ops, [ETR_MODE_ETR_SG] =3D &etr_sg_buf_ops, diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index a14645b04624..fbb015079872 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -470,6 +470,7 @@ static inline uint32_t find_crash_tracedata_crc(struct = tmc_drvdata *drvdata, } =20 struct coresight_device *tmc_etr_get_catu_device(struct tmc_drvdata *drvda= ta); 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The interrupt will be triggered when the data size in the ETR buffer exceeds the threshold of the BYTECNTRVAL register. Programming a threshold in the BYTECNTRVAL register of CTCU device will enable the interrupt. Acked-by: Krzysztof Kozlowski Reviewed-by: Mike Leach Signed-off-by: Jie Gan --- Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml | 10 ++++++= ++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml= b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml index e002f87361ad..2981001a7d7f 100644 --- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml +++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml @@ -44,6 +44,11 @@ properties: items: - const: apb =20 + interrupts: + items: + - description: Interrupt for the ETR device connected to in-port0. + - description: Interrupt for the ETR device connected to in-port1. + label: description: Description of a coresight device. @@ -65,6 +70,8 @@ additionalProperties: false =20 examples: - | + #include + ctcu@1001000 { compatible =3D "qcom,sa8775p-ctcu"; reg =3D <0x1001000 0x1000>; @@ -72,6 +79,9 @@ examples: clocks =3D <&aoss_qmp>; clock-names =3D "apb"; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f8e982fd3sm17077339b3a.10.2026.04.21.03.56.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2026 03:56:53 -0700 (PDT) From: Jie Gan Date: Tue, 21 Apr 2026 18:55:55 +0800 Subject: [PATCH v17 6/7] coresight: ctcu: enable byte-cntr for TMC ETR devices Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260421-enable-byte-cntr-for-ctcu-v17-6-9cf36ff55fc0@oss.qualcomm.com> References: <20260421-enable-byte-cntr-for-ctcu-v17-0-9cf36ff55fc0@oss.qualcomm.com> In-Reply-To: <20260421-enable-byte-cntr-for-ctcu-v17-0-9cf36ff55fc0@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Alexander Shishkin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Tingwei Zhang , Bjorn Andersson , Konrad Dybcio Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jie Gan X-Mailer: b4 0.14.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776768976; l=30162; i=jie.gan@oss.qualcomm.com; s=20250909; h=from:subject:message-id; bh=CkaWzgvWCuvwdrbI56bXbUnMRdeKGQFZ5+RIrsXHoFI=; b=FtA0Q+E2wzq5MUP0DNefxEiAxhgw2gdSj5DElNljPvtO4DTzKt2mUXkvbFvIUPNoTyApGaTdm IRpqZbD9bB9BoyqbV+xA9kcK2pQ1IXt/e7vWjP/IaIvT/0YVm1VYHKy X-Developer-Key: i=jie.gan@oss.qualcomm.com; a=ed25519; pk=3LxxUZRPCNkvPDlWOvXfJNqNO4SfGdy3eghMb8puHuk= X-Authority-Analysis: v=2.4 cv=bOQm5v+Z c=1 sm=1 tr=0 ts=69e757f7 cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=o-scWc0g34K81CHX7UgA:9 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: ony-V-Beyusmt2hwHI1DS2kNTZpgtcmT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIxMDEwOCBTYWx0ZWRfX+wUkXyudyuNT U5jqWlmU+ilPUIqvRjjiErRhiS71E6lsELDU+48YiEtEiVfeziICh/s2iX+RFnQcndl9RP33jDv 4cDJ+a/lsKDnTdVrMnfzQrvCaMVsgUZpBqGXOC5dXihqEavsgi7M6+WZJwl5ykmRMoRmCebB7vX oAkSvgKOtI7S053p4xjTPQcvQ7dXzNgNHzcEl4RFUX4LykdkZxrueMh8FTqSruVnfPgKxKqYwS2 a3XF3nqGXJJq70K/fhjhF8gCyAomIiNHaIomOAcA1y6EY7G9B8hKT4Ogc6hY5uCYDII5xZuGmI4 Ib+Pyuonete4EipJf3D0U4LITC5kiI2VENzXdI6dGitU5SDI2/gDLESJQFp4qTXtPlQMk9L/NKv Z9MnIz2WXHqwErf5a6yr2/Uz9B4KIDxmDbp9shW3GRV3tM4hqeH6ZPC2UgkLjiH2YfS/TS/EBbZ Fyb1eca7QBDqbNqG3Xw== X-Proofpoint-ORIG-GUID: ony-V-Beyusmt2hwHI1DS2kNTZpgtcmT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-21_02,2026-04-20_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604210108 The byte-cntr function provided by the CTCU device is used to transfer data from the ETR buffer to the userspace. An interrupt is triggered if the data size exceeds the threshold set in the BYTECNTRVAL register. The interrupt handler counts the number of triggered interruptions and the read function will read the data from the synced ETR buffer. Switching the sysfs_buf when current buffer is full or the timeout is triggered and resets rrp and rwp registers after switched the buffer. The synced buffer will become available for reading after the switch. Byte-cntr workflow: start -> ctcu_enable(ctcu_byte_cntr_start) -> tmc_enable_etr_sink -> tmc_read_prepare_etr(jump to tmc_read_prepare_byte_cntr) -> tmc_etr_get_sysfs_trace(jump to tmc_byte_cntr_get_data) -> tmc_disable_etr_sink -> ctcu_disable(ctcu_byte_cntr_stop) -> tmc_read_unprepare_etr(jump to tmc_read_unprepare_byte_cntr) -> finish Signed-off-by: Jie Gan --- .../ABI/testing/sysfs-bus-coresight-devices-ctcu | 9 + drivers/hwtracing/coresight/Makefile | 2 +- .../hwtracing/coresight/coresight-ctcu-byte-cntr.c | 298 +++++++++++++++++= ++++ drivers/hwtracing/coresight/coresight-ctcu-core.c | 124 ++++++++- drivers/hwtracing/coresight/coresight-ctcu.h | 79 +++++- drivers/hwtracing/coresight/coresight-tmc-core.c | 3 +- drivers/hwtracing/coresight/coresight-tmc-etr.c | 114 +++++++- drivers/hwtracing/coresight/coresight-tmc.h | 9 + 8 files changed, 613 insertions(+), 25 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu b/D= ocumentation/ABI/testing/sysfs-bus-coresight-devices-ctcu new file mode 100644 index 000000000000..3b400480ad53 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-ctcu @@ -0,0 +1,9 @@ +What: /sys/bus/coresight/devices//irq_enabled[0:1] +Date: March 2026 +KernelVersion: 7.2 +Contact: Tingwei Zhang ; Jinlong Ma= o ; Jie Gan +Description: + (RW) Configure the flag to enable interrupt to count data during CTCU en= ablement. + An interrupt is generated when the data size exceeds the value set in th= e IRQ register. + 0 : disable + 1 : enable diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/cores= ight/Makefile index ab16d06783a5..821a1b06b20c 100644 --- a/drivers/hwtracing/coresight/Makefile +++ b/drivers/hwtracing/coresight/Makefile @@ -55,5 +55,5 @@ coresight-cti-y :=3D coresight-cti-core.o coresight-cti-p= latform.o \ obj-$(CONFIG_ULTRASOC_SMB) +=3D ultrasoc-smb.o obj-$(CONFIG_CORESIGHT_DUMMY) +=3D coresight-dummy.o obj-$(CONFIG_CORESIGHT_CTCU) +=3D coresight-ctcu.o -coresight-ctcu-y :=3D coresight-ctcu-core.o +coresight-ctcu-y :=3D coresight-ctcu-core.o coresight-ctcu-byte-cntr.o obj-$(CONFIG_CORESIGHT_KUNIT_TESTS) +=3D coresight-kunit-tests.o diff --git a/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c b/drive= rs/hwtracing/coresight/coresight-ctcu-byte-cntr.c new file mode 100644 index 000000000000..2e136aa4f219 --- /dev/null +++ b/drivers/hwtracing/coresight/coresight-ctcu-byte-cntr.c @@ -0,0 +1,298 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include + +#include "coresight-ctcu.h" +#include "coresight-priv.h" +#include "coresight-tmc.h" + +static irqreturn_t byte_cntr_handler(int irq, void *data) +{ + struct ctcu_byte_cntr *byte_cntr_data =3D data; + + atomic_inc(&byte_cntr_data->irq_cnt); + wake_up(&byte_cntr_data->wq); + + return IRQ_HANDLED; +} + +static void ctcu_cfg_byte_cntr_reg(struct ctcu_drvdata *drvdata, u32 val, + u32 offset) +{ + /* A one value for IRQCTRL register represents 8 bytes */ + ctcu_program_register(drvdata, val / 8, offset); +} + +static struct ctcu_byte_cntr *ctcu_get_byte_cntr(struct coresight_device *= ctcu, + struct coresight_device *etr) +{ + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(ctcu->dev.parent); + int port; + + port =3D coresight_get_in_port(etr, ctcu); + if (port < 0 || port > 1) + return NULL; + + return &drvdata->byte_cntr_data[port]; +} + +static bool ctcu_byte_cntr_switch_buffer(struct tmc_drvdata *etr_drvdata, + struct ctcu_byte_cntr *byte_cntr_data) +{ + struct etr_buf_node *nd, *next, *curr_node =3D NULL, *picked_node =3D NUL= L; + struct etr_buf *curr_buf =3D etr_drvdata->sysfs_buf; + bool found_free_buf =3D false; + + if (WARN_ON(!etr_drvdata || !byte_cntr_data)) + return false; + + /* Stop the ETR before initiating the switch */ + if (coresight_get_mode(etr_drvdata->csdev) !=3D CS_MODE_DISABLED) + tmc_etr_enable_disable_hw(etr_drvdata, false); + + list_for_each_entry_safe(nd, next, &etr_drvdata->etr_buf_list, link) { + /* curr_buf is free for next round */ + if (nd->sysfs_buf =3D=3D curr_buf) { + nd->is_free =3D true; + curr_node =3D nd; + } else if (!found_free_buf && nd->is_free) { + picked_node =3D nd; + found_free_buf =3D true; + } + } + + if (found_free_buf) { + curr_node->pos =3D 0; + curr_node->reading =3D true; + byte_cntr_data->buf_node =3D curr_node; + etr_drvdata->sysfs_buf =3D picked_node->sysfs_buf; + etr_drvdata->etr_buf =3D picked_node->sysfs_buf; + picked_node->is_free =3D false; + /* Reset irq_cnt for next etr_buf */ + atomic_set(&byte_cntr_data->irq_cnt, 0); + /* Restart the ETR once a free buffer is available */ + if (coresight_get_mode(etr_drvdata->csdev) !=3D CS_MODE_DISABLED) + tmc_etr_enable_disable_hw(etr_drvdata, true); + } + + return found_free_buf; +} + +/* + * ctcu_byte_cntr_get_data() - reads data from the deactivated and filled = buffer. + * The byte-cntr reading work reads data from the deactivated and filled b= uffer. + * The read operation waits for a buffer to become available, either fille= d or + * upon timeout, and then reads trace data from the synced buffer. + */ +static ssize_t tmc_byte_cntr_get_data(struct tmc_drvdata *etr_drvdata, lof= f_t pos, + size_t len, char **bufpp) +{ + struct coresight_device *ctcu =3D tmc_etr_get_ctcu_device(etr_drvdata); + struct device *dev =3D &etr_drvdata->csdev->dev; + struct ctcu_byte_cntr *byte_cntr_data; + struct etr_buf *sysfs_buf; + atomic_t *irq_cnt; + ssize_t actual; + int ret; + + byte_cntr_data =3D ctcu_get_byte_cntr(ctcu, etr_drvdata->csdev); + if (!byte_cntr_data || !byte_cntr_data->irq_enabled) + return -EINVAL; + + irq_cnt =3D &byte_cntr_data->irq_cnt; + +wait_buffer: + if (!byte_cntr_data->buf_node) { + ret =3D wait_event_interruptible_timeout(byte_cntr_data->wq, + (atomic_read(irq_cnt) >=3D MAX_IRQ_CNT - 1) || + !byte_cntr_data->enable, + BYTE_CNTR_TIMEOUT); + if (ret < 0) + return ret; + /* + * The current etr_buf is almost full or timeout is triggered, + * so switch the buffer and mark the switched buffer as reading. + */ + if (byte_cntr_data->enable) { + if (!ctcu_byte_cntr_switch_buffer(etr_drvdata, byte_cntr_data)) { + dev_err(dev, "Switch buffer failed for the byte-cntr\n"); + return -ENOMEM; + } + } else { + /* Exit byte-cntr reading */ + return 0; + } + } + + /* Check the status of current etr_buf */ + if (atomic_read(irq_cnt) >=3D MAX_IRQ_CNT) + dev_warn(dev, "Data overwrite happened\n"); + + pos =3D byte_cntr_data->buf_node->pos; + sysfs_buf =3D byte_cntr_data->buf_node->sysfs_buf; + actual =3D tmc_etr_read_sysfs_buf(sysfs_buf, pos, len, bufpp); + if (actual <=3D 0) { + /* Reset buf_node upon reading is finished or failed */ + byte_cntr_data->buf_node->reading =3D false; + byte_cntr_data->buf_node =3D NULL; + + /* + * Nothing in the buffer, waiting for the next buffer + * to be filled. + */ + if (actual =3D=3D 0) + goto wait_buffer; + } + + return actual; +} + +static int tmc_read_prepare_byte_cntr(struct tmc_drvdata *etr_drvdata) +{ + struct coresight_device *ctcu =3D tmc_etr_get_ctcu_device(etr_drvdata); + struct ctcu_byte_cntr *byte_cntr_data; + unsigned long flags; + int ret =3D 0; + + /* byte-cntr is operating with SYSFS mode being enabled only */ + if (coresight_get_mode(etr_drvdata->csdev) !=3D CS_MODE_SYSFS) + return -EINVAL; + + byte_cntr_data =3D ctcu_get_byte_cntr(ctcu, etr_drvdata->csdev); + if (!byte_cntr_data || !byte_cntr_data->irq_enabled) + return -EINVAL; + + raw_spin_lock_irqsave(&byte_cntr_data->spin_lock, flags); + if (byte_cntr_data->reading) { + raw_spin_unlock_irqrestore(&byte_cntr_data->spin_lock, flags); + return -EBUSY; + } + + byte_cntr_data->reading =3D true; + raw_spin_unlock_irqrestore(&byte_cntr_data->spin_lock, flags); + /* Setup an available etr_buf_list for byte-cntr */ + ret =3D tmc_create_etr_buf_list(etr_drvdata, 2); + if (ret) { + byte_cntr_data->reading =3D false; + return ret; + } + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + atomic_set(&byte_cntr_data->irq_cnt, 0); + /* + * Configure the byte-cntr register to enable IRQ. The configured + * size is 5% of the buffer_size. + */ + ctcu_cfg_byte_cntr_reg(byte_cntr_data->ctcu_drvdata, + etr_drvdata->size / MAX_IRQ_CNT, + byte_cntr_data->irq_ctrl_offset); + enable_irq_wake(byte_cntr_data->irq); + byte_cntr_data->buf_node =3D NULL; + + return 0; +} + +static int tmc_read_unprepare_byte_cntr(struct tmc_drvdata *etr_drvdata) +{ + struct coresight_device *ctcu =3D tmc_etr_get_ctcu_device(etr_drvdata); + struct ctcu_byte_cntr *byte_cntr_data; + + byte_cntr_data =3D ctcu_get_byte_cntr(ctcu, etr_drvdata->csdev); + if (!byte_cntr_data || !byte_cntr_data->irq_enabled) + return -EINVAL; + + tmc_clean_etr_buf_list(etr_drvdata); + scoped_guard(raw_spinlock_irqsave, &byte_cntr_data->spin_lock) { + /* Configure the byte-cntr register to disable IRQ */ + ctcu_cfg_byte_cntr_reg(byte_cntr_data->ctcu_drvdata, 0, + byte_cntr_data->irq_ctrl_offset); + disable_irq_wake(byte_cntr_data->irq); + byte_cntr_data->buf_node =3D NULL; + byte_cntr_data->reading =3D false; + } + wake_up(&byte_cntr_data->wq); + + return 0; +} + +const struct tmc_sysfs_ops byte_cntr_sysfs_ops =3D { + .read_prepare =3D tmc_read_prepare_byte_cntr, + .read_unprepare =3D tmc_read_unprepare_byte_cntr, + .get_trace_data =3D tmc_byte_cntr_get_data, +}; + +/* Start the byte-cntr function when the path is enabled. */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight= _path *path) +{ + struct coresight_device *sink =3D coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + + byte_cntr_data =3D ctcu_get_byte_cntr(csdev, sink); + if (!byte_cntr_data) + return; + + /* Don't start byte-cntr function when irq_enabled is not set. */ + if (!byte_cntr_data->irq_enabled || byte_cntr_data->enable) + return; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable =3D true; +} + +/* Stop the byte-cntr function when the path is disabled. */ +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_= path *path) +{ + struct coresight_device *sink =3D coresight_get_sink(path); + struct ctcu_byte_cntr *byte_cntr_data; + + if (coresight_get_mode(sink) =3D=3D CS_MODE_SYSFS) + return; + + byte_cntr_data =3D ctcu_get_byte_cntr(csdev, sink); + if (!byte_cntr_data) + return; + + guard(raw_spinlock_irqsave)(&byte_cntr_data->spin_lock); + byte_cntr_data->enable =3D false; +} + +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata,= int etr_num) +{ + struct ctcu_byte_cntr *byte_cntr_data; + struct device_node *nd =3D dev->of_node; + int irq_num, ret, i, irq_registered =3D 0; + + for (i =3D 0; i < etr_num; i++) { + byte_cntr_data =3D &drvdata->byte_cntr_data[i]; + irq_num =3D of_irq_get(nd, i); + if (irq_num < 0) { + dev_err(dev, "Failed to get IRQ from DT for port%d\n", i); + continue; + } + + ret =3D devm_request_irq(dev, irq_num, byte_cntr_handler, + IRQF_TRIGGER_RISING | IRQF_SHARED, + dev_name(dev), byte_cntr_data); + if (ret) { + dev_err(dev, "Failed to register IRQ for port%d\n", i); + continue; + } + + byte_cntr_data->irq =3D irq_num; + byte_cntr_data->ctcu_drvdata =3D drvdata; + init_waitqueue_head(&byte_cntr_data->wq); + raw_spin_lock_init(&byte_cntr_data->spin_lock); + irq_registered++; + } + + if (irq_registered) + tmc_etr_set_byte_cntr_sysfs_ops(&byte_cntr_sysfs_ops); +} diff --git a/drivers/hwtracing/coresight/coresight-ctcu-core.c b/drivers/hw= tracing/coresight/coresight-ctcu-core.c index e8720026c9e3..897d51936b88 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu-core.c +++ b/drivers/hwtracing/coresight/coresight-ctcu-core.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + * Copyright (c) 2024-2026 Qualcomm Innovation Center, Inc. All rights res= erved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 #include @@ -18,6 +19,7 @@ =20 #include "coresight-ctcu.h" #include "coresight-priv.h" +#include "coresight-tmc.h" =20 #define ctcu_writel(drvdata, val, offset) __raw_writel((val), drvdata->bas= e + offset) #define ctcu_readl(drvdata, offset) __raw_readl(drvdata->base + offset) @@ -43,17 +45,21 @@ =20 #define CTCU_ATID_REG_BIT(traceid) (traceid % 32) #define CTCU_ATID_REG_SIZE 0x10 +#define CTCU_ETR0_IRQCTRL 0x6c +#define CTCU_ETR1_IRQCTRL 0x70 #define CTCU_ETR0_ATID0 0xf8 #define CTCU_ETR1_ATID0 0x108 =20 static const struct ctcu_etr_config sa8775p_etr_cfgs[] =3D { { - .atid_offset =3D CTCU_ETR0_ATID0, - .port_num =3D 0, + .atid_offset =3D CTCU_ETR0_ATID0, + .irq_ctrl_offset =3D CTCU_ETR0_IRQCTRL, + .port_num =3D 0, }, { - .atid_offset =3D CTCU_ETR1_ATID0, - .port_num =3D 1, + .atid_offset =3D CTCU_ETR1_ATID0, + .irq_ctrl_offset =3D CTCU_ETR1_IRQCTRL, + .port_num =3D 1, }, }; =20 @@ -62,6 +68,85 @@ static const struct ctcu_config sa8775p_cfgs =3D { .num_etr_config =3D ARRAY_SIZE(sa8775p_etr_cfgs), }; =20 +void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u32 offs= et) +{ + CS_UNLOCK(drvdata->base); + ctcu_writel(drvdata, val, offset); + CS_LOCK(drvdata->base); +} + +static ssize_t irq_enabled_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct ctcu_byte_cntr_irq_attribute *irq_attr =3D + container_of(attr, struct ctcu_byte_cntr_irq_attribute, attr); + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + u8 port =3D irq_attr->port; + + if (!drvdata->byte_cntr_data[port].irq_ctrl_offset) + return -EINVAL; + + return sysfs_emit(buf, "%u\n", + (unsigned int)drvdata->byte_cntr_data[port].irq_enabled); +} + +static ssize_t irq_enabled_store(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t size) +{ + struct ctcu_byte_cntr_irq_attribute *irq_attr =3D + container_of(attr, struct ctcu_byte_cntr_irq_attribute, attr); + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + u8 port =3D irq_attr->port; + unsigned long val; + + if (kstrtoul(buf, 0, &val)) + return -EINVAL; + + guard(raw_spinlock_irqsave)(&drvdata->byte_cntr_data[port].spin_lock); + if (drvdata->byte_cntr_data[port].reading) + return -EBUSY; + else if (drvdata->byte_cntr_data[port].irq_ctrl_offset) + drvdata->byte_cntr_data[port].irq_enabled =3D !!val; + + return size; +} + +static umode_t irq_enabled_is_visible(struct kobject *kobj, + struct attribute *attr, int n) +{ + struct device_attribute *dev_attr =3D + container_of(attr, struct device_attribute, attr); + struct ctcu_byte_cntr_irq_attribute *irq_attr =3D + container_of(dev_attr, struct ctcu_byte_cntr_irq_attribute, attr); + struct device *dev =3D kobj_to_dev(kobj); + struct ctcu_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + u8 port =3D irq_attr->port; + + if (drvdata && drvdata->byte_cntr_data[port].irq_ctrl_offset) + return attr->mode; + + return 0; +} + +static struct attribute *ctcu_attrs[] =3D { + ctcu_byte_cntr_irq_rw(0), + ctcu_byte_cntr_irq_rw(1), + NULL, +}; + +static struct attribute_group ctcu_attr_grp =3D { + .attrs =3D ctcu_attrs, + .is_visible =3D irq_enabled_is_visible, +}; + +static const struct attribute_group *ctcu_attr_grps[] =3D { + &ctcu_attr_grp, + NULL, +}; + static void ctcu_program_atid_register(struct ctcu_drvdata *drvdata, u32 r= eg_offset, u8 bit, bool enable) { @@ -140,11 +225,15 @@ static int ctcu_set_etr_traceid(struct coresight_devi= ce *csdev, struct coresight static int ctcu_enable(struct coresight_device *csdev, enum cs_mode mode, struct coresight_path *path) { + ctcu_byte_cntr_start(csdev, path); + return ctcu_set_etr_traceid(csdev, path, true); } =20 static int ctcu_disable(struct coresight_device *csdev, struct coresight_p= ath *path) { + ctcu_byte_cntr_stop(csdev, path); + return ctcu_set_etr_traceid(csdev, path, false); } =20 @@ -195,7 +284,10 @@ static int ctcu_probe(struct platform_device *pdev) for (i =3D 0; i < cfgs->num_etr_config; i++) { etr_cfg =3D &cfgs->etr_cfgs[i]; drvdata->atid_offset[i] =3D etr_cfg->atid_offset; + drvdata->byte_cntr_data[i].irq_ctrl_offset =3D + etr_cfg->irq_ctrl_offset; } + ctcu_byte_cntr_init(dev, drvdata, cfgs->num_etr_config); } } =20 @@ -209,6 +301,7 @@ static int ctcu_probe(struct platform_device *pdev) desc.dev =3D dev; desc.ops =3D &ctcu_ops; desc.access =3D CSDEV_ACCESS_IOMEM(base); + desc.groups =3D ctcu_attr_grps; raw_spin_lock_init(&drvdata->spin_lock); =20 drvdata->csdev =3D coresight_register(&desc); @@ -244,10 +337,31 @@ static int ctcu_platform_probe(struct platform_device= *pdev) static void ctcu_platform_remove(struct platform_device *pdev) { struct ctcu_drvdata *drvdata =3D platform_get_drvdata(pdev); + struct ctcu_byte_cntr *byte_cntr_data; + unsigned long flags; + int i; =20 if (WARN_ON(!drvdata)) return; =20 + /* + * Signal all active byte-cntr readers to exit, then wait for them to + * finish before resetting the ops pointer and freeing driver data. + * Without this, a reader blocked in wait_event_interruptible_timeout() + * would access the freed ctcu_drvdata wait-queue head (use-after-free). + */ + for (i =3D 0; i < ETR_MAX_NUM; i++) { + byte_cntr_data =3D &drvdata->byte_cntr_data[i]; + if (!byte_cntr_data->reading) + continue; + raw_spin_lock_irqsave(&byte_cntr_data->spin_lock, flags); + byte_cntr_data->enable =3D false; + raw_spin_unlock_irqrestore(&byte_cntr_data->spin_lock, flags); + wake_up_all(&byte_cntr_data->wq); + wait_event(byte_cntr_data->wq, !byte_cntr_data->reading); + } + + tmc_etr_reset_byte_cntr_sysfs_ops(); ctcu_remove(pdev); pm_runtime_disable(&pdev->dev); } diff --git a/drivers/hwtracing/coresight/coresight-ctcu.h b/drivers/hwtraci= ng/coresight/coresight-ctcu.h index e9594c38dd91..a2ae0a0d91d0 100644 --- a/drivers/hwtracing/coresight/coresight-ctcu.h +++ b/drivers/hwtracing/coresight/coresight-ctcu.h @@ -1,23 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ /* - * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + * Copyright (c) 2024-2026 Qualcomm Innovation Center, Inc. All rights res= erved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 #ifndef _CORESIGHT_CTCU_H #define _CORESIGHT_CTCU_H + +#include #include "coresight-trace-id.h" =20 /* Maximum number of supported ETR devices for a single CTCU. */ #define ETR_MAX_NUM 2 =20 +#define BYTE_CNTR_TIMEOUT (3 * HZ) +#define MAX_IRQ_CNT 20 + /** * struct ctcu_etr_config * @atid_offset: offset to the ATID0 Register. - * @port_num: in-port number of CTCU device that connected to ETR. + * @port_num: in-port number of the CTCU device that connected to ETR. + * @irq_ctrl_offset: offset to the BYTECNTRVAL register. */ struct ctcu_etr_config { const u32 atid_offset; const u32 port_num; + const u32 irq_ctrl_offset; }; =20 struct ctcu_config { @@ -25,15 +33,68 @@ struct ctcu_config { int num_etr_config; }; =20 -struct ctcu_drvdata { - void __iomem *base; - struct clk *apb_clk; - struct device *dev; - struct coresight_device *csdev; +/** + * struct ctcu_byte_cntr + * @enable: indicates that byte_cntr function is enabled or not. + * @irq_enabled: indicates that the interruption is enabled. + * @reading: indicates that byte_cntr is reading. + * @irq: allocated number of the IRQ. + * @irq_cnt: IRQ count number of the triggered interruptions. + * @wq: waitqueue for reading data from ETR buffer. + * @spin_lock: spinlock of the byte_cntr_data. + * @irq_ctrl_offset: offset to the BYTECNTVAL Register. + * @ctcu_drvdata: drvdata of the CTCU device. + * @buf_node: etr_buf_node for reading. + */ +struct ctcu_byte_cntr { + bool enable; + bool irq_enabled; + bool reading; + int irq; + atomic_t irq_cnt; + wait_queue_head_t wq; raw_spinlock_t spin_lock; - u32 atid_offset[ETR_MAX_NUM]; + u32 irq_ctrl_offset; + struct ctcu_drvdata *ctcu_drvdata; + struct etr_buf_node *buf_node; +}; + +struct ctcu_drvdata { + void __iomem *base; + struct clk *apb_clk; + struct device *dev; + struct coresight_device *csdev; + struct ctcu_byte_cntr byte_cntr_data[ETR_MAX_NUM]; + raw_spinlock_t spin_lock; + u32 atid_offset[ETR_MAX_NUM]; /* refcnt for each traceid of each sink */ - u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; + u8 traceid_refcnt[ETR_MAX_NUM][CORESIGHT_TRACE_ID_RES_TOP]; }; =20 +/** + * struct ctcu_byte_cntr_irq_attribute + * @attr: The device attribute. + * @port: port number. + */ +struct ctcu_byte_cntr_irq_attribute { + struct device_attribute attr; + u8 port; +}; + +#define ctcu_byte_cntr_irq_rw(port) \ + (&((struct ctcu_byte_cntr_irq_attribute[]) { \ + { \ + __ATTR(irq_enabled##port, 0644, irq_enabled_show, \ + irq_enabled_store), \ + port, \ + } \ + })[0].attr.attr) + +void ctcu_program_register(struct ctcu_drvdata *drvdata, u32 val, u32 offs= et); + +/* Byte-cntr functions */ +void ctcu_byte_cntr_start(struct coresight_device *csdev, struct coresight= _path *path); +void ctcu_byte_cntr_stop(struct coresight_device *csdev, struct coresight_= path *path); +void ctcu_byte_cntr_init(struct device *dev, struct ctcu_drvdata *drvdata,= int port_num); + #endif diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 110eedde077f..9f4fd86e8c32 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -293,7 +293,8 @@ static ssize_t tmc_read(struct file *file, char __user = *data, size_t len, return -EFAULT; } =20 - *ppos +=3D actual; + if (!tmc_etr_update_buf_node_pos(drvdata, actual)) + *ppos +=3D actual; dev_dbg(&drvdata->csdev->dev, "%zu bytes copied\n", actual); =20 return actual; diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index bb76e7e37874..14e3a89432ec 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1168,6 +1168,8 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvd= ata, return rc; } =20 +static const struct tmc_sysfs_ops *byte_cntr_sysfs_ops; + /* * Return the available trace data in the buffer (starts at etr_buf->offse= t, * limited by etr_buf->len) from @pos, with a maximum limit of @len, @@ -1178,23 +1180,39 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *dr= vdata, * We are protected here by drvdata->reading !=3D 0, which ensures the * sysfs_buf stays alive. */ -ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, - loff_t pos, size_t len, char **bufpp) +ssize_t tmc_etr_read_sysfs_buf(struct etr_buf *sysfs_buf, loff_t pos, + size_t len, char **bufpp) { s64 offset; ssize_t actual =3D len; - struct etr_buf *etr_buf =3D drvdata->sysfs_buf; =20 - if (pos + actual > etr_buf->len) - actual =3D etr_buf->len - pos; + if (pos + actual > sysfs_buf->len) + actual =3D sysfs_buf->len - pos; if (actual <=3D 0) return actual; =20 /* Compute the offset from which we read the data */ - offset =3D etr_buf->offset + pos; - if (offset >=3D etr_buf->size) - offset -=3D etr_buf->size; - return tmc_etr_buf_get_data(etr_buf, offset, actual, bufpp); + offset =3D sysfs_buf->offset + pos; + if (offset >=3D sysfs_buf->size) + offset -=3D sysfs_buf->size; + return tmc_etr_buf_get_data(sysfs_buf, offset, actual, bufpp); +} +EXPORT_SYMBOL_GPL(tmc_etr_read_sysfs_buf); + +ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata, + loff_t pos, size_t len, char **bufpp) +{ + ssize_t ret; + const struct tmc_sysfs_ops *byte_cntr_ops =3D READ_ONCE(byte_cntr_sysfs_o= ps); + + if (byte_cntr_ops) { + ret =3D byte_cntr_ops->get_trace_data(drvdata, pos, len, bufpp); + /* Return the filled buffer */ + if (ret > 0 || ret =3D=3D -ENOMEM) + return ret; + } + + return tmc_etr_read_sysfs_buf(drvdata->sysfs_buf, pos, len, bufpp); } =20 static struct etr_buf * @@ -1248,6 +1266,39 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata = *drvdata) =20 } =20 +static void tmc_etr_reset_sysfs_buf(struct tmc_drvdata *drvdata) +{ + u32 sts; + + CS_UNLOCK(drvdata->base); + tmc_write_rrp(drvdata, drvdata->sysfs_buf->hwaddr); + tmc_write_rwp(drvdata, drvdata->sysfs_buf->hwaddr); + sts =3D readl_relaxed(drvdata->base + TMC_STS) & ~TMC_STS_FULL; + writel_relaxed(sts, drvdata->base + TMC_STS); + CS_LOCK(drvdata->base); +} + +/** + * tmc_etr_enable_disable_hw - enable/disable the ETR hw. + * @drvdata: drvdata of the TMC device. + * @enable: indicates enable/disable. + */ +void tmc_etr_enable_disable_hw(struct tmc_drvdata *drvdata, bool enable) +{ + unsigned long flags; + + raw_spin_lock_irqsave(&drvdata->spinlock, flags); + if (enable) { + tmc_etr_reset_sysfs_buf(drvdata); + __tmc_etr_enable_hw(drvdata); + } else { + __tmc_etr_disable_hw(drvdata); + } + + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); +} +EXPORT_SYMBOL_GPL(tmc_etr_enable_disable_hw); + void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) { __tmc_etr_disable_hw(drvdata); @@ -2041,15 +2092,54 @@ int tmc_create_etr_buf_list(struct tmc_drvdata *drv= data, int num_nodes) } EXPORT_SYMBOL_GPL(tmc_create_etr_buf_list); =20 +void tmc_etr_set_byte_cntr_sysfs_ops(const struct tmc_sysfs_ops *sysfs_ops) +{ + WRITE_ONCE(byte_cntr_sysfs_ops, sysfs_ops); +} +EXPORT_SYMBOL_GPL(tmc_etr_set_byte_cntr_sysfs_ops); + +void tmc_etr_reset_byte_cntr_sysfs_ops(void) +{ + WRITE_ONCE(byte_cntr_sysfs_ops, NULL); +} +EXPORT_SYMBOL_GPL(tmc_etr_reset_byte_cntr_sysfs_ops); + +bool tmc_etr_update_buf_node_pos(struct tmc_drvdata *drvdata, ssize_t size) +{ + struct etr_buf_node *nd, *next; + + if (drvdata->config_type !=3D TMC_CONFIG_TYPE_ETR) + return false; + + list_for_each_entry_safe(nd, next, &drvdata->etr_buf_list, link) { + if (nd && nd->reading) { + nd->pos +=3D size; + return true; + } + } + + return false; +} + int tmc_read_prepare_etr(struct tmc_drvdata *drvdata) { int ret =3D 0; unsigned long flags; + const struct tmc_sysfs_ops *byte_cntr_ops; =20 /* config types are set a boot time and never change */ if (WARN_ON_ONCE(drvdata->config_type !=3D TMC_CONFIG_TYPE_ETR)) return -EINVAL; =20 + byte_cntr_ops =3D READ_ONCE(byte_cntr_sysfs_ops); + if (byte_cntr_ops) { + ret =3D byte_cntr_ops->read_prepare(drvdata); + if (!ret || ret =3D=3D -EBUSY) + return ret; + + ret =3D 0; + } + raw_spin_lock_irqsave(&drvdata->spinlock, flags); if (drvdata->reading) { ret =3D -EBUSY; @@ -2081,11 +2171,17 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvd= ata) { unsigned long flags; struct etr_buf *sysfs_buf =3D NULL; + const struct tmc_sysfs_ops *byte_cntr_ops; =20 /* config types are set a boot time and never change */ if (WARN_ON_ONCE(drvdata->config_type !=3D TMC_CONFIG_TYPE_ETR)) return -EINVAL; =20 + byte_cntr_ops =3D READ_ONCE(byte_cntr_sysfs_ops); + if (byte_cntr_ops) + if (!byte_cntr_ops->read_unprepare(drvdata)) + return 0; + raw_spin_lock_irqsave(&drvdata->spinlock, flags); =20 /* RE-enable the TMC if need be */ diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index fbb015079872..a15e2f93f16a 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -211,12 +211,15 @@ struct tmc_resrv_buf { /** * @sysfs_buf: Allocated sysfs_buf. * @is_free: Indicates whether the buffer is free to choose. + * @reading: Indicates byte_cntr is reading the buffer attached to + * the node. * @pos: Offset to the start of the buffer. * @link: list_head of the node. */ struct etr_buf_node { struct etr_buf *sysfs_buf; bool is_free; + bool reading; loff_t pos; struct list_head link; }; @@ -480,5 +483,11 @@ struct etr_buf *tmc_etr_get_buffer(struct coresight_de= vice *csdev, extern const struct attribute_group coresight_etr_group; void tmc_clean_etr_buf_list(struct tmc_drvdata *drvdata); int tmc_create_etr_buf_list(struct tmc_drvdata *drvdata, int num_nodes); +void tmc_etr_set_byte_cntr_sysfs_ops(const struct tmc_sysfs_ops *sysfs_ops= ); +void tmc_etr_reset_byte_cntr_sysfs_ops(void); +void tmc_etr_enable_disable_hw(struct tmc_drvdata *drvdata, bool enable); +bool tmc_etr_update_buf_node_pos(struct tmc_drvdata *drvdata, ssize_t size= ); +ssize_t tmc_etr_read_sysfs_buf(struct etr_buf *sysfs_buf, loff_t pos, + size_t len, char **bufpp); =20 #endif --=20 2.34.1 From nobody Thu Apr 30 05:07:24 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10E0D28371 for ; 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Reviewed-by: Konrad Dybcio Signed-off-by: Jie Gan --- arch/arm64/boot/dts/qcom/lemans.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qco= m/lemans.dtsi index fe6e76351823..2cc855ec9759 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -2800,6 +2800,9 @@ ctcu@4001000 { clocks =3D <&aoss_qmp>; clock-names =3D "apb"; =20 + interrupts =3D , + ; + in-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1