From nobody Fri Jun 19 23:22:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A979A3BFE38; Mon, 20 Apr 2026 19:20:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776712815; cv=none; b=dw6T9CBjxpBTlVn1ZPJSPz0SYidLC7FfkjAJ+afj8aK+yn2/OWULy40XM/n0FsmCUhrSUJ3TQ4Cg+13E5+0EZ7iCxG49frga3YSfeR9h24rFlT5aZ7B32eTHrENg1K5dZl75Pem83yhQ0x0Nr8USjWbUfzXvhgBzwJUp9LghQl4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776712815; c=relaxed/simple; bh=Jcxwupu+wTBpDG6xdcuBM9DrQH2ZXWKxV+VH4aAhImk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ecj2V4KKZcCBNe//OA+3jXeO0M0KFgKtmo7JbTB5plBIkkyMnRpaxzSL5nD6HVP/CovtRQhHaCeoqWLhRi994Kh3zNCeWTggh5riadUPK7cHxeaP9/DssrWvPwJYbjjjdReNdmirNbWAHNNmUNXJaKKZcVcr+Exyz4VnOhWSGCA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=akAmqQQn; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="akAmqQQn" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 3ECA326F66; Mon, 20 Apr 2026 21:20:10 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id SZB-5Fth3vU0; Mon, 20 Apr 2026 21:20:09 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776712809; bh=Jcxwupu+wTBpDG6xdcuBM9DrQH2ZXWKxV+VH4aAhImk=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=akAmqQQnAWCdFcofrYq7GBx155c7PGBdIfRZ3YbmrPuR6Y7kqb8XkSB/i3Wd/jzos iLm7G4CDiSh3xLytIJ9BPgG30X17MBnxdaK8DJ4YKnWxAaKxK9V7Q/t6/Lj3fj0ump hz0p2PQXcdVFRBiW/IHdbEW3ZxLy7chQ7wnxaqfJxU6hXe52uRvmA03nw6NkrbanyW FjcWOGvs88T3mxFBTQA8wnMtQ+7Dd6v8eot3NG95PiYQic8MJaBz08Ga1icNDR1NEr ZfOuuttEqU6qEhjypZ7QM6Z8D0iBKI+IsuLdrrgc37oZUiIVQ7iPXmuqEGKVI/mMq5 zMCwp6J2A4acA== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov , Michael Zavertkin Subject: [PATCH v5 1/6] phy: realtek: usb2: introduce vstatus/new_reg_req variables to driver data Date: Tue, 21 Apr 2026 00:19:36 +0500 Message-ID: <20260420191941.81834-2-adilov@disroot.org> In-Reply-To: <20260420191941.81834-1-adilov@disroot.org> References: <20260420191941.81834-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In RTL9607C SoC, the vstatus register is located at a certain offset from the base and so introduce the vstatus_offset to handle it. Busy bit of the vstatus and new_reg_req bit are also different and so introduce these variables to the driver data as well. Add these variables to the pre-existing phy cfg structs for RTD SoCs and assign them the default values. Co-developed-by: Michael Zavertkin Signed-off-by: Michael Zavertkin Signed-off-by: Rustam Adilov --- drivers/phy/realtek/phy-rtk-usb2.c | 67 +++++++++++++++++++++++------- 1 file changed, 52 insertions(+), 15 deletions(-) diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-r= tk-usb2.c index 248550ef98ca..f5f943518d4f 100644 --- a/drivers/phy/realtek/phy-rtk-usb2.c +++ b/drivers/phy/realtek/phy-rtk-usb2.c @@ -64,6 +64,9 @@ struct phy_reg { void __iomem *reg_wrap_vstatus; void __iomem *reg_gusb2phyacc0; int vstatus_index; + int vstatus_offset; + u32 vstatus_busy; + u32 new_reg_req; }; =20 struct phy_data { @@ -96,6 +99,9 @@ struct phy_cfg { bool do_toggle_driving; bool use_default_parameter; bool is_double_sensitivity_mode; + int vstatus_offset; + u32 vstatus_busy; + u32 new_reg_req; }; =20 struct phy_parameter { @@ -162,21 +168,21 @@ static char rtk_phy_read(struct phy_reg *phy_reg, cha= r addr) addr -=3D OFFEST_PHY_READ; =20 /* polling until VBusy =3D=3D 0 */ - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return (char)ret; =20 - /* VCtrl =3D low nibble of addr, and set PHY_NEW_REG_REQ */ - val =3D PHY_NEW_REG_REQ | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); + /* VCtrl =3D low nibble of addr, and set phy_reg->new_reg_req */ + val =3D phy_reg->new_reg_req | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return (char)ret; =20 - /* VCtrl =3D high nibble of addr, and set PHY_NEW_REG_REQ */ - val =3D PHY_NEW_REG_REQ | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); + /* VCtrl =3D high nibble of addr, and set phy_reg->new_reg_req */ + val =3D phy_reg->new_reg_req | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return (char)ret; =20 @@ -194,25 +200,25 @@ static int rtk_phy_write(struct phy_reg *phy_reg, cha= r addr, char data) int ret =3D 0; =20 /* write data to VStatusOut2 (data output to phy) */ - writel((u32)data << shift_bits, reg_wrap_vstatus); + writel((u32)data << shift_bits, reg_wrap_vstatus + phy_reg->vstatus_offse= t); =20 - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return ret; =20 - /* VCtrl =3D low nibble of addr, set PHY_NEW_REG_REQ */ - val =3D PHY_NEW_REG_REQ | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); + /* VCtrl =3D low nibble of addr, set phy_reg->new_reg_req */ + val =3D phy_reg->new_reg_req | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); =20 writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return ret; =20 - /* VCtrl =3D high nibble of addr, set PHY_NEW_REG_REQ */ - val =3D PHY_NEW_REG_REQ | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); + /* VCtrl =3D high nibble of addr, set phy_reg->new_reg_req */ + val =3D phy_reg->new_reg_req | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); =20 writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, PHY_VSTS_BUSY, 0); + ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); if (ret) return ret; =20 @@ -957,6 +963,7 @@ static int get_phy_data_by_efuse(struct rtk_phy *rtk_ph= y, =20 static int parse_phy_data(struct rtk_phy *rtk_phy) { + struct phy_cfg *phy_cfg =3D rtk_phy->phy_cfg; struct device *dev =3D rtk_phy->dev; struct device_node *np =3D dev->of_node; struct phy_parameter *phy_parameter; @@ -974,6 +981,9 @@ static int parse_phy_data(struct rtk_phy *rtk_phy) phy_parameter->phy_reg.reg_wrap_vstatus =3D of_iomap(np, 0); phy_parameter->phy_reg.reg_gusb2phyacc0 =3D of_iomap(np, 1) + index; phy_parameter->phy_reg.vstatus_index =3D index; + phy_parameter->phy_reg.vstatus_offset =3D phy_cfg->vstatus_offset; + phy_parameter->phy_reg.vstatus_busy =3D phy_cfg->vstatus_busy; + phy_parameter->phy_reg.new_reg_req =3D phy_cfg->new_reg_req; =20 if (of_property_read_bool(np, "realtek,inverse-hstx-sync-clock")) phy_parameter->inverse_hstx_sync_clock =3D true; @@ -1085,6 +1095,9 @@ static const struct phy_cfg rtd1295_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D false, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1395_phy_cfg =3D { @@ -1109,6 +1122,9 @@ static const struct phy_cfg rtd1395_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D false, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1395_phy_cfg_2port =3D { @@ -1133,6 +1149,9 @@ static const struct phy_cfg rtd1395_phy_cfg_2port =3D= { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D false, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1619_phy_cfg =3D { @@ -1155,6 +1174,9 @@ static const struct phy_cfg rtd1619_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D false, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1319_phy_cfg =3D { @@ -1181,6 +1203,9 @@ static const struct phy_cfg rtd1319_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1312c_phy_cfg =3D { @@ -1206,6 +1231,9 @@ static const struct phy_cfg rtd1312c_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0xf, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1619b_phy_cfg =3D { @@ -1231,6 +1259,9 @@ static const struct phy_cfg rtd1619b_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0x8, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1319d_phy_cfg =3D { @@ -1256,6 +1287,9 @@ static const struct phy_cfg rtd1319d_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0x8, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct phy_cfg rtd1315e_phy_cfg =3D { @@ -1282,6 +1316,9 @@ static const struct phy_cfg rtd1315e_phy_cfg =3D { .driving_updated_for_dev_dis =3D 0x8, .use_default_parameter =3D false, .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0, + .vstatus_busy =3D PHY_VSTS_BUSY, + .new_reg_req =3D PHY_NEW_REG_REQ, }; =20 static const struct of_device_id usbphy_rtk_dt_match[] =3D { --=20 2.53.0 From nobody Fri Jun 19 23:22:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 804273C3434; Mon, 20 Apr 2026 19:20:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776712818; cv=none; b=VLiMEL0O/KYF3aemMkqyneKPZpt0TxxPm58Fyj2g/8lqmgevll5qVc/oYccZVrKgJeG8dgmbvQoJqrGJ1YudH8FtwWF1FCZ30uOLpT7vChnqKo7r/KL74Hu0JFcKqw9b0oWiUTEU7JEnCblv+6whusXybbEz+Por1J3XitN3eeQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776712818; c=relaxed/simple; bh=ROOlVgUrHHP+HI+NTgDLFYkShVeEFMmEVnBVofPqvSQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Tk+dzt83o6QkEle6c0uwpKTqRcYh32qWyxEqqhhUioNvJsPbsuDsNnsrQZ9U5twWIuVFlSbvXK1RVLdcXbX4dxHbSBukg5nBApZ51ZBtOX/I3GsPZwat3eIJDopRtWzRU0iWVLjJdzVnEKBO8bKnaDon1aAhmYEjsBoojJlI2As= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=gK/SgyTz; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="gK/SgyTz" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id A1CE426E4F; Mon, 20 Apr 2026 21:20:12 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id RpVIoUe0qFPW; Mon, 20 Apr 2026 21:20:12 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776712812; bh=ROOlVgUrHHP+HI+NTgDLFYkShVeEFMmEVnBVofPqvSQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=gK/SgyTzgbWIRdC61cf2FeHn59LGd9z4NX4hcN5f66ABVstKFe+vbNGDI2wV4CuyB GRI0WnLT4e4TH4fO3v0FWzgvSmQ+d8/zoWYYExwBttgpgRBmxeV8Mu+ywECiIIyQQ2 0KXQemW4ZmaOgIxsp9XnOFIhr3M3OIJk0PVpWD7uactsXxKiSP8D60aaTtvFCmDM8H WPW7vRQeEnSwAgYtV0Za9xPRfGCW9Rg8XesdwMmktq51vCFBwLEnevrO32H63BVwFJ XR1nQMhwT7VBcxjsVBstNrKRKIyzLj/L0lc1Q9b/OPwsZBX91yvREnnqQ9GHcmbJsJ uHKj4W4Vcfwfw== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov , Michael Zavertkin Subject: [PATCH v5 2/6] phy: realtek: usb2: introduce read and write functions to driver data Date: Tue, 21 Apr 2026 00:19:37 +0500 Message-ID: <20260420191941.81834-3-adilov@disroot.org> In-Reply-To: <20260420191941.81834-1-adilov@disroot.org> References: <20260420191941.81834-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" RTL9607C is a big endian SoC but has little endian USB host controller and thus, reads and writes to the reg_gusb2phyacc0 should go through le32_to_cpu and cpu_to_le32 functions respectively. This doesn't apply to vstatus register though as it is in the different register region compared to USB host controller region. The reason is readl/writel functions, despite the supposed little endian byte swap, still operate with native endian and this is because RTL9607C is MIPS and here readl/writel are native unless SWAP_IO_SPACE is enabled. Enabling SWAP_IO_SPACE results in boot hangs so that is not an option. And so wrapping them around le32 makes a proper byte swap from big endian to little endian. To handle this situation, introduce read and write functions to the driver data and create a default variation of read and write function for the current RTD SoCs. Adjust all instances of utmi_wait_register function to now include the read function as one of its arguments. Assign the existing phy configuration for RTD SoCs to the default read and write functions. Co-developed-by: Michael Zavertkin Signed-off-by: Michael Zavertkin Signed-off-by: Rustam Adilov --- drivers/phy/realtek/phy-rtk-usb2.c | 63 ++++++++++++++++++++++++------ 1 file changed, 50 insertions(+), 13 deletions(-) diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-r= tk-usb2.c index f5f943518d4f..19297a42a841 100644 --- a/drivers/phy/realtek/phy-rtk-usb2.c +++ b/drivers/phy/realtek/phy-rtk-usb2.c @@ -67,6 +67,9 @@ struct phy_reg { int vstatus_offset; u32 vstatus_busy; u32 new_reg_req; + + u32 (*read)(void __iomem *reg); + void (*write)(u32 val, void __iomem *reg); }; =20 struct phy_data { @@ -102,6 +105,9 @@ struct phy_cfg { int vstatus_offset; u32 vstatus_busy; u32 new_reg_req; + + u32 (*read)(void __iomem *reg); + void (*write)(u32 val, void __iomem *reg); }; =20 struct phy_parameter { @@ -128,6 +134,16 @@ struct rtk_phy { struct dentry *debug_dir; }; =20 +static u32 rtk_usb2phy_read(void __iomem *reg) +{ + return readl(reg); +} + +static void rtk_usb2phy_write(u32 val, void __iomem *reg) +{ + writel(val, reg); +} + /* mapping 0xE0 to 0 ... 0xE7 to 7, 0xF0 to 8 ,,, 0xF7 to 15 */ static inline int page_addr_to_array_index(u8 addr) { @@ -144,12 +160,13 @@ static inline u8 array_index_to_page_addr(int index) #define PHY_IO_TIMEOUT_USEC (50000) #define PHY_IO_DELAY_US (100) =20 -static inline int utmi_wait_register(void __iomem *reg, u32 mask, u32 resu= lt) +static inline int utmi_wait_register(u32 (*read)(void __iomem *reg), void = __iomem *reg, u32 mask, + u32 result) { int ret; unsigned int val; =20 - ret =3D read_poll_timeout(readl, val, ((val & mask) =3D=3D result), + ret =3D read_poll_timeout(read, val, ((val & mask) =3D=3D result), PHY_IO_DELAY_US, PHY_IO_TIMEOUT_USEC, false, reg); if (ret) { pr_err("%s can't program USB phy\n", __func__); @@ -168,25 +185,25 @@ static char rtk_phy_read(struct phy_reg *phy_reg, cha= r addr) addr -=3D OFFEST_PHY_READ; =20 /* polling until VBusy =3D=3D 0 */ - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return (char)ret; =20 /* VCtrl =3D low nibble of addr, and set phy_reg->new_reg_req */ val =3D phy_reg->new_reg_req | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); - writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + phy_reg->write(val, reg_gusb2phyacc0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return (char)ret; =20 /* VCtrl =3D high nibble of addr, and set phy_reg->new_reg_req */ val =3D phy_reg->new_reg_req | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); - writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + phy_reg->write(val, reg_gusb2phyacc0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return (char)ret; =20 - val =3D readl(reg_gusb2phyacc0); + val =3D phy_reg->read(reg_gusb2phyacc0); =20 return (char)(val & PHY_REG_DATA_MASK); } @@ -202,23 +219,23 @@ static int rtk_phy_write(struct phy_reg *phy_reg, cha= r addr, char data) /* write data to VStatusOut2 (data output to phy) */ writel((u32)data << shift_bits, reg_wrap_vstatus + phy_reg->vstatus_offse= t); =20 - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return ret; =20 /* VCtrl =3D low nibble of addr, set phy_reg->new_reg_req */ val =3D phy_reg->new_reg_req | (GET_LOW_NIBBLE(addr) << PHY_VCTRL_SHIFT); =20 - writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + phy_reg->write(val, reg_gusb2phyacc0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return ret; =20 /* VCtrl =3D high nibble of addr, set phy_reg->new_reg_req */ val =3D phy_reg->new_reg_req | (GET_HIGH_NIBBLE(addr) << PHY_VCTRL_SHIFT); =20 - writel(val, reg_gusb2phyacc0); - ret =3D utmi_wait_register(reg_gusb2phyacc0, phy_reg->vstatus_busy, 0); + phy_reg->write(val, reg_gusb2phyacc0); + ret =3D utmi_wait_register(phy_reg->read, reg_gusb2phyacc0, phy_reg->vsta= tus_busy, 0); if (ret) return ret; =20 @@ -984,6 +1001,8 @@ static int parse_phy_data(struct rtk_phy *rtk_phy) phy_parameter->phy_reg.vstatus_offset =3D phy_cfg->vstatus_offset; phy_parameter->phy_reg.vstatus_busy =3D phy_cfg->vstatus_busy; phy_parameter->phy_reg.new_reg_req =3D phy_cfg->new_reg_req; + phy_parameter->phy_reg.read =3D phy_cfg->read; + phy_parameter->phy_reg.write =3D phy_cfg->write; =20 if (of_property_read_bool(np, "realtek,inverse-hstx-sync-clock")) phy_parameter->inverse_hstx_sync_clock =3D true; @@ -1098,6 +1117,8 @@ static const struct phy_cfg rtd1295_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1395_phy_cfg =3D { @@ -1125,6 +1146,8 @@ static const struct phy_cfg rtd1395_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1395_phy_cfg_2port =3D { @@ -1152,6 +1175,8 @@ static const struct phy_cfg rtd1395_phy_cfg_2port =3D= { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1619_phy_cfg =3D { @@ -1177,6 +1202,8 @@ static const struct phy_cfg rtd1619_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1319_phy_cfg =3D { @@ -1206,6 +1233,8 @@ static const struct phy_cfg rtd1319_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1312c_phy_cfg =3D { @@ -1234,6 +1263,8 @@ static const struct phy_cfg rtd1312c_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1619b_phy_cfg =3D { @@ -1262,6 +1293,8 @@ static const struct phy_cfg rtd1619b_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1319d_phy_cfg =3D { @@ -1290,6 +1323,8 @@ static const struct phy_cfg rtd1319d_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct phy_cfg rtd1315e_phy_cfg =3D { @@ -1319,6 +1354,8 @@ static const struct phy_cfg rtd1315e_phy_cfg =3D { .vstatus_offset =3D 0, .vstatus_busy =3D PHY_VSTS_BUSY, .new_reg_req =3D PHY_NEW_REG_REQ, + .read =3D rtk_usb2phy_read, + .write =3D rtk_usb2phy_write, }; =20 static const struct of_device_id usbphy_rtk_dt_match[] =3D { --=20 2.53.0 From nobody Fri Jun 19 23:22:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CF043C3C08; Mon, 20 Apr 2026 19:20:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776712820; cv=none; b=PJ8L9LkaKzQ4W6us+c8lgDcYhEAfkauzDnVqlO71I3bG7I7L5M8qCXDkZN/VYkL4H/ObfE7zUEVxgcNervpqcQy5RjmnhvXFJT4iK4RVPlatH9qnHcHwdPsqbhG9kIrqvmVsCQMNemoEARXoHwd8JqQceKtzDklw1RULMFATRZg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776712820; c=relaxed/simple; bh=f9s72veV302u0cDA0XC5ArjgV/PXcnfDIUMvghXl40c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=N63QeVI8OiOhGCXJOPyIgA75Yml1lWoeTNlP4wc99KA8tG8UTMebnhFbsx6Ua0UCUdlaZlGF8DPz6dfmM1riQXYts0B53zkfFl9IQKTbIi0fFnKXpVrUUzZC6Hr8idZ2+RJ80Xs7KjsYA2RctA8TTH7b34PR+FmTc1ZhtwzXzxQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=LHDWL5ZD; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="LHDWL5ZD" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id E8F3026F22; Mon, 20 Apr 2026 21:20:14 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id pFDcml-QG7wp; Mon, 20 Apr 2026 21:20:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776712814; bh=f9s72veV302u0cDA0XC5ArjgV/PXcnfDIUMvghXl40c=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=LHDWL5ZD+sOqxKfpwbpzUTAriB1qnoe3N+hqxt2ifFPjgHMdhi/tIH8W9Hs1/1KQ+ DQPQQ9I5lOA4L187zS7m9r3/+z+LD+tyq2XW4STdYJjRynVzR5uTGPp9rmyC3NGZ3q kvfMrp9JoS0yrBNa8ear0lPmTVbVznYcpUj4jSq0uNQUCz8VJ7VAmKVqFSbnyqZYeu E2vQuvOL3Yagd+fq5hn5aiMhyKBvY8tpbmkgHnLlDYwb/DXGZU/6FQOO6LkZ+A3OWj YT2NtRiMLamsRNTMHad5vRP2olfDG8apRCUFtzBPT6qalAUnerhYDZywyaYKrv8Nvb RoTRectGNN1ig== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov Subject: [PATCH v5 3/6] dt-bindings: phy: realtek,usb2phy.yaml: extend for resets and RTL9607C support Date: Tue, 21 Apr 2026 00:19:38 +0500 Message-ID: <20260420191941.81834-4-adilov@disroot.org> In-Reply-To: <20260420191941.81834-1-adilov@disroot.org> References: <20260420191941.81834-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the "realtek,rtl9607-usb2phy" compatible for USB2 PHY on the RTL9607C SoC series. Add a resets property to properties to describe the usb2phy reset line. In RTL9607C, USB2 PHY reset line is from "IP Enable controller" which is multipurpose and handle activating various SoC peripherals. It is unclear whether RTD SoCs have something similar to that so set the resets to false for these devices. RTL9607C requires the "resets" to be specified so add the corresponding if check for the "realtek,rtl9607-usb2phy" compatible. Signed-off-by: Rustam Adilov --- .../bindings/phy/realtek,usb2phy.yaml | 25 ++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/realtek,usb2phy.yaml b/D= ocumentation/devicetree/bindings/phy/realtek,usb2phy.yaml index 9911ada39ee7..7b50833c8e19 100644 --- a/Documentation/devicetree/bindings/phy/realtek,usb2phy.yaml +++ b/Documentation/devicetree/bindings/phy/realtek,usb2phy.yaml @@ -11,7 +11,8 @@ maintainers: - Stanley Chang =20 description: | - Realtek USB 2.0 PHY support the digital home center (DHC) RTD series SoC= s. + Realtek USB 2.0 PHY support the digital home center (DHC) RTD and + RTL9607C series SoCs. The USB 2.0 PHY driver is designed to support the XHCI controller. The S= oCs support multiple XHCI controllers. One PHY device node maps to one XHCI controller. @@ -57,6 +58,12 @@ description: | XHCI controller#1 -- usb2phy -- phy#0 XHCI controller#2 -- usb2phy -- phy#0 =20 + RTL9607C SoCs USB + The USB architecture includes OHCI and EHCI controllers. + Both of them map to one USB2.0 PHY. + OHCI controller#0 -- usb2phy -- phy#0 + EHCI controller#0 -- usb2phy -- phy#0 + properties: compatible: enum: @@ -69,6 +76,7 @@ properties: - realtek,rtd1395-usb2phy-2port - realtek,rtd1619-usb2phy - realtek,rtd1619b-usb2phy + - realtek,rtl9607-usb2phy =20 reg: items: @@ -130,6 +138,9 @@ properties: minimum: -8 maximum: 8 =20 + resets: + maxItems: 1 + required: - compatible - reg @@ -157,6 +168,18 @@ allOf: then: properties: realtek,driving-level-compensate: false + - if: + properties: + compatible: + contains: + enum: + - realtek,rtl9607-usb2phy + then: + required: + - resets + else: + properties: + resets: false =20 additionalProperties: false =20 --=20 2.53.0 From nobody Fri Jun 19 23:22:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A1D06382378; Mon, 20 Apr 2026 19:20:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776712822; cv=none; b=oJGYzCz7/9wVAEr3o70dGyHVB5p0iDreDXR3xsBuM7p3pyEpTvtKDmF22F/+CngfpJNZaxTyfmaiKmrKFALlUd6NmqLKwMTdI/9OLxlgmlNOMjeNE7DHrOlv43szFv75By7LUeJdvJ0WqxS3pI/RQjzXy7OgJ5BHWPKbVKerNCs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776712822; c=relaxed/simple; bh=I4bAzl1GDu2wOCTjoJs7Sz/xGm5YwQN59J/ybBhb/EQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Y0T0pOjVVA1WEZ/+E+HtqjIbzVJ+kcZ59dOttkq5ICedRLceoSLrruKp9sgwvJNrTTC3cxjYYTmcrQuFfxzfStnwPfiZpRCzV4LMkELbFaAT0YK7xH7F0oQz5j7DvDGzYAmss9Np4gXKjQ0tnE5TwkN6c4INV4D6vFuAOOvs31w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=VQxKa7Wr; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="VQxKa7Wr" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 162AE27011; Mon, 20 Apr 2026 21:20:18 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id VetugQQBQRKD; Mon, 20 Apr 2026 21:20:17 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776712817; bh=I4bAzl1GDu2wOCTjoJs7Sz/xGm5YwQN59J/ybBhb/EQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=VQxKa7WrEBkGgFrKO/Y78/ce4S7uJivyZVkvZSGNCt5aSScP2rouohgZ+bwRvvr9N 2kvNEUe8OHKyS9Co2k9U4HOD5X9g+CjRKWmMIIuQ+yaGP5A3UiopKkmn1VdreuzBHT Ntb9eJaDLZgKaCcYZAvFvgq7QhMSpYBevuP3SXhBLhq4Kty5Hm7rIA79iZykJZx47t 83vaoClW+Sm3T5Z++ehaZxv55Mjg+PjxKIqhR2rz2UPQ+yTUmgKhdP0Iv/0vTzZXjY TrO7nMihHWmRwqKiqsJ2GXHGTn4JM18lfLSR1yctJ4V3HEo+5VlsihLfKi92uCoAFv 7Z194FC/CLHhw== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov , Michael Zavertkin Subject: [PATCH v5 4/6] phy: realtek: usb2: introduce reset controller struct Date: Tue, 21 Apr 2026 00:19:39 +0500 Message-ID: <20260420191941.81834-5-adilov@disroot.org> In-Reply-To: <20260420191941.81834-1-adilov@disroot.org> References: <20260420191941.81834-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In RTL9607C, there is so called "IP Enable Controller" which resemble reset controller with reset lines and is used for various things like USB, PCIE, GMAC and such. Introduce the reset_control struct to this driver to handle deasserting usb2 phy reset line. Make use of the function devm_reset_control_array_get_optional_exclusive() function to get the reset controller and since existing RTD SoCs don't specify the resets we can have a cleaner code. Since the vendor usb driver developed by Realtek doesn't assert the reset line (or in their case clear the register bit), we can reasonably assume reset_control_assert is not needed here. Co-developed-by: Michael Zavertkin Signed-off-by: Michael Zavertkin Signed-off-by: Rustam Adilov --- drivers/phy/realtek/phy-rtk-usb2.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-r= tk-usb2.c index 19297a42a841..aaa07a69224a 100644 --- a/drivers/phy/realtek/phy-rtk-usb2.c +++ b/drivers/phy/realtek/phy-rtk-usb2.c @@ -17,6 +17,7 @@ #include #include #include +#include #include =20 /* GUSB2PHYACCn register */ @@ -130,6 +131,7 @@ struct rtk_phy { struct phy_cfg *phy_cfg; int num_phy; struct phy_parameter *phy_parameter; + struct reset_control *phy_rst; =20 struct dentry *debug_dir; }; @@ -676,6 +678,15 @@ static int rtk_phy_init(struct phy *phy) if (!rtk_phy) return -EINVAL; =20 + if (rtk_phy->phy_rst) { + ret =3D reset_control_deassert(rtk_phy->phy_rst); + + if (ret) + return ret; + + usleep_range(5000, 6000); + } + for (i =3D 0; i < rtk_phy->num_phy; i++) ret =3D do_rtk_phy_init(rtk_phy, i); =20 @@ -1059,6 +1070,11 @@ static int rtk_usb2phy_probe(struct platform_device = *pdev) =20 rtk_phy->num_phy =3D phy_cfg->num_phy; =20 + rtk_phy->phy_rst =3D devm_reset_control_array_get_optional_exclusive(dev); + if (IS_ERR(rtk_phy->phy_rst)) + return dev_err_probe(dev, PTR_ERR(rtk_phy->phy_rst), + "usb2 phy resets are not working\n"); + ret =3D parse_phy_data(rtk_phy); if (ret) goto err; --=20 2.53.0 From nobody Fri Jun 19 23:22:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 363FE3C4565; Mon, 20 Apr 2026 19:20:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776712825; cv=none; b=snT41Bnta513XLVc9bXZ4f9f0eTIP0oDTwYqo6Sci9rpgrIemL5g34GUjTSgQ6uEkgAFYz3IhcF7ukKuSqUwwKGxCRv5AycO4UP0VWqeTwiHBrIujqlOpDqry+LuYAKskYlkBIxzfPuz3gkVLg9Mp65PnDtnVcmwguh9/i7l35Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776712825; c=relaxed/simple; bh=daxptYU8HlXdVQlCPKqv2iutTKO/3+o3g3ChmcjZbdM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cSdScJBNl5EPdXfqdLlyn+BkzENmtxRHTSE3rJrVGHikIx0JSiOv30wJBcXYUJFjmcYUqRhdugrLXmMUAS/QX/jnYhpJGl3f7H9PIFvdvPOBJKdFjeyimpqHk5MIKUv0R+ZYYQTCTkRZ1JaPslsqNJTJ9OV5OEnHFdmRWxe+q3w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=Qp6iPuhQ; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="Qp6iPuhQ" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id B3BDD26F19; Mon, 20 Apr 2026 21:20:20 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id 0wy79rXnQk12; Mon, 20 Apr 2026 21:20:20 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776712820; bh=daxptYU8HlXdVQlCPKqv2iutTKO/3+o3g3ChmcjZbdM=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Qp6iPuhQlcNn3ZmHa0O6KenLeV8byoVcD1/vX/NC4KCkw7Y2aE30Rdk1WLls9YHq2 6ch8lhJSGNGT+AOsQy63FUNkP4FF+/GlqSfU/x9GBxH3X8RFQ93CWAnUECPA32sWX1 QK/A8r8cUxjOEccrTEcx28XYk5R7ylMNvKHMxdbrPO0p9Jt9mEvLVoY/ea/8QyollO XP6ymdq/+Gy3duksC/cfhyi4M2Wz9zGaM6cc4izFKBAl6KVXyR7J6n0IYLkcAD74t1 HDFs9x23mtjYnSUywwuRtC6lgdcdx/zxudouWCZ5FFy0m2MadruDPFkfIS7yeWUlV2 ZkNHifJnJrSgg== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov , Michael Zavertkin Subject: [PATCH v5 5/6] phy: realtek: usb2: add support for RTL9607C USB2 PHY Date: Tue, 21 Apr 2026 00:19:40 +0500 Message-ID: <20260420191941.81834-6-adilov@disroot.org> In-Reply-To: <20260420191941.81834-1-adilov@disroot.org> References: <20260420191941.81834-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the usb2 phy of RTL9607C series based SoCs. Add the macros and phy config struct for rtl9607. RTL9607C requires to clear a "force host disconnect" bit in the specific register (which is at an offset from reg_wrap_vstatus) before proceeding with phy parameter writes. Since it belongs into the vstatus register region, it doesn't need bytes swapping. Add the bool variable to the driver data struct and hide this whole procedure under the if statement that checks this new variable. Add the appropriate little endian read and write functions for rtl9607 and assign them to its phy config struct. As mentioned earlier, the readl/writel are native endian on MIPS arch if SWAP_IO_SPACE is not enabled. Since enabling SWAP_IO_SPACE results in boot hang on RTL9607C machine, wrapping le32 around readl/writel should be a good compromise, but swab32 could be also work. Co-developed-by: Michael Zavertkin Signed-off-by: Michael Zavertkin Signed-off-by: Rustam Adilov --- drivers/phy/realtek/phy-rtk-usb2.c | 57 ++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/phy/realtek/phy-rtk-usb2.c b/drivers/phy/realtek/phy-r= tk-usb2.c index aaa07a69224a..7671f8a9ff61 100644 --- a/drivers/phy/realtek/phy-rtk-usb2.c +++ b/drivers/phy/realtek/phy-rtk-usb2.c @@ -26,6 +26,12 @@ #define PHY_VCTRL_SHIFT 8 #define PHY_REG_DATA_MASK 0xff =20 +#define PHY_9607_VSTS_BUSY BIT(17) +#define PHY_9607_NEW_REG_REQ BIT(13) + +#define PHY_9607_FORCE_DISCONNECT_REG 0x10 +#define PHY_9607_FORCE_DISCONNECT_BIT BIT(5) + #define GET_LOW_NIBBLE(addr) ((addr) & 0x0f) #define GET_HIGH_NIBBLE(addr) (((addr) & 0xf0) >> 4) =20 @@ -109,6 +115,7 @@ struct phy_cfg { =20 u32 (*read)(void __iomem *reg); void (*write)(u32 val, void __iomem *reg); + bool force_host_disconnect; }; =20 struct phy_parameter { @@ -146,6 +153,18 @@ static void rtk_usb2phy_write(u32 val, void __iomem *r= eg) writel(val, reg); } =20 +static u32 rtk_usb2phy_read_le(void __iomem *reg) +{ + return le32_to_cpu(readl(reg)); +} + +static void rtk_usb2phy_write_le(u32 val, void __iomem *reg) +{ + u32 tmp =3D cpu_to_le32(val); + + writel(tmp, reg); +} + /* mapping 0xE0 to 0 ... 0xE7 to 7, 0xF0 to 8 ,,, 0xF7 to 15 */ static inline int page_addr_to_array_index(u8 addr) { @@ -600,6 +619,16 @@ static int do_rtk_phy_init(struct rtk_phy *rtk_phy, in= t index) goto do_toggle; } =20 + if (phy_cfg->force_host_disconnect) { + /* disable force-host-disconnect */ + u32 temp =3D readl(phy_reg->reg_wrap_vstatus + PHY_9607_FORCE_DISCONNECT= _REG); + + temp &=3D ~PHY_9607_FORCE_DISCONNECT_BIT; + writel(temp, phy_reg->reg_wrap_vstatus + PHY_9607_FORCE_DISCONNECT_REG); + + msleep(10); + } + /* Set page 0 */ phy_data_page =3D phy_cfg->page0; rtk_phy_set_page(phy_reg, 0); @@ -1374,6 +1403,33 @@ static const struct phy_cfg rtd1315e_phy_cfg =3D { .write =3D rtk_usb2phy_write, }; =20 +static const struct phy_cfg rtl9607_phy_cfg =3D { + .page0_size =3D MAX_USB_PHY_PAGE0_DATA_SIZE, + .page0 =3D { [0] =3D {0xe0, 0x95}, + [4] =3D {0xe4, 0x6a}, + [12] =3D {0xf3, 0x31}, }, + .page1_size =3D MAX_USB_PHY_PAGE1_DATA_SIZE, + .page1 =3D { [0] =3D {0xe0, 0x26}, }, + .page2_size =3D MAX_USB_PHY_PAGE2_DATA_SIZE, + .page2 =3D { [7] =3D {0xe7, 0x33}, }, + .num_phy =3D 1, + .check_efuse_version =3D CHECK_EFUSE_V2, + .efuse_dc_driving_rate =3D EFUS_USB_DC_CAL_RATE, + .dc_driving_mask =3D 0x1f, + .efuse_dc_disconnect_rate =3D EFUS_USB_DC_DIS_RATE, + .dc_disconnect_mask =3D 0xf, + .usb_dc_disconnect_at_page0 =3D true, + .do_toggle =3D true, + .driving_updated_for_dev_dis =3D 0x8, + .is_double_sensitivity_mode =3D true, + .vstatus_offset =3D 0xc, + .vstatus_busy =3D PHY_9607_VSTS_BUSY, + .new_reg_req =3D PHY_9607_NEW_REG_REQ, + .read =3D rtk_usb2phy_read_le, + .write =3D rtk_usb2phy_write_le, + .force_host_disconnect =3D true, +}; + static const struct of_device_id usbphy_rtk_dt_match[] =3D { { .compatible =3D "realtek,rtd1295-usb2phy", .data =3D &rtd1295_phy_cfg }, { .compatible =3D "realtek,rtd1312c-usb2phy", .data =3D &rtd1312c_phy_cfg= }, @@ -1384,6 +1440,7 @@ static const struct of_device_id usbphy_rtk_dt_match[= ] =3D { { .compatible =3D "realtek,rtd1395-usb2phy-2port", .data =3D &rtd1395_phy= _cfg_2port }, { .compatible =3D "realtek,rtd1619-usb2phy", .data =3D &rtd1619_phy_cfg }, { .compatible =3D "realtek,rtd1619b-usb2phy", .data =3D &rtd1619b_phy_cfg= }, + { .compatible =3D "realtek,rtl9607-usb2phy", .data =3D &rtl9607_phy_cfg }, {}, }; MODULE_DEVICE_TABLE(of, usbphy_rtk_dt_match); --=20 2.53.0 From nobody Fri Jun 19 23:22:45 2026 Received: from layka.disroot.org (layka.disroot.org [178.21.23.139]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 387893C457F; Mon, 20 Apr 2026 19:20:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.21.23.139 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776712828; cv=none; b=Jg6wK5b1U5D4noup4OnaWvEexQoEEpgDL1TDNH8aBcXLjcZ/WW5woeTqqcaNGM4WUwHrqNUbQqbB5tIb396FiOM6jCl44nm4XiYqH6D/H3A2vdq2EjdUfYauQ0NfQgqzLEMuLV8Fnvc10JsexQnRhNAW715ObzmnSsRF703aOz4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776712828; c=relaxed/simple; bh=Fsbxr1KoI6nvNJg1iQcsK0ER51AzQq33E2rDDFIUpTE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GU2q9zfDOysba9Moi8zs27Mclpb7WDbzSOlHHTQiTe4h18JTAGMby6zucW1g4i87MygV2p1FxwnVqzigtks/00bMzzxrGRh1G56Id4hbvOrw0Xx3dMf2WbqnFoOJcx9sBvbJsLJdwXvvJPsnjDJ4zy8SDko6kL7NIuz+g5im1Rw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org; spf=pass smtp.mailfrom=disroot.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b=aInaYlC/; arc=none smtp.client-ip=178.21.23.139 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=disroot.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=disroot.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=disroot.org header.i=@disroot.org header.b="aInaYlC/" Received: from mail01.disroot.lan (localhost [127.0.0.1]) by disroot.org (Postfix) with ESMTP id 8962926F22; Mon, 20 Apr 2026 21:20:23 +0200 (CEST) X-Virus-Scanned: SPAM Filter at disroot.org Received: from layka.disroot.org ([127.0.0.1]) by localhost (disroot.org [127.0.0.1]) (amavis, port 10024) with ESMTP id zyzU4oivZufu; Mon, 20 Apr 2026 21:20:23 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=disroot.org; s=mail; t=1776712823; bh=Fsbxr1KoI6nvNJg1iQcsK0ER51AzQq33E2rDDFIUpTE=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=aInaYlC/7dzZhmMg15U1Ny2/11f4aKXfT2xj6SVuqjjVt90OwEDAL+TsUNj/ZEibn Fv+qYgTfg4gdUWrdyjWfJp/nxaXur27nk9BSlD9y9Cf3rugzQmvJBQ3WHL7NCEAPKx Rib6wVsFFv0PNICLtCCgXYJAzTmQFBWhdC1uf3MHtwHILeAtP1xIQYSF8dt9oK6Z4n JnGgieWjAciESDw+1vTlZE0sYSzW7778w+pXwAUkcwCAYfIvkxBe1lK7sFYnuouEZm /uKSB98u9V7CwrpUgN84jQiTRozt6p4d+DFCGdsA9KGzT7KXkdh3q806Rh6xmwAoZi BAuKg051yH3jg== From: Rustam Adilov To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanley Chang , linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Rustam Adilov Subject: [PATCH v5 6/6] phy: realtek: Make configs available for MACH_REALTEK_RTL Date: Tue, 21 Apr 2026 00:19:41 +0500 Message-ID: <20260420191941.81834-7-adilov@disroot.org> In-Reply-To: <20260420191941.81834-1-adilov@disroot.org> References: <20260420191941.81834-1-adilov@disroot.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add the MACH_REALTEK_RTL to the if statement to make the config options available for Realtek RTL SoCs as well. Signed-off-by: Rustam Adilov --- drivers/phy/realtek/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/realtek/Kconfig b/drivers/phy/realtek/Kconfig index 75ac7e7c31ae..76f9215d8b94 100644 --- a/drivers/phy/realtek/Kconfig +++ b/drivers/phy/realtek/Kconfig @@ -3,7 +3,7 @@ # Phy drivers for Realtek platforms # =20 -if ARCH_REALTEK || COMPILE_TEST +if ARCH_REALTEK || MACH_REALTEK_RTL || COMPILE_TEST =20 config PHY_RTK_RTD_USB2PHY tristate "Realtek RTD USB2 PHY Transceiver Driver" @@ -29,4 +29,4 @@ config PHY_RTK_RTD_USB3PHY DWC3 USB IP. This driver will do the PHY initialization of the parameters. =20 -endif # ARCH_REALTEK || COMPILE_TEST +endif # ARCH_REALTEK || MACH_REALTEK_RTL || COMPILE_TEST --=20 2.53.0