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charset="utf-8" According to user manual / programming guide there is no separate PCIe phy 3A and 3B, but one 8-lane QMP PCIe Gen5 PHY which consists of two 4-lane blocks. This is also visible in memory map, where the 0xf00000 is marked as the main block with additional sub blocks for each 4-lane phys. Describing the sub phys without the rest is not correct from hardware description, even if it works. Link: https://lore.kernel.org/r/20260420-optimistic-unnatural-stingray-80da= 35@quoll/ Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 5 --- arch/arm64/boot/dts/qcom/glymur.dtsi | 39 +----------------------- 2 files changed, 1 insertion(+), 43 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts= /qcom/glymur-crd.dtsi index 2852d257ac8c..647e934f4edc 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -440,11 +440,6 @@ &pcie3b { pinctrl-names =3D "default"; }; =20 -&pcie3b_phy { - vdda-phy-supply =3D <&vreg_l3c_e1_0p89>; - vdda-pll-supply =3D <&vreg_l2c_e1_1p14>; -}; - &pcie3b_port0 { reset-gpios =3D <&tlmm 155 GPIO_ACTIVE_LOW>; wake-gpios =3D <&tlmm 157 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qco= m/glymur.dtsi index f23cf81ddb77..d5408bd3a389 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -737,7 +737,7 @@ gcc: clock-controller@100000 { <0>, /* USB 2 Phy PIPEGMUX */ <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ <0>, /* PCIe 3a */ - <&pcie3b_phy>, /* PCIe 3b */ + <0>, /* PCIe 3b */ <&pcie4_phy>, /* PCIe 4 */ <&pcie5_phy>, /* PCIe 5 */ <&pcie6_phy>, /* PCIe 6 */ @@ -3632,49 +3632,12 @@ pcie3b_port0: pcie@0 { reg =3D <0x0 0x0 0x0 0x0 0x0>; bus-range =3D <0x01 0xff>; =20 - phys =3D <&pcie3b_phy>; - #address-cells =3D <3>; #size-cells =3D <2>; ranges; }; }; =20 - pcie3b_phy: phy@f10000 { - compatible =3D "qcom,glymur-qmp-gen5x4-pcie-phy"; - reg =3D <0x0 0x00f10000 0x0 0x10000>; - - clocks =3D <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, - <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, - <&tcsr TCSR_PCIE_3_CLKREF_EN>, - <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_3B_PIPE_CLK>, - <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; - clock-names =3D "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - resets =3D <&gcc GCC_PCIE_3B_PHY_BCR>, - <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; - reset-names =3D "phy", - "phy_nocsr"; - - assigned-clocks =3D <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; - assigned-clock-rates =3D <100000000>; - - power-domains =3D <&gcc GCC_PCIE_3B_PHY_GDSC>; - - #clock-cells =3D <0>; - clock-output-names =3D "pcie3b_pipe_clk"; - - #phy-cells =3D <0>; - - status =3D "disabled"; - }; - tcsr_mutex: hwlock@1f40000 { compatible =3D "qcom,tcsr-mutex"; reg =3D <0x0 0x01f40000 0x0 0x20000>; --=20 2.51.0