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charset="utf-8" Convert the LPASS LPI pinctrl driver to use the PM clock framework for runtime power management. This allows the LPASS LPI pinctrl driver to drop clock votes when idle, improves power efficiency on platforms using LPASS LPI island mode, and aligns the driver with common runtime PM patterns used across Qualcomm LPASS subsystems. Signed-off-by: Ajay Kumar Nandam --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 22 +++++++++---------- .../pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 7 ++++++ 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 76aed3296279..2b0956ff2ae0 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -15,6 +15,8 @@ #include #include #include +#include +#include =20 #include "../pinctrl-utils.h" =20 @@ -22,7 +24,6 @@ =20 #define MAX_NR_GPIO 32 #define GPIO_FUNC 0 -#define MAX_LPI_NUM_CLKS 2 =20 struct lpi_pinctrl { struct device *dev; @@ -31,7 +32,6 @@ struct lpi_pinctrl { struct pinctrl_desc desc; char __iomem *tlmm_base; char __iomem *slew_base; - struct clk_bulk_data clks[MAX_LPI_NUM_CLKS]; /* Protects from concurrent register updates */ struct mutex lock; DECLARE_BITMAP(ever_gpio, MAX_NR_GPIO); @@ -480,9 +480,6 @@ int lpi_pinctrl_probe(struct platform_device *pdev) pctrl->data =3D data; pctrl->dev =3D &pdev->dev; =20 - pctrl->clks[0].id =3D "core"; - pctrl->clks[1].id =3D "audio"; - pctrl->tlmm_base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pctrl->tlmm_base)) return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), @@ -495,13 +492,17 @@ int lpi_pinctrl_probe(struct platform_device *pdev) "Slew resource not provided\n"); } =20 - ret =3D devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); + ret =3D devm_pm_clk_create(dev); if (ret) return ret; =20 - ret =3D clk_bulk_prepare_enable(MAX_LPI_NUM_CLKS, pctrl->clks); - if (ret) - return dev_err_probe(dev, ret, "Can't enable clocks\n"); + ret =3D of_pm_clk_add_clks(dev); + if (ret < 0) + return ret; + + pm_runtime_set_autosuspend_delay(dev, 100); + pm_runtime_use_autosuspend(dev); + devm_pm_runtime_enable(dev); =20 pctrl->desc.pctlops =3D &lpi_gpio_pinctrl_ops; pctrl->desc.pmxops =3D &lpi_gpio_pinmux_ops; @@ -539,8 +540,8 @@ int lpi_pinctrl_probe(struct platform_device *pdev) return 0; =20 err_pinctrl: + pm_runtime_disable(dev); mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); =20 return ret; } @@ -552,7 +553,6 @@ void lpi_pinctrl_remove(struct platform_device *pdev) int i; =20 mutex_destroy(&pctrl->lock); - clk_bulk_disable_unprepare(MAX_LPI_NUM_CLKS, pctrl->clks); =20 for (i =3D 0; i < pctrl->data->npins; i++) pinctrl_generic_remove_group(pctrl->ctrl, i); diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sc7280-lpass-lpi.c index 750f410311a8..64a200dd8f41 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -139,10 +141,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sc7280-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, --=20 2.34.1 From nobody Tue Jun 16 14:55:10 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1E9D33A0EB1 for ; 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charset="utf-8" The LPASS LPI core was switched to the PM clock framework and runtime PM, but only the sc7280 variant driver wired runtime PM callbacks. Hook up runtime PM callbacks for the remaining LPASS LPI variant drivers so all SoCs using the common core get consistent pm_clk based clock handling: - sc8280xp - sm4250 - sm6115 - sm8250 - sm8450 - sm8550 - sm8650 This is a mechanical per-variant driver update that relies on the same generic PM clock flow (of_pm_clk_add_clks() + pm_clk_suspend/ pm_clk_resume()) and DT-provided clocks. Runtime behavior was validated on Kodiak (sc7280). Signed-off-by: Ajay Kumar Nandam --- drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 7 +++++++ drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c | 11 +++++++++-- drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c | 11 +++++++++-- 7 files changed, 59 insertions(+), 10 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pi= nctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c index 0e839b6aaaf4..1a61316c8c47 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -173,10 +175,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sc8280xp-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sc8280xp-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm4250-lpass-lpi.c index c0e178be9cfc..75bafa62426a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -221,10 +223,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sm4250-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm6115-lpass-lpi.c index b7d9186861a2..05435ea6e17a 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -141,10 +143,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { .name =3D "qcom-sm6115-lpass-lpi-pinctrl", .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8250-lpass-lpi.c index c27452eece3e..656f22da7dde 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c @@ -7,6 +7,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -134,10 +136,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8250-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8250-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8450-lpass-lpi.c index 439f6541622e..a79f99ec6df9 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -202,10 +204,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8450-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8450-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8550-lpass-lpi.c index 73065919c8c2..9037ef0020da 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -210,10 +212,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8550-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8550-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8650-lpass-lpi.c index f9fcedf5a65d..513ddc99dd37 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c @@ -6,6 +6,8 @@ #include #include #include +#include +#include =20 #include "pinctrl-lpass-lpi.h" =20 @@ -217,10 +219,15 @@ static const struct of_device_id lpi_pinctrl_of_match= [] =3D { }; MODULE_DEVICE_TABLE(of, lpi_pinctrl_of_match); =20 +static const struct dev_pm_ops lpi_pinctrl_pm_ops =3D { + RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL) +}; + static struct platform_driver lpi_pinctrl_driver =3D { .driver =3D { - .name =3D "qcom-sm8650-lpass-lpi-pinctrl", - .of_match_table =3D lpi_pinctrl_of_match, + .name =3D "qcom-sm8650-lpass-lpi-pinctrl", + .of_match_table =3D lpi_pinctrl_of_match, + .pm =3D pm_ptr(&lpi_pinctrl_pm_ops), }, .probe =3D lpi_pinctrl_probe, .remove =3D lpi_pinctrl_remove, --=20 2.34.1 From nobody Tue Jun 16 14:55:10 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4339D3A16A0 for ; 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charset="utf-8" Ensure the LPI pinctrl device clocks are runtime resumed before accessing GPIO registers and autosuspended after the access completes. Guard GPIO register read and write helpers with synchronous runtime PM calls so the device is active during MMIO operations. Signed-off-by: Ajay Kumar Nandam --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 26 ++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 2b0956ff2ae0..75ae21478fa4 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -38,32 +38,46 @@ struct lpi_pinctrl { const struct lpi_pinctrl_variant_data *data; }; =20 -static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, +static u32 lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr) { - u32 pin_offset; + u32 pin_offset, val; + int ret; =20 if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) pin_offset =3D state->data->groups[pin].pin_offset; else pin_offset =3D LPI_TLMM_REG_OFFSET * pin; =20 - return ioread32(state->tlmm_base + pin_offset + addr); + ret =3D pm_runtime_resume_and_get(state->dev); + if (ret < 0) + return 0; + + val =3D ioread32(state->tlmm_base + pin_offset + addr); + pm_runtime_put_autosuspend(state->dev); + + return val; } =20 -static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, - unsigned int addr, unsigned int val) +static void lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, + unsigned int addr, unsigned int val) { u32 pin_offset; + int ret; =20 if (state->data->flags & LPI_FLAG_USE_PREDEFINED_PIN_OFFSET) pin_offset =3D state->data->groups[pin].pin_offset; else pin_offset =3D LPI_TLMM_REG_OFFSET * pin; =20 + ret =3D pm_runtime_resume_and_get(state->dev); + if (ret < 0) + return; + iowrite32(val, state->tlmm_base + pin_offset + addr); + pm_runtime_put_autosuspend(state->dev); =20 - return 0; + return; } =20 static const struct pinctrl_ops lpi_gpio_pinctrl_ops =3D { --=20 2.34.1