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This is useful for multi-channel devices that have multiple backends, where looking up by index is more straightforward than using named backends. Extract __devm_iio_backend_fwnode_get_by_index() from the existing __devm_iio_backend_fwnode_get(), taking the index directly as a parameter. The new public API devm_iio_backend_get_by_index() uses the index to find the backend reference in the io-backends property, avoiding the need for io-backend-names. Reviewed-by: David Lechner Reviewed-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- Changes in v9: - No changes drivers/iio/industrialio-backend.c | 53 +++++++++++++++++++++--------- include/linux/iio/backend.h | 1 + 2 files changed, 39 insertions(+), 15 deletions(-) diff --git a/drivers/iio/industrialio-backend.c b/drivers/iio/industrialio-= backend.c index 10e689f49441..138ebebc9c0d 100644 --- a/drivers/iio/industrialio-backend.c +++ b/drivers/iio/industrialio-backend.c @@ -964,23 +964,13 @@ int iio_backend_data_transfer_addr(struct iio_backend= *back, u32 address) } EXPORT_SYMBOL_NS_GPL(iio_backend_data_transfer_addr, "IIO_BACKEND"); =20 -static struct iio_backend *__devm_iio_backend_fwnode_get(struct device *de= v, const char *name, - struct fwnode_handle *fwnode) +static struct iio_backend *__devm_iio_backend_fwnode_get_by_index(struct d= evice *dev, + struct fwnode_handle *fwnode, + unsigned int index) { struct iio_backend *back; - unsigned int index; int ret; =20 - if (name) { - ret =3D device_property_match_string(dev, "io-backend-names", - name); - if (ret < 0) - return ERR_PTR(ret); - index =3D ret; - } else { - index =3D 0; - } - struct fwnode_handle *fwnode_back __free(fwnode_handle) =3D fwnode_find_reference(fwnode, "io-backends", index); if (IS_ERR(fwnode_back)) @@ -996,8 +986,7 @@ static struct iio_backend *__devm_iio_backend_fwnode_ge= t(struct device *dev, con if (ret) return ERR_PTR(ret); =20 - if (name) - back->idx =3D index; + back->idx =3D index; =20 return back; } @@ -1005,6 +994,24 @@ static struct iio_backend *__devm_iio_backend_fwnode_= get(struct device *dev, con return ERR_PTR(-EPROBE_DEFER); } =20 +static struct iio_backend *__devm_iio_backend_fwnode_get(struct device *de= v, const char *name, + struct fwnode_handle *fwnode) +{ + unsigned int index; + int ret; + + if (name) { + ret =3D device_property_match_string(dev, "io-backend-names", name); + if (ret < 0) + return ERR_PTR(ret); + index =3D ret; + } else { + index =3D 0; + } + + return __devm_iio_backend_fwnode_get_by_index(dev, fwnode, index); +} + /** * devm_iio_backend_get - Device managed backend device get * @dev: Consumer device for the backend @@ -1021,6 +1028,22 @@ struct iio_backend *devm_iio_backend_get(struct devi= ce *dev, const char *name) } EXPORT_SYMBOL_NS_GPL(devm_iio_backend_get, "IIO_BACKEND"); =20 +/** + * devm_iio_backend_get_by_index - Device managed backend device get by in= dex + * @dev: Consumer device for the backend + * @index: Index of the backend in the io-backends property + * + * Gets the backend at @index associated with @dev. + * + * RETURNS: + * A backend pointer, negative error pointer otherwise. + */ +struct iio_backend *devm_iio_backend_get_by_index(struct device *dev, unsi= gned int index) +{ + return __devm_iio_backend_fwnode_get_by_index(dev, dev_fwnode(dev), index= ); +} +EXPORT_SYMBOL_NS_GPL(devm_iio_backend_get_by_index, "IIO_BACKEND"); + /** * devm_iio_backend_fwnode_get - Device managed backend firmware node get * @dev: Consumer device for the backend diff --git a/include/linux/iio/backend.h b/include/linux/iio/backend.h index 4d15c2a9802c..3f95ed1fdf9e 100644 --- a/include/linux/iio/backend.h +++ b/include/linux/iio/backend.h @@ -261,6 +261,7 @@ int iio_backend_extend_chan_spec(struct iio_backend *ba= ck, bool iio_backend_has_caps(struct iio_backend *back, u32 caps); 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charset="utf-8" Add support for the AD4880, a dual-channel 20-bit 40MSPS SAR ADC with integrated fully differential amplifiers (FDA). The AD4880 has two independent ADC channels, each with its own SPI configuration interface. This requires: - Two entries in reg property for primary and secondary channel chip selects - Two io-backends entries for the two data channels Acked-by: Conor Dooley Reviewed-by: David Lechner Signed-off-by: Antoniu Miclaus --- Changes in v9: - Add Conor's ack .../bindings/iio/adc/adi,ad4080.yaml | 53 ++++++++++++++++++- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad4080.yaml index 79df2696ef24..9c6a56c7c8ef 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml @@ -18,7 +18,11 @@ description: | service a wide variety of precision, wide bandwidth data acquisition applications. =20 + The AD4880 is a dual-channel variant with two independent ADC channels, + each with its own SPI configuration interface. + https://www.analog.com/media/en/technical-documentation/data-sheets/ad40= 80.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad48= 80.pdf =20 $ref: /schemas/spi/spi-peripheral-props.yaml# =20 @@ -34,9 +38,15 @@ properties: - adi,ad4086 - adi,ad4087 - adi,ad4088 + - adi,ad4880 =20 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 + description: + SPI chip select(s). For single-channel devices, one chip select. + For multi-channel devices like AD4880, two chip selects are required + as each channel has its own SPI configuration interface. =20 spi-max-frequency: description: Configuration of the SPI bus. @@ -60,7 +70,10 @@ properties: vrefin-supply: true =20 io-backends: - maxItems: 1 + minItems: 1 + items: + - description: Backend for channel A (primary) + - description: Backend for channel B (secondary) =20 adi,lvds-cnv-enable: description: Enable the LVDS signal type on the CNV pin. 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Mon, 20 Apr 2026 06:12:45 -0400 From: Antoniu Miclaus To: Lars-Peter Clausen , Michael Hennerich , Antoniu Miclaus , Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , , , Subject: [PATCH v9 3/3] iio: adc: ad4080: add support for AD4880 dual-channel ADC Date: Mon, 20 Apr 2026 13:12:25 +0300 Message-ID: <20260420101225.4173-4-antoniu.miclaus@analog.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260420101225.4173-1-antoniu.miclaus@analog.com> References: <20260420101225.4173-1-antoniu.miclaus@analog.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIwMDA5OSBTYWx0ZWRfX5j1zUuFYBtTu ch3HNnSzYBruzqt0wwSBSov3Q3KoRy2VPkxeikAEGTvL8Lr99h7wOO/mMqSTIUXyozQKL2YTCg9 2uhmjFzAN5/oI2uTkD7vnHfAr4XYHg+7KXE0xig88z+/9HLeWMm/fDEopOBpOvU2k+kRXQpReXu 6tvIF6L7Gd06UJZJcNsuQ14RyR8fPKjb9yrNO8NoDuZnOzjRad1tBgsCx9EYwC89fyI+btlUIp8 Cbsh6BxxANmYGHHOZT6F/NWIP+vwbO+8+LfMLu8Y0ysHGYHfQUzKCqeARYKDU0OBAnWQ9sHtxTS bfIRsE5Tt2BQ/1l2y7qHgAt7uivET0zivwX2ou5DCwFm4km88xNgFrVWohuoqw5cy6DaaTFM5Nv PekZNXpD1p2Bg2kldIi5b6jnOVIHEjTsixGMKziQYxjhiKTCicjL+0V6vlmy7W+eplfho3IBvP4 dXb2Ui+bxzqyI+afcvg== X-Authority-Analysis: v=2.4 cv=Oo1/DS/t c=1 sm=1 tr=0 ts=69e5fc26 cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=Z0pTeXoby7EwIRygza74:22 a=IpJZQVW2AAAA:8 a=gAnH3GRIAAAA:8 a=tTZA3VM7F9AdKBy-ZqoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=IawgGOuG5U0WyFbmm1f5:22 X-Proofpoint-ORIG-GUID: LfaLtC1iUgCeOJpAYcFWR3qQ0ffOaV_w X-Proofpoint-GUID: LfaLtC1iUgCeOJpAYcFWR3qQ0ffOaV_w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-20_02,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 malwarescore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 priorityscore=1501 clxscore=1015 adultscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604200099 Add support for the AD4880, a dual-channel 20-bit 40MSPS SAR ADC with integrated fully differential amplifiers (FDA). The AD4880 has two independent ADC channels, each with its own SPI configuration interface. The driver uses spi_new_ancillary_device() to create an additional SPI device for the second channel, allowing both channels to share the same SPI bus with different chip selects. Reviewed-by: David Lechner Reviewed-by: Nuno S=C3=A1 Signed-off-by: Antoniu Miclaus --- Changes in v9: - No changes drivers/iio/adc/ad4080.c | 257 +++++++++++++++++++++++++++++---------- 1 file changed, 195 insertions(+), 62 deletions(-) diff --git a/drivers/iio/adc/ad4080.c b/drivers/iio/adc/ad4080.c index 204ad198342b..265d85ac171a 100644 --- a/drivers/iio/adc/ad4080.c +++ b/drivers/iio/adc/ad4080.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -134,6 +135,9 @@ #define AD4086_CHIP_ID 0x0056 #define AD4087_CHIP_ID 0x0057 #define AD4088_CHIP_ID 0x0058 +#define AD4880_CHIP_ID 0x0750 + +#define AD4080_MAX_CHANNELS 2 =20 #define AD4080_LVDS_CNV_CLK_CNT_MAX 7 =20 @@ -179,8 +183,9 @@ struct ad4080_chip_info { }; =20 struct ad4080_state { - struct regmap *regmap; - struct iio_backend *back; + struct spi_device *spi[AD4080_MAX_CHANNELS]; + struct regmap *regmap[AD4080_MAX_CHANNELS]; + struct iio_backend *back[AD4080_MAX_CHANNELS]; const struct ad4080_chip_info *info; /* * Synchronize access to members the of driver state, and ensure @@ -189,7 +194,7 @@ struct ad4080_state { struct mutex lock; unsigned int num_lanes; unsigned long clk_rate; - enum ad4080_filter_type filter_type; + enum ad4080_filter_type filter_type[AD4080_MAX_CHANNELS]; bool lvds_cnv_en; }; =20 @@ -206,9 +211,9 @@ static int ad4080_reg_access(struct iio_dev *indio_dev,= unsigned int reg, struct ad4080_state *st =3D iio_priv(indio_dev); =20 if (readval) - return regmap_read(st->regmap, reg, readval); + return regmap_read(st->regmap[0], reg, readval); =20 - return regmap_write(st->regmap, reg, writeval); + return regmap_write(st->regmap[0], reg, writeval); } =20 static int ad4080_get_scale(struct ad4080_state *st, int *val, int *val2) @@ -229,8 +234,9 @@ static unsigned int ad4080_get_dec_rate(struct iio_dev = *dev, struct ad4080_state *st =3D iio_priv(dev); int ret; unsigned int data; + unsigned int ch =3D chan->channel; =20 - ret =3D regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data); + ret =3D regmap_read(st->regmap[ch], AD4080_REG_FILTER_CONFIG, &data); if (ret) return ret; =20 @@ -242,13 +248,14 @@ static int ad4080_set_dec_rate(struct iio_dev *dev, unsigned int mode) { struct ad4080_state *st =3D iio_priv(dev); + unsigned int ch =3D chan->channel; =20 guard(mutex)(&st->lock); =20 - if ((st->filter_type >=3D SINC_5 && mode >=3D 512) || mode < 2) + if ((st->filter_type[ch] >=3D SINC_5 && mode >=3D 512) || mode < 2) return -EINVAL; =20 - return regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG, + return regmap_update_bits(st->regmap[ch], AD4080_REG_FILTER_CONFIG, AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, FIELD_PREP(AD4080_FILTER_CONFIG_SINC_DEC_RATE_MSK, (ilog2(mode) - 1))); @@ -268,15 +275,15 @@ static int ad4080_read_raw(struct iio_dev *indio_dev, dec_rate =3D ad4080_get_dec_rate(indio_dev, chan); if (dec_rate < 0) return dec_rate; - if (st->filter_type =3D=3D SINC_5_COMP) + if (st->filter_type[chan->channel] =3D=3D SINC_5_COMP) dec_rate *=3D 2; - if (st->filter_type) + if (st->filter_type[chan->channel]) *val =3D DIV_ROUND_CLOSEST(st->clk_rate, dec_rate); else *val =3D st->clk_rate; return IIO_VAL_INT; case IIO_CHAN_INFO_OVERSAMPLING_RATIO: - if (st->filter_type =3D=3D FILTER_NONE) { + if (st->filter_type[chan->channel] =3D=3D FILTER_NONE) { *val =3D 1; } else { *val =3D ad4080_get_dec_rate(indio_dev, chan); @@ -297,7 +304,7 @@ static int ad4080_write_raw(struct iio_dev *indio_dev, =20 switch (mask) { case IIO_CHAN_INFO_OVERSAMPLING_RATIO: - if (st->filter_type =3D=3D FILTER_NONE && val > 1) + if (st->filter_type[chan->channel] =3D=3D FILTER_NONE && val > 1) return -EINVAL; =20 return ad4080_set_dec_rate(indio_dev, chan, val); @@ -306,23 +313,23 @@ static int ad4080_write_raw(struct iio_dev *indio_dev, } } =20 -static int ad4080_lvds_sync_write(struct ad4080_state *st) +static int ad4080_lvds_sync_write(struct ad4080_state *st, unsigned int ch) { - struct device *dev =3D regmap_get_device(st->regmap); + struct device *dev =3D regmap_get_device(st->regmap[ch]); int ret; =20 - ret =3D regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, + ret =3D regmap_set_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_A, AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); if (ret) return ret; =20 - ret =3D iio_backend_interface_data_align(st->back, 10000); + ret =3D iio_backend_interface_data_align(st->back[ch], 10000); if (ret) return dev_err_probe(dev, ret, "Data alignment process failed\n"); =20 dev_dbg(dev, "Success: Pattern correct and Locked!\n"); - return regmap_clear_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, + return regmap_clear_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_= A, AD4080_ADC_DATA_INTF_CONFIG_A_INTF_CHK_EN); } =20 @@ -331,9 +338,10 @@ static int ad4080_get_filter_type(struct iio_dev *dev, { struct ad4080_state *st =3D iio_priv(dev); unsigned int data; + unsigned int ch =3D chan->channel; int ret; =20 - ret =3D regmap_read(st->regmap, AD4080_REG_FILTER_CONFIG, &data); + ret =3D regmap_read(st->regmap[ch], AD4080_REG_FILTER_CONFIG, &data); if (ret) return ret; =20 @@ -345,6 +353,7 @@ static int ad4080_set_filter_type(struct iio_dev *dev, unsigned int mode) { struct ad4080_state *st =3D iio_priv(dev); + unsigned int ch =3D chan->channel; int dec_rate; int ret; =20 @@ -357,18 +366,18 @@ static int ad4080_set_filter_type(struct iio_dev *dev, if (mode >=3D SINC_5 && dec_rate >=3D 512) return -EINVAL; =20 - ret =3D iio_backend_filter_type_set(st->back, mode); + ret =3D iio_backend_filter_type_set(st->back[ch], mode); if (ret) return ret; =20 - ret =3D regmap_update_bits(st->regmap, AD4080_REG_FILTER_CONFIG, + ret =3D regmap_update_bits(st->regmap[ch], AD4080_REG_FILTER_CONFIG, AD4080_FILTER_CONFIG_FILTER_SEL_MSK, FIELD_PREP(AD4080_FILTER_CONFIG_FILTER_SEL_MSK, mode)); if (ret) return ret; =20 - st->filter_type =3D mode; + st->filter_type[ch] =3D mode; =20 return 0; } @@ -382,14 +391,14 @@ static int ad4080_read_avail(struct iio_dev *indio_de= v, =20 switch (mask) { case IIO_CHAN_INFO_OVERSAMPLING_RATIO: - switch (st->filter_type) { + switch (st->filter_type[chan->channel]) { case FILTER_NONE: *vals =3D ad4080_dec_rate_none; *length =3D ARRAY_SIZE(ad4080_dec_rate_none); break; default: *vals =3D ad4080_dec_rate_avail; - *length =3D st->filter_type >=3D SINC_5 ? + *length =3D st->filter_type[chan->channel] >=3D SINC_5 ? (ARRAY_SIZE(ad4080_dec_rate_avail) - 2) : ARRAY_SIZE(ad4080_dec_rate_avail); break; @@ -401,6 +410,28 @@ static int ad4080_read_avail(struct iio_dev *indio_dev, } } =20 +static int ad4880_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *scan_mask) +{ + struct ad4080_state *st =3D iio_priv(indio_dev); + int ret; + + for (unsigned int ch =3D 0; ch < st->info->num_channels; ch++) { + /* + * Each backend has a single channel (channel 0 from the + * backend's perspective), so always use channel index 0. + */ + if (test_bit(ch, scan_mask)) + ret =3D iio_backend_chan_enable(st->back[ch], 0); + else + ret =3D iio_backend_chan_disable(st->back[ch], 0); + if (ret) + return ret; + } + + return 0; +} + static const struct iio_info ad4080_iio_info =3D { .debugfs_reg_access =3D ad4080_reg_access, .read_raw =3D ad4080_read_raw, @@ -408,6 +439,19 @@ static const struct iio_info ad4080_iio_info =3D { .read_avail =3D ad4080_read_avail, }; =20 +/* + * AD4880 needs update_scan_mode to enable/disable individual backend chan= nels. + * Single-channel devices don't need this as their backends may not implem= ent + * chan_enable/chan_disable operations. + */ +static const struct iio_info ad4880_iio_info =3D { + .debugfs_reg_access =3D ad4080_reg_access, + .read_raw =3D ad4080_read_raw, + .write_raw =3D ad4080_write_raw, + .read_avail =3D ad4080_read_avail, + .update_scan_mode =3D ad4880_update_scan_mode, +}; + static const struct iio_enum ad4080_filter_type_enum =3D { .items =3D ad4080_filter_type_iio_enum, .num_items =3D ARRAY_SIZE(ad4080_filter_type_iio_enum), @@ -422,17 +466,28 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[= ] =3D { { } }; =20 -#define AD4080_CHANNEL_DEFINE(bits, storage) { \ +/* + * AD4880 needs per-channel filter configuration since each channel has + * its own independent ADC with separate SPI interface. + */ +static struct iio_chan_spec_ext_info ad4880_ext_info[] =3D { + IIO_ENUM("filter_type", IIO_SEPARATE, &ad4080_filter_type_enum), + IIO_ENUM_AVAILABLE("filter_type", IIO_SEPARATE, + &ad4080_filter_type_enum), + { } +}; + +#define AD4080_CHANNEL_DEFINE(bits, storage, idx) { \ .type =3D IIO_VOLTAGE, \ .indexed =3D 1, \ - .channel =3D 0, \ + .channel =3D (idx), \ .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE), \ .info_mask_shared_by_all =3D BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .info_mask_shared_by_all_available =3D \ BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ .ext_info =3D ad4080_ext_info, \ - .scan_index =3D 0, \ + .scan_index =3D (idx), \ .scan_type =3D { \ .sign =3D 's', \ .realbits =3D (bits), \ @@ -440,23 +495,51 @@ static struct iio_chan_spec_ext_info ad4080_ext_info[= ] =3D { }, \ } =20 -static const struct iio_chan_spec ad4080_channel =3D AD4080_CHANNEL_DEFINE= (20, 32); +/* + * AD4880 has per-channel attributes (filter_type, oversampling_ratio, + * sampling_frequency) since each channel has its own independent ADC + * with separate SPI configuration interface. + */ +#define AD4880_CHANNEL_DEFINE(bits, storage, idx) { \ + .type =3D IIO_VOLTAGE, \ + .indexed =3D 1, \ + .channel =3D (idx), \ + .info_mask_separate =3D BIT(IIO_CHAN_INFO_SCALE) | \ + BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .info_mask_separate_available =3D \ + BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ + .ext_info =3D ad4880_ext_info, \ + .scan_index =3D (idx), \ + .scan_type =3D { \ + .sign =3D 's', \ + .realbits =3D (bits), \ + .storagebits =3D (storage), \ + }, \ +} =20 -static const struct iio_chan_spec ad4081_channel =3D AD4080_CHANNEL_DEFINE= (20, 32); +static const struct iio_chan_spec ad4080_channel =3D AD4080_CHANNEL_DEFINE= (20, 32, 0); =20 -static const struct iio_chan_spec ad4082_channel =3D AD4080_CHANNEL_DEFINE= (20, 32); +static const struct iio_chan_spec ad4081_channel =3D AD4080_CHANNEL_DEFINE= (20, 32, 0); =20 -static const struct iio_chan_spec ad4083_channel =3D AD4080_CHANNEL_DEFINE= (16, 16); +static const struct iio_chan_spec ad4082_channel =3D AD4080_CHANNEL_DEFINE= (20, 32, 0); =20 -static const struct iio_chan_spec ad4084_channel =3D AD4080_CHANNEL_DEFINE= (16, 16); +static const struct iio_chan_spec ad4083_channel =3D AD4080_CHANNEL_DEFINE= (16, 16, 0); =20 -static const struct iio_chan_spec ad4085_channel =3D AD4080_CHANNEL_DEFINE= (16, 16); +static const struct iio_chan_spec ad4084_channel =3D AD4080_CHANNEL_DEFINE= (16, 16, 0); =20 -static const struct iio_chan_spec ad4086_channel =3D AD4080_CHANNEL_DEFINE= (14, 16); +static const struct iio_chan_spec ad4085_channel =3D AD4080_CHANNEL_DEFINE= (16, 16, 0); =20 -static const struct iio_chan_spec ad4087_channel =3D AD4080_CHANNEL_DEFINE= (14, 16); +static const struct iio_chan_spec ad4086_channel =3D AD4080_CHANNEL_DEFINE= (14, 16, 0); =20 -static const struct iio_chan_spec ad4088_channel =3D AD4080_CHANNEL_DEFINE= (14, 16); +static const struct iio_chan_spec ad4087_channel =3D AD4080_CHANNEL_DEFINE= (14, 16, 0); + +static const struct iio_chan_spec ad4088_channel =3D AD4080_CHANNEL_DEFINE= (14, 16, 0); + +static const struct iio_chan_spec ad4880_channels[] =3D { + AD4880_CHANNEL_DEFINE(20, 32, 0), + AD4880_CHANNEL_DEFINE(20, 32, 1), +}; =20 static const struct ad4080_chip_info ad4080_chip_info =3D { .name =3D "ad4080", @@ -548,25 +631,34 @@ static const struct ad4080_chip_info ad4088_chip_info= =3D { .lvds_cnv_clk_cnt_max =3D 8, }; =20 -static int ad4080_setup(struct iio_dev *indio_dev) +static const struct ad4080_chip_info ad4880_chip_info =3D { + .name =3D "ad4880", + .product_id =3D AD4880_CHIP_ID, + .scale_table =3D ad4080_scale_table, + .num_scales =3D ARRAY_SIZE(ad4080_scale_table), + .num_channels =3D 2, + .channels =3D ad4880_channels, + .lvds_cnv_clk_cnt_max =3D AD4080_LVDS_CNV_CLK_CNT_MAX, +}; + +static int ad4080_setup_channel(struct ad4080_state *st, unsigned int ch) { - struct ad4080_state *st =3D iio_priv(indio_dev); - struct device *dev =3D regmap_get_device(st->regmap); + struct device *dev =3D regmap_get_device(st->regmap[ch]); __le16 id_le; u16 id; int ret; =20 - ret =3D regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A, + ret =3D regmap_write(st->regmap[ch], AD4080_REG_INTERFACE_CONFIG_A, AD4080_INTERFACE_CONFIG_A_SW_RESET); if (ret) return ret; =20 - ret =3D regmap_write(st->regmap, AD4080_REG_INTERFACE_CONFIG_A, + ret =3D regmap_write(st->regmap[ch], AD4080_REG_INTERFACE_CONFIG_A, AD4080_INTERFACE_CONFIG_A_SDO_ENABLE); if (ret) return ret; =20 - ret =3D regmap_bulk_read(st->regmap, AD4080_REG_PRODUCT_ID_L, &id_le, + ret =3D regmap_bulk_read(st->regmap[ch], AD4080_REG_PRODUCT_ID_L, &id_le, sizeof(id_le)); if (ret) return ret; @@ -575,18 +667,18 @@ static int ad4080_setup(struct iio_dev *indio_dev) if (id !=3D st->info->product_id) dev_info(dev, "Unrecognized CHIP_ID 0x%X\n", id); =20 - ret =3D regmap_set_bits(st->regmap, AD4080_REG_GPIO_CONFIG_A, + ret =3D regmap_set_bits(st->regmap[ch], AD4080_REG_GPIO_CONFIG_A, AD4080_GPIO_CONFIG_A_GPO_1_EN); if (ret) return ret; =20 - ret =3D regmap_write(st->regmap, AD4080_REG_GPIO_CONFIG_B, + ret =3D regmap_write(st->regmap[ch], AD4080_REG_GPIO_CONFIG_B, FIELD_PREP(AD4080_GPIO_CONFIG_B_GPIO_1_SEL_MSK, AD4080_GPIO_CONFIG_B_GPIO_FILTER_RES_RDY)); if (ret) return ret; =20 - ret =3D iio_backend_num_lanes_set(st->back, st->num_lanes); + ret =3D iio_backend_num_lanes_set(st->back[ch], st->num_lanes); if (ret) return ret; =20 @@ -594,7 +686,7 @@ static int ad4080_setup(struct iio_dev *indio_dev) return 0; =20 /* Set maximum LVDS Data Transfer Latency */ - ret =3D regmap_update_bits(st->regmap, + ret =3D regmap_update_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_B, AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, FIELD_PREP(AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_CLK_CNT_MSK, @@ -603,24 +695,38 @@ static int ad4080_setup(struct iio_dev *indio_dev) return ret; =20 if (st->num_lanes > 1) { - ret =3D regmap_set_bits(st->regmap, AD4080_REG_ADC_DATA_INTF_CONFIG_A, + ret =3D regmap_set_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_= A, AD4080_ADC_DATA_INTF_CONFIG_A_SPI_LVDS_LANES); if (ret) return ret; } =20 - ret =3D regmap_set_bits(st->regmap, + ret =3D regmap_set_bits(st->regmap[ch], AD4080_REG_ADC_DATA_INTF_CONFIG_B, AD4080_ADC_DATA_INTF_CONFIG_B_LVDS_CNV_EN); if (ret) return ret; =20 - return ad4080_lvds_sync_write(st); + return ad4080_lvds_sync_write(st, ch); } =20 -static int ad4080_properties_parse(struct ad4080_state *st) +static int ad4080_setup(struct iio_dev *indio_dev) +{ + struct ad4080_state *st =3D iio_priv(indio_dev); + int ret; + + for (unsigned int ch =3D 0; ch < st->info->num_channels; ch++) { + ret =3D ad4080_setup_channel(st, ch); + if (ret) + return ret; + } + + return 0; +} + +static int ad4080_properties_parse(struct ad4080_state *st, + struct device *dev) { - struct device *dev =3D regmap_get_device(st->regmap); =20 st->lvds_cnv_en =3D device_property_read_bool(dev, "adi,lvds-cnv-enable"); =20 @@ -655,14 +761,28 @@ static int ad4080_probe(struct spi_device *spi) return dev_err_probe(dev, ret, "failed to get and enable supplies\n"); =20 - st->regmap =3D devm_regmap_init_spi(spi, &ad4080_regmap_config); - if (IS_ERR(st->regmap)) - return PTR_ERR(st->regmap); + /* Setup primary SPI device (channel 0) */ + st->spi[0] =3D spi; + st->regmap[0] =3D devm_regmap_init_spi(spi, &ad4080_regmap_config); + if (IS_ERR(st->regmap[0])) + return PTR_ERR(st->regmap[0]); =20 st->info =3D spi_get_device_match_data(spi); if (!st->info) return -ENODEV; =20 + /* Setup ancillary SPI devices for additional channels */ + for (unsigned int ch =3D 1; ch < st->info->num_channels; ch++) { + st->spi[ch] =3D devm_spi_new_ancillary_device(spi, spi_get_chipselect(sp= i, ch)); + if (IS_ERR(st->spi[ch])) + return dev_err_probe(dev, PTR_ERR(st->spi[ch]), + "failed to register ancillary device\n"); + + st->regmap[ch] =3D devm_regmap_init_spi(st->spi[ch], &ad4080_regmap_conf= ig); + if (IS_ERR(st->regmap[ch])) + return PTR_ERR(st->regmap[ch]); + } + ret =3D devm_mutex_init(dev, &st->lock); if (ret) return ret; @@ -670,9 +790,10 @@ static int ad4080_probe(struct spi_device *spi) indio_dev->name =3D st->info->name; indio_dev->channels =3D st->info->channels; indio_dev->num_channels =3D st->info->num_channels; - indio_dev->info =3D &ad4080_iio_info; + indio_dev->info =3D st->info->num_channels > 1 ? + &ad4880_iio_info : &ad4080_iio_info; =20 - ret =3D ad4080_properties_parse(st); + ret =3D ad4080_properties_parse(st, dev); if (ret) return ret; =20 @@ -682,15 +803,25 @@ static int ad4080_probe(struct spi_device *spi) =20 st->clk_rate =3D clk_get_rate(clk); =20 - st->back =3D devm_iio_backend_get(dev, NULL); - if (IS_ERR(st->back)) - return PTR_ERR(st->back); + /* Get backends for all channels */ + for (unsigned int ch =3D 0; ch < st->info->num_channels; ch++) { + st->back[ch] =3D devm_iio_backend_get_by_index(dev, ch); + if (IS_ERR(st->back[ch])) + return PTR_ERR(st->back[ch]); =20 - ret =3D devm_iio_backend_request_buffer(dev, st->back, indio_dev); - if (ret) - return ret; + ret =3D devm_iio_backend_enable(dev, st->back[ch]); + if (ret) + return ret; + } =20 - ret =3D devm_iio_backend_enable(dev, st->back); + /* + * Request buffer from the first backend only. For multi-channel + * devices (e.g., AD4880), the FPGA uses two axi_ad408x IP instances + * (one per ADC channel) whose outputs are combined by a packer block + * that interleaves all channel data into a single DMA stream routed + * through the first backend's clock domain. + */ + ret =3D devm_iio_backend_request_buffer(dev, st->back[0], indio_dev); if (ret) return ret; =20 @@ -711,6 +842,7 @@ static const struct spi_device_id ad4080_id[] =3D { { "ad4086", (kernel_ulong_t)&ad4086_chip_info }, { "ad4087", (kernel_ulong_t)&ad4087_chip_info }, { "ad4088", (kernel_ulong_t)&ad4088_chip_info }, + { "ad4880", (kernel_ulong_t)&ad4880_chip_info }, { } }; MODULE_DEVICE_TABLE(spi, ad4080_id); @@ -725,6 +857,7 @@ static const struct of_device_id ad4080_of_match[] =3D { { .compatible =3D "adi,ad4086", &ad4086_chip_info }, { .compatible =3D "adi,ad4087", &ad4087_chip_info }, { .compatible =3D "adi,ad4088", &ad4088_chip_info }, + { .compatible =3D "adi,ad4880", &ad4880_chip_info }, { } }; MODULE_DEVICE_TABLE(of, ad4080_of_match); --=20 2.43.0