From nobody Sat Jun 20 04:58:29 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB8DA277035 for ; Mon, 20 Apr 2026 09:16:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776676614; cv=none; b=UmTyONxeiyQoLmIt3/bkZG4SGvz7V4wCdVzMcJfdyEF8uhQ8Vy5uF93Vv2erXovazxzSWeuVGK3pYyK9hGuN+7ylEpYssYgfGa03rFXaJ3nnVuHE94vt2bKxdos03msYowCJQ7nR2P6zwzaVvUKEzB4p4bIZEctZtOU0JheSu/o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776676614; c=relaxed/simple; bh=/Ga1v17sifGMNU5boXZBxIIqhQz4A909zgaNi64+tfI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=B726oTxUz1mbCknIz6PsqIikFM33cv2gKW4G34nkg1ZR09gVRh3BQJxbdzCgem3eam/aQ5B0/B/+At0o7g+vVdNJiildjaG7QbiZhjYqmq2tzxqdIW/qb2xYFhuoFZFWF4UR1y9jBdfn+XmC8qoMuAPYJlrBkuju2MU1+XMvixc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=RVjmxo98; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=RVjmxo98; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="RVjmxo98"; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="RVjmxo98" Received: from imap1.dmz-prg2.suse.org (unknown [10.150.64.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id CC6D75BCE0; Mon, 20 Apr 2026 09:16:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776676609; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+FvkLGB/iuFMNt34pOJZj4GKwn5sfg6EuBDMkD8z8V0=; b=RVjmxo988SbmIgRGIYxoLn4+jwzZYOPXwhiaHKiX7wXZkk4yZAWbJmOL/wIjidpoY5ZSEB 3HGIXx25BXHbeO+YcZUJIPhEJpxJZWxLOZcoYdSGtJdrJrg+7Y7P0HDvNFIlF2sgj9o/4T P5GQpvL+YyuWfUbsIgByF69PtvJBjN0= Authentication-Results: smtp-out2.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776676609; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+FvkLGB/iuFMNt34pOJZj4GKwn5sfg6EuBDMkD8z8V0=; b=RVjmxo988SbmIgRGIYxoLn4+jwzZYOPXwhiaHKiX7wXZkk4yZAWbJmOL/wIjidpoY5ZSEB 3HGIXx25BXHbeO+YcZUJIPhEJpxJZWxLOZcoYdSGtJdrJrg+7Y7P0HDvNFIlF2sgj9o/4T P5GQpvL+YyuWfUbsIgByF69PtvJBjN0= Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 9A313593AE; Mon, 20 Apr 2026 09:16:49 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id zyh0JAHv5WnAPQAAD6G6ig (envelope-from ); Mon, 20 Apr 2026 09:16:49 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen Subject: [PATCH RFC 1/6] x86/msr: Rename msr_read() and msr_write() Date: Mon, 20 Apr 2026 11:16:29 +0200 Message-ID: <20260420091634.128787-2-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260420091634.128787-1-jgross@suse.com> References: <20260420091634.128787-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; FUZZY_RATELIMITED(0.00)[rspamd.com]; RCPT_COUNT_SEVEN(0.00)[8]; MIME_TRACE(0.00)[0:+]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; URIBL_BLOCKED(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:mid,suse.com:email]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Score: -2.80 X-Spam-Level: Content-Type: text/plain; charset="utf-8" Rename the existing msr_read() and msr_write() functions to msr_do_read() and msr_do_write(), as the original names will be used for new MSR access functions in the future. Signed-off-by: Juergen Gross --- arch/x86/kernel/msr.c | 12 ++++++------ arch/x86/lib/msr.c | 12 ++++++------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c index 4469c784eaa0..43791746103c 100644 --- a/arch/x86/kernel/msr.c +++ b/arch/x86/kernel/msr.c @@ -49,8 +49,8 @@ enum allow_write_msrs { =20 static enum allow_write_msrs allow_writes =3D MSR_WRITES_DEFAULT; =20 -static ssize_t msr_read(struct file *file, char __user *buf, - size_t count, loff_t *ppos) +static ssize_t msr_do_read(struct file *file, char __user *buf, + size_t count, loff_t *ppos) { u32 __user *tmp =3D (u32 __user *) buf; u32 data[2]; @@ -105,8 +105,8 @@ static int filter_write(u32 reg) return 0; } =20 -static ssize_t msr_write(struct file *file, const char __user *buf, - size_t count, loff_t *ppos) +static ssize_t msr_do_write(struct file *file, const char __user *buf, + size_t count, loff_t *ppos) { const u32 __user *tmp =3D (const u32 __user *)buf; u32 data[2]; @@ -227,8 +227,8 @@ static int msr_open(struct inode *inode, struct file *f= ile) static const struct file_operations msr_fops =3D { .owner =3D THIS_MODULE, .llseek =3D no_seek_end_llseek, - .read =3D msr_read, - .write =3D msr_write, + .read =3D msr_do_read, + .write =3D msr_do_write, .open =3D msr_open, .unlocked_ioctl =3D msr_ioctl, .compat_ioctl =3D msr_ioctl, diff --git a/arch/x86/lib/msr.c b/arch/x86/lib/msr.c index dfdd1da89f36..be6c34666743 100644 --- a/arch/x86/lib/msr.c +++ b/arch/x86/lib/msr.c @@ -28,7 +28,7 @@ void msrs_free(struct msr __percpu *msrs) EXPORT_SYMBOL(msrs_free); =20 /** - * msr_read - Read an MSR with error handling + * msr_do_read - Read an MSR with error handling * @msr: MSR to read * @m: value to read into * @@ -37,7 +37,7 @@ EXPORT_SYMBOL(msrs_free); * * Return: %0 for success, otherwise an error code */ -static int msr_read(u32 msr, struct msr *m) +static int msr_do_read(u32 msr, struct msr *m) { int err; u64 val; @@ -50,14 +50,14 @@ static int msr_read(u32 msr, struct msr *m) } =20 /** - * msr_write - Write an MSR with error handling + * msr_do_write - Write an MSR with error handling * * @msr: MSR to write * @m: value to write * * Return: %0 for success, otherwise an error code */ -static int msr_write(u32 msr, struct msr *m) +static int msr_do_write(u32 msr, struct msr *m) { return wrmsrq_safe(msr, m->q); } @@ -70,7 +70,7 @@ static inline int __flip_bit(u32 msr, u8 bit, bool set) if (bit > 63) return err; =20 - err =3D msr_read(msr, &m); + err =3D msr_do_read(msr, &m); if (err) return err; =20 @@ -83,7 +83,7 @@ static inline int __flip_bit(u32 msr, u8 bit, bool set) if (m1.q =3D=3D m.q) return 0; =20 - err =3D msr_write(msr, &m1); + err =3D msr_do_write(msr, &m1); if (err) return err; =20 --=20 2.53.0 From nobody Sat Jun 20 04:58:29 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0842438550E for ; Mon, 20 Apr 2026 09:16:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776676620; cv=none; b=KsWPwPvuVOKUtexmHpZXUUKnwPCuAzr5P2CVXhtEDZs2a7mf5hE1jaipDCF5IY2o8c95328HcQWofyf6CeGlHXQtVlFBqNWT6IAfcFOOjoI1lAM+IkOH8m0J5BWszZCXdXGsplMrLOn3FxGNKT9J3ezXookMY0AXatU9higCars= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776676620; c=relaxed/simple; bh=uDAtzIr09POoiA68Zem+8p4NrDgenjrCvY0fHrxTovY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jrJTl0PS57qyTnUd1S/FFBM09cagu2X8MBt8eQTRHH5SqRAJM8n9R/DvzPkvBrPPMTSK8J39Tc+iyj9+jnTOfd5nPJMb7v7d533ZGgwguUVeqQj18jSqoFCoYKod6msM9fWeIAmJXT6jV7yEP+e3EhnepO8xmDMJNI/gPXWUHS4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=u2BqB+oz; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=u2BqB+oz; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="u2BqB+oz"; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="u2BqB+oz" Received: from imap1.dmz-prg2.suse.org (unknown [10.150.64.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 50EED5BD22; Mon, 20 Apr 2026 09:16:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776676615; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Q7rrGCVlsS3R/AjxzlI2HAv2K2IxMbsCL1rzEK421iU=; b=u2BqB+ozHWJLrj2BqI5mgdrLWDMhShBmqH9Z+bXLonto7GdXdd01bPEOnnsM5BVngkLn1G vEPw76/yOs6R64l53RkbAP2wgU2CSuq/1inoi8t1V9fWeAI0FL9MvQhOm4DJO7RZfx299a wQYHlxDw14obH85MbXBkW8dIk9InpTY= Authentication-Results: smtp-out2.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776676615; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Q7rrGCVlsS3R/AjxzlI2HAv2K2IxMbsCL1rzEK421iU=; b=u2BqB+ozHWJLrj2BqI5mgdrLWDMhShBmqH9Z+bXLonto7GdXdd01bPEOnnsM5BVngkLn1G vEPw76/yOs6R64l53RkbAP2wgU2CSuq/1inoi8t1V9fWeAI0FL9MvQhOm4DJO7RZfx299a wQYHlxDw14obH85MbXBkW8dIk9InpTY= Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 1FB02593AE; Mon, 20 Apr 2026 09:16:55 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id OKiqBgfv5WnEPQAAD6G6ig (envelope-from ); Mon, 20 Apr 2026 09:16:55 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH RFC 2/6] x86/msr: Create a new minimal set of local MSR access functions Date: Mon, 20 Apr 2026 11:16:30 +0200 Message-ID: <20260420091634.128787-3-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260420091634.128787-1-jgross@suse.com> References: <20260420091634.128787-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam-Score: -2.80 X-Spam-Level: X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; FUZZY_RATELIMITED(0.00)[rspamd.com]; RCPT_COUNT_SEVEN(0.00)[8]; MIME_TRACE(0.00)[0:+]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; URIBL_BLOCKED(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:mid,suse.com:email]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO Content-Type: text/plain; charset="utf-8" Today there are two sets of MSR access functions (apart from the low level ones): one is using 64 bit values, and the other a pair of 32-bit values for the MSR contents. The read variants are macros, while the write variants are proper inline functions. In order to prepare for non-serializing variants of the write functions, create a complete set of MSR functions using a proper name space ("msr_*") without the 32-bit pair variants. Name the write variants explicitly msr_write_[safe_]ser() and msr_write_[safe_]noser() in order to make it very clear whether the serializing or the non-serializing variant is meant. Right now the new set will be based on the old wrmsr*() and rdmsr*() functions, but when all users have been switched to use the new functions, the old wrmsr*() and rdmsr*() functions will be dropped. Signed-off-by: Juergen Gross --- arch/x86/include/asm/msr.h | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 9c2ea29e12a9..cc21c8699e23 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -227,6 +227,44 @@ static __always_inline u64 rdpmc(int counter) =20 #endif /* !CONFIG_PARAVIRT_XXL */ =20 +/* + * New set of MSR access functions. New code should use those instead of t= he + * legacy wrmsr*() and rdmsr*() ones. + */ +static __always_inline u64 msr_read(u32 msr) +{ + u64 val; + + rdmsrq(msr, val); + + return val; +} + +static __always_inline int msr_read_safe(u32 msr, u64 *val) +{ + return rdmsrq_safe(msr, val); +} + +static __always_inline void msr_write_ser(u32 msr, u64 val) +{ + wrmsrq(msr, val); +} + +static __always_inline int msr_write_safe_ser(u32 msr, u64 val) +{ + return wrmsrq_safe(msr, val); +} + +static __always_inline void msr_write_noser(u32 msr, u64 val) +{ + wrmsrq(msr, val); +} + +static __always_inline int msr_write_safe_noser(u32 msr, u64 val) +{ + return wrmsrq_safe(msr, val); +} + /* Instruction opcode for WRMSRNS supported in binutils >=3D 2.40 */ #define ASM_WRMSRNS _ASM_BYTES(0x0f,0x01,0xc6) =20 --=20 2.53.0 From nobody Sat Jun 20 04:58:29 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D20438C417 for ; Mon, 20 Apr 2026 09:17:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776676624; cv=none; b=di/Vs/IX3Ib/mjmhherAl75xOuPRlY4lFfnMsIC7oO0UFqxOxFiJbEFYjbFnbva7KIZGE8n98VMfcOXCdbgk3p/sUf+e9UH8Ha52g2JvVkiNJ6GElowdeLO2ylNryL4LKhOiKU5jDk5bunWN46PMphkFt75dWoaOoUJ29d1zLDs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776676624; c=relaxed/simple; bh=/W4p1o73k3PN42AY5wRcRSj87TVmJ0AjOw+IyJKsPx4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bLglKmRpSlsYtDLxPGfgCWyQjml9iVnDEbVO7Mt3/gEGtNzqdvQQQIur+cKsDIIz3q3AsUHO5Fw2uMhh3U48IagWo7cLDDrSvxDupiijXApmcC3Nvfrn57Opj3Rwd5MjqMXkR90aWD0g7Y6Ld18Ln0YMbYjfdEEgk2SR8tp3eig= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=CdYIAHnE; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=CdYIAHnE; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="CdYIAHnE"; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="CdYIAHnE" Received: from imap1.dmz-prg2.suse.org (unknown [10.150.64.97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id C99CA6A7D7; Mon, 20 Apr 2026 09:17:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776676620; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0zIYFwLCWymBghvJFZcKwH1jpjugjzO4mSM7EF43F4U=; b=CdYIAHnEABlthC8xB23n/FEN7D0JIYzeGnZrfV0tFUoNBsBhTeCFP24PIpalHnu93fGq7q 80KkQC31InrQl5Vujfa7dTG1FVqPm/YbyvtmDjlHIEyUZvuVpTwd2sPWXRqi2CUgQ5FCJj WQ4OCUzX8GxFecJj2lq62wt1jDQcImk= Authentication-Results: smtp-out1.suse.de; none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776676620; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0zIYFwLCWymBghvJFZcKwH1jpjugjzO4mSM7EF43F4U=; b=CdYIAHnEABlthC8xB23n/FEN7D0JIYzeGnZrfV0tFUoNBsBhTeCFP24PIpalHnu93fGq7q 80KkQC31InrQl5Vujfa7dTG1FVqPm/YbyvtmDjlHIEyUZvuVpTwd2sPWXRqi2CUgQ5FCJj WQ4OCUzX8GxFecJj2lq62wt1jDQcImk= Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 9A2D5593AE; Mon, 20 Apr 2026 09:17:00 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 0hGHJAzv5WnIPQAAD6G6ig (envelope-from ); Mon, 20 Apr 2026 09:17:00 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH RFC 3/6] x86/msr: Create a new minimal set of inter-CPU MSR access functions Date: Mon, 20 Apr 2026 11:16:31 +0200 Message-ID: <20260420091634.128787-4-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260420091634.128787-1-jgross@suse.com> References: <20260420091634.128787-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spamd-Result: default: False [-2.80 / 50.00]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; FUZZY_RATELIMITED(0.00)[rspamd.com]; RCPT_COUNT_SEVEN(0.00)[8]; MIME_TRACE(0.00)[0:+]; ARC_NA(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; URIBL_BLOCKED(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo]; RCVD_TLS_ALL(0.00)[] X-Spam-Flag: NO X-Spam-Score: -2.80 X-Spam-Level: Content-Type: text/plain; charset="utf-8" Like for local MSR access functions create a set of inter-CPU MSR access functions using the "msr_" name space. For writing MSRs of other CPUs there is no need to have serializing and non-serializing variants. Base the new functions on the old ones for now. This can be changed when all callers have been changed to use the new functions only, in order to delete the old ones then. Signed-off-by: Juergen Gross --- arch/x86/include/asm/msr.h | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index cc21c8699e23..74e87b2b39fd 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -369,5 +369,37 @@ static inline int wrmsr_safe_regs_on_cpu(unsigned int = cpu, u32 regs[8]) #define wrmsrl(msr, val) wrmsrq(msr, val) #define rdmsrl_on_cpu(cpu, msr, q) rdmsrq_on_cpu(cpu, msr, q) =20 +static inline int msr_read_on_cpu(unsigned int cpu, u32 msr, u64 *val) +{ + return rdmsrq_on_cpu(cpu, msr, val); +} + +static inline int msr_read_safe_on_cpu(unsigned int cpu, u32 msr, u64 *val) +{ + return rdmsrq_safe_on_cpu(cpu, msr, val); +} + +static inline int msr_write_on_cpu(unsigned int cpu, u32 msr, u64 val) +{ + return wrmsrq_on_cpu(cpu, msr, val); +} + +static inline int msr_write_safe_on_cpu(unsigned int cpu, u32 msr, u64 val) +{ + return wrmsrq_safe_on_cpu(cpu, msr, val); +} + +static inline void msr_read_on_cpus(const struct cpumask *cpus, u32 msr, + struct msr __percpu *msrs) +{ + rdmsr_on_cpus(cpus, msr, msrs); +} + +static inline void msr_write_on_cpus(const struct cpumask *cpus, u32 msr, + struct msr __percpu *msrs) +{ + wrmsr_on_cpus(cpus, msr, msrs); +} + #endif /* __ASSEMBLER__ */ #endif /* _ASM_X86_MSR_H */ --=20 2.53.0 From nobody Sat Jun 20 04:58:29 2026 Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.223.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E22B38553E for ; Mon, 20 Apr 2026 09:17:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.130 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776676630; cv=none; b=IUSWR3RmvZS6g4SxQLGZBfySKf8NqKr+HPV7pI8tI5WfFKCUHXNIYBpGPjEt6owFLQ4RBTHGr5wz99FyF0iLBAFuzMEpyZvC4kDWPTxxHa2thEpfYm34WnHbj3aYc4ykAxIia2OOYUkIrpMPnQbx9zuKttcvr1q3FiozK0Bf0wQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776676630; c=relaxed/simple; bh=6zpe/dsMyNJA+SQ7zamr61zllof60DPgKrLwdDzcFMw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YZiA41RHFAmykt4PiZm1IVbb86Uj5Esj4qXTnRgUWFhCrIKqU/Gffh4mSWwZvcztgAehQXJo1qEnGOTmyk48SP/lkzyMW9P4HMX1Vv1e0RUZLtexbxoDTHMw1KcSmV5Hlmd6qi4pekCsfeRlrik7B7+A+gaTLGqqRn+Yevo75aQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=blhKER2E; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=blhKER2E; arc=none smtp.client-ip=195.135.223.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="blhKER2E"; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="blhKER2E" Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 52B646A8E3; Mon, 20 Apr 2026 09:17:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776676626; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Gs2/tyfQansJGWsPeB/X7grYSFW1Cp0LNMKe3Zz00IE=; b=blhKER2EwV6aV9iU3uHUfPB0wSx6aJr9+uxQxzixWnrIs0l/xpZzQ7E18xY0FHbwO8fLZR YUEjcPZUjPMXbrB7S+IJVUW/lVycm3Yhl9F2RH22UEZ4Nir2m+EBfJEKbShbHoGbBzNY+S zmw1NZNWTxwGQcYaF1YyYht+40uFT2c= Authentication-Results: smtp-out1.suse.de; dkim=pass header.d=suse.com header.s=susede1 header.b=blhKER2E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776676626; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Gs2/tyfQansJGWsPeB/X7grYSFW1Cp0LNMKe3Zz00IE=; b=blhKER2EwV6aV9iU3uHUfPB0wSx6aJr9+uxQxzixWnrIs0l/xpZzQ7E18xY0FHbwO8fLZR YUEjcPZUjPMXbrB7S+IJVUW/lVycm3Yhl9F2RH22UEZ4Nir2m+EBfJEKbShbHoGbBzNY+S zmw1NZNWTxwGQcYaF1YyYht+40uFT2c= Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 2021E593AE; Mon, 20 Apr 2026 09:17:06 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id Es/FBhLv5WnQPQAAD6G6ig (envelope-from ); Mon, 20 Apr 2026 09:17:06 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org Cc: Juergen Gross , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH RFC 4/6] x86/msr: Rename the *_safe_regs[_on_cpu]() MSR functions Date: Mon, 20 Apr 2026 11:16:32 +0200 Message-ID: <20260420091634.128787-5-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260420091634.128787-1-jgross@suse.com> References: <20260420091634.128787-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-3.01 / 50.00]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; R_DKIM_ALLOW(-0.20)[suse.com:s=susede1]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; FUZZY_RATELIMITED(0.00)[rspamd.com]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:104:10:150:64:97:from]; RCVD_COUNT_TWO(0.00)[2]; MIME_TRACE(0.00)[0:+]; ARC_NA(0.00)[]; TO_DN_SOME(0.00)[]; URIBL_BLOCKED(0.00)[suse.com:dkim,suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:106:10:150:64:167:received]; RCPT_COUNT_SEVEN(0.00)[8]; FROM_EQ_ENVFROM(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCVD_TLS_ALL(0.00)[]; DKIM_TRACE(0.00)[suse.com:+]; SPAMHAUS_XBL(0.00)[2a07:de40:b281:104:10:150:64:97:from]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:dkim,suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns] X-Rspamd-Queue-Id: 52B646A8E3 X-Spam-Flag: NO X-Spam-Score: -3.01 X-Spam-Level: Content-Type: text/plain; charset="utf-8" Move the functions rdmsr_safe_regs[_on_cpu]() and wrmsr_safe_regs[_on_cpu]() into the "msr_" name space and change all callers accordingly. Signed-off-by: Juergen Gross --- arch/x86/include/asm/msr.h | 17 ++++++++--------- arch/x86/kernel/cpu/amd.c | 4 ++-- arch/x86/kernel/msr.c | 4 ++-- arch/x86/lib/msr-reg-export.c | 4 ++-- arch/x86/lib/msr-reg.S | 16 ++++++++-------- arch/x86/lib/msr-smp.c | 20 ++++++++++---------- 6 files changed, 32 insertions(+), 33 deletions(-) diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h index 74e87b2b39fd..9b3d16b2eb61 100644 --- a/arch/x86/include/asm/msr.h +++ b/arch/x86/include/asm/msr.h @@ -156,9 +156,6 @@ static inline int notrace native_write_msr_safe(u32 msr= , u64 val) return err; } =20 -extern int rdmsr_safe_regs(u32 regs[8]); -extern int wrmsr_safe_regs(u32 regs[8]); - static inline u64 native_read_pmc(int counter) { EAX_EDX_DECLARE_ARGS(val, low, high); @@ -292,6 +289,8 @@ struct msr __percpu *msrs_alloc(void); void msrs_free(struct msr __percpu *msrs); int msr_set_bit(u32 msr, u8 bit); int msr_clear_bit(u32 msr, u8 bit); +int msr_read_safe_regs(u32 regs[8]); +int msr_write_safe_regs(u32 regs[8]); =20 #ifdef CONFIG_SMP int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); @@ -304,8 +303,8 @@ int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32= *l, u32 *h); int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); int rdmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); int wrmsrq_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); -int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); -int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); +int msr_read_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); +int msr_write_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); #else /* CONFIG_SMP */ static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *= h) { @@ -354,13 +353,13 @@ static inline int wrmsrq_safe_on_cpu(unsigned int cpu= , u32 msr_no, u64 q) { return wrmsrq_safe(msr_no, q); } -static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) +static inline int msr_read_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) { - return rdmsr_safe_regs(regs); + return msr_read_safe_regs(regs); } -static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) +static inline int msr_write_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) { - return wrmsr_safe_regs(regs); + return msr_write_safe_regs(regs); } #endif /* CONFIG_SMP */ =20 diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c index 2d9ae6ab1701..7266fcfcf448 100644 --- a/arch/x86/kernel/cpu/amd.c +++ b/arch/x86/kernel/cpu/amd.c @@ -45,7 +45,7 @@ static inline int rdmsrq_amd_safe(unsigned msr, u64 *p) gprs[1] =3D msr; gprs[7] =3D 0x9c5a203a; =20 - err =3D rdmsr_safe_regs(gprs); + err =3D msr_read_safe_regs(gprs); =20 *p =3D gprs[0] | ((u64)gprs[2] << 32); =20 @@ -64,7 +64,7 @@ static inline int wrmsrq_amd_safe(unsigned msr, u64 val) gprs[2] =3D val >> 32; gprs[7] =3D 0x9c5a203a; =20 - return wrmsr_safe_regs(gprs); + return msr_write_safe_regs(gprs); } =20 /* diff --git a/arch/x86/kernel/msr.c b/arch/x86/kernel/msr.c index 43791746103c..e3e71e3ba59f 100644 --- a/arch/x86/kernel/msr.c +++ b/arch/x86/kernel/msr.c @@ -162,7 +162,7 @@ static long msr_ioctl(struct file *file, unsigned int i= oc, unsigned long arg) err =3D -EFAULT; break; } - err =3D rdmsr_safe_regs_on_cpu(cpu, regs); + err =3D msr_read_safe_regs_on_cpu(cpu, regs); if (err) break; if (copy_to_user(uregs, ®s, sizeof(regs))) @@ -188,7 +188,7 @@ static long msr_ioctl(struct file *file, unsigned int i= oc, unsigned long arg) =20 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); =20 - err =3D wrmsr_safe_regs_on_cpu(cpu, regs); + err =3D msr_write_safe_regs_on_cpu(cpu, regs); if (err) break; if (copy_to_user(uregs, ®s, sizeof(regs))) diff --git a/arch/x86/lib/msr-reg-export.c b/arch/x86/lib/msr-reg-export.c index 876b4168ab0a..c3da46f0581b 100644 --- a/arch/x86/lib/msr-reg-export.c +++ b/arch/x86/lib/msr-reg-export.c @@ -2,5 +2,5 @@ #include #include =20 -EXPORT_SYMBOL(rdmsr_safe_regs); -EXPORT_SYMBOL(wrmsr_safe_regs); +EXPORT_SYMBOL(msr_read_safe_regs); +EXPORT_SYMBOL(msr_write_safe_regs); diff --git a/arch/x86/lib/msr-reg.S b/arch/x86/lib/msr-reg.S index 5ef8494896e8..ccb9e3a962f4 100644 --- a/arch/x86/lib/msr-reg.S +++ b/arch/x86/lib/msr-reg.S @@ -12,8 +12,8 @@ * reg layout: u32 gprs[eax, ecx, edx, ebx, esp, ebp, esi, edi] * */ -.macro op_safe_regs op -SYM_TYPED_FUNC_START(\op\()_safe_regs) +.macro op_safe_regs name op +SYM_TYPED_FUNC_START(\name) pushq %rbx pushq %r12 movq %rdi, %r10 /* Save pointer */ @@ -42,13 +42,13 @@ SYM_TYPED_FUNC_START(\op\()_safe_regs) jmp 2b =20 _ASM_EXTABLE(1b, 3b) -SYM_FUNC_END(\op\()_safe_regs) +SYM_FUNC_END(\name) .endm =20 #else /* X86_32 */ =20 -.macro op_safe_regs op -SYM_FUNC_START(\op\()_safe_regs) +.macro op_safe_regs name op +SYM_FUNC_START(\name) pushl %ebx pushl %ebp pushl %esi @@ -84,11 +84,11 @@ SYM_FUNC_START(\op\()_safe_regs) jmp 2b =20 _ASM_EXTABLE(1b, 3b) -SYM_FUNC_END(\op\()_safe_regs) +SYM_FUNC_END(\name) .endm =20 #endif =20 -op_safe_regs rdmsr -op_safe_regs wrmsr +op_safe_regs msr_read_safe_regs rdmsr +op_safe_regs msr_write_safe_regs wrmsr =20 diff --git a/arch/x86/lib/msr-smp.c b/arch/x86/lib/msr-smp.c index b8f63419e6ae..21bb1aee2af7 100644 --- a/arch/x86/lib/msr-smp.c +++ b/arch/x86/lib/msr-smp.c @@ -236,42 +236,42 @@ EXPORT_SYMBOL(rdmsrq_safe_on_cpu); * These variants are significantly slower, but allows control over * the entire 32-bit GPR set. */ -static void __rdmsr_safe_regs_on_cpu(void *info) +static void __msr_read_safe_regs(void *info) { struct msr_regs_info *rv =3D info; =20 - rv->err =3D rdmsr_safe_regs(rv->regs); + rv->err =3D msr_read_safe_regs(rv->regs); } =20 -static void __wrmsr_safe_regs_on_cpu(void *info) +static void __msr_write_safe_regs(void *info) { struct msr_regs_info *rv =3D info; =20 - rv->err =3D wrmsr_safe_regs(rv->regs); + rv->err =3D msr_write_safe_regs(rv->regs); } =20 -int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) +int msr_read_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) { int err; struct msr_regs_info rv; =20 rv.regs =3D regs; rv.err =3D -EIO; - err =3D smp_call_function_single(cpu, __rdmsr_safe_regs_on_cpu, &rv, 1); + err =3D smp_call_function_single(cpu, __msr_read_safe_regs, &rv, 1); =20 return err ? err : rv.err; } -EXPORT_SYMBOL(rdmsr_safe_regs_on_cpu); +EXPORT_SYMBOL(msr_read_safe_regs_on_cpu); =20 -int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) +int msr_write_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) { int err; struct msr_regs_info rv; =20 rv.regs =3D regs; rv.err =3D -EIO; - err =3D smp_call_function_single(cpu, __wrmsr_safe_regs_on_cpu, &rv, 1); + err =3D smp_call_function_single(cpu, __msr_write_safe_regs, &rv, 1); =20 return err ? err : rv.err; } -EXPORT_SYMBOL(wrmsr_safe_regs_on_cpu); +EXPORT_SYMBOL(msr_write_safe_regs_on_cpu); --=20 2.53.0 From nobody Sat Jun 20 04:58:29 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC505389E1F for ; Mon, 20 Apr 2026 09:17:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776676635; cv=none; b=DmVOGBvcHbmDJDmG3gACBapSfbuRHddcpyqUjA4Y6+R9YbcTidK9WVwp9basBkWTaNLxCaNySM5o3mxWQnMMz7tsqhsoX15fnPpwfrwnkvxD1U0cwd3RC46kpSCk0Es4th80e07riUbHx42SscBptiJfJ0m2HCaHFbeJVmuU5PE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776676635; c=relaxed/simple; bh=D3U5LdGFb+vzdoquwuvp70L8A5JVwF2Y+/m9coxoCbk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=cA1WwqZf9bx3K6Sbhr55WOQemxvUldYFhFJTzvuK44/HrFAjhOQjPSJz0jJDI/2yW+ki6RE8DQzRWRli8V+NPwplyZUthfxOLbmt0+ZDyYwEr8H3uyA+67I6ktSEPpPv14KhQ3dI2ha+g1RvH1OhWcnKsGimVxB6MwtOXWYwNkw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=Q3ntXF2g; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=Q3ntXF2g; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="Q3ntXF2g"; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="Q3ntXF2g" Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 09FD15BD2B; Mon, 20 Apr 2026 09:17:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776676632; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vv/M4Z9PXi0GEHr3QkUSw4FciIOYNriK9SiqYNb/cMU=; b=Q3ntXF2gNok4hGtLT2dDQqCvhcgE8x8YaOJSsppkATO/HQ8mkRNmE9/9rx2rZL9nynecH0 esrGf4vmfO5Ujta5V7bWX8BPiaWuw7yLgd8cWRAHMHkHLqHv/5REZUEckJwJNh+2MYEDAa REmXekpDOBp4vqTKQO9w5mSSBD/Fp7Y= Authentication-Results: smtp-out2.suse.de; dkim=pass header.d=suse.com header.s=susede1 header.b=Q3ntXF2g DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776676632; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vv/M4Z9PXi0GEHr3QkUSw4FciIOYNriK9SiqYNb/cMU=; b=Q3ntXF2gNok4hGtLT2dDQqCvhcgE8x8YaOJSsppkATO/HQ8mkRNmE9/9rx2rZL9nynecH0 esrGf4vmfO5Ujta5V7bWX8BPiaWuw7yLgd8cWRAHMHkHLqHv/5REZUEckJwJNh+2MYEDAa REmXekpDOBp4vqTKQO9w5mSSBD/Fp7Y= Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 9E010593AE; Mon, 20 Apr 2026 09:17:11 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id 4tR9JRfv5WnYPQAAD6G6ig (envelope-from ); Mon, 20 Apr 2026 09:17:11 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-perf-users@vger.kernel.org Cc: Juergen Gross , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" Subject: [PATCH RFC 5/6] x86/events: Switch core parts to use new MSR access functions Date: Mon, 20 Apr 2026 11:16:33 +0200 Message-ID: <20260420091634.128787-6-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260420091634.128787-1-jgross@suse.com> References: <20260420091634.128787-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Rspamd-Action: no action X-Rspamd-Server: rspamd2.dmz-prg2.suse.org X-Spamd-Result: default: False [-3.01 / 50.00]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; R_DKIM_ALLOW(-0.20)[suse.com:s=susede1]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; ARC_NA(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCPT_COUNT_TWELVE(0.00)[18]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; URIBL_BLOCKED(0.00)[imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns,suse.com:dkim,suse.com:mid,suse.com:email]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:104:10:150:64:97:from]; RCVD_COUNT_TWO(0.00)[2]; TO_MATCH_ENVRCPT_ALL(0.00)[]; FROM_HAS_DN(0.00)[]; RCVD_VIA_SMTP_AUTH(0.00)[]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:106:10:150:64:167:received]; FROM_EQ_ENVFROM(0.00)[]; SPAMHAUS_XBL(0.00)[2a07:de40:b281:104:10:150:64:97:from]; R_RATELIMIT(0.00)[to_ip_from(RLkdkdrsxe9hqhhs5ask8616i6)]; RCVD_TLS_ALL(0.00)[]; DKIM_TRACE(0.00)[suse.com:+]; TO_DN_SOME(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:dkim,suse.com:mid,suse.com:email,imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns] X-Rspamd-Queue-Id: 09FD15BD2B X-Spam-Flag: NO X-Spam-Score: -3.01 X-Spam-Level: Content-Type: text/plain; charset="utf-8" Switch the core parts of the x86 events subsystem to use the new msr_*() functions instead of the rdmsr*()/wrmsr*() ones. Use msr_write_noser() in case there is another MSR write later in the same function and msr_write_ser() for the last MSR write in a function. Signed-off-by: Juergen Gross --- arch/x86/events/core.c | 42 ++++++++++++++++++------------------ arch/x86/events/msr.c | 2 +- arch/x86/events/perf_event.h | 26 +++++++++++----------- arch/x86/events/probe.c | 2 +- arch/x86/events/rapl.c | 8 +++---- 5 files changed, 40 insertions(+), 40 deletions(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 810ab21ffd99..c15e0d1a6658 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -279,7 +279,7 @@ bool check_hw_exists(struct pmu *pmu, unsigned long *cn= tr_mask, */ for_each_set_bit(i, cntr_mask, X86_PMC_IDX_MAX) { reg =3D x86_pmu_config_addr(i); - ret =3D rdmsrq_safe(reg, &val); + ret =3D msr_read_safe(reg, &val); if (ret) goto msr_fail; if (val & ARCH_PERFMON_EVENTSEL_ENABLE) { @@ -293,7 +293,7 @@ bool check_hw_exists(struct pmu *pmu, unsigned long *cn= tr_mask, =20 if (*(u64 *)fixed_cntr_mask) { reg =3D MSR_ARCH_PERFMON_FIXED_CTR_CTRL; - ret =3D rdmsrq_safe(reg, &val); + ret =3D msr_read_safe(reg, &val); if (ret) goto msr_fail; for_each_set_bit(i, fixed_cntr_mask, X86_PMC_IDX_MAX) { @@ -324,11 +324,11 @@ bool check_hw_exists(struct pmu *pmu, unsigned long *= cntr_mask, * (qemu/kvm) that don't trap on the MSR access and always return 0s. */ reg =3D x86_pmu_event_addr(reg_safe); - if (rdmsrq_safe(reg, &val)) + if (msr_read_safe(reg, &val)) goto msr_fail; val ^=3D 0xffffUL; - ret =3D wrmsrq_safe(reg, val); - ret |=3D rdmsrq_safe(reg, &val_new); + ret =3D msr_write_safe_noser(reg, val); + ret |=3D msr_read_safe(reg, &val_new); if (ret || val !=3D val_new) goto msr_fail; =20 @@ -713,13 +713,13 @@ void x86_pmu_disable_all(void) =20 if (!test_bit(idx, cpuc->active_mask)) continue; - rdmsrq(x86_pmu_config_addr(idx), val); + val =3D msr_read(x86_pmu_config_addr(idx)); if (!(val & ARCH_PERFMON_EVENTSEL_ENABLE)) continue; val &=3D ~ARCH_PERFMON_EVENTSEL_ENABLE; - wrmsrq(x86_pmu_config_addr(idx), val); + msr_write_noser(x86_pmu_config_addr(idx), val); if (is_counter_pair(hwc)) - wrmsrq(x86_pmu_config_addr(idx + 1), 0); + msr_write_noser(x86_pmu_config_addr(idx + 1), 0); } } =20 @@ -1446,14 +1446,14 @@ int x86_perf_event_set_period(struct perf_event *ev= ent) */ local64_set(&hwc->prev_count, (u64)-left); =20 - wrmsrq(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); + msr_write_noser(hwc->event_base, (u64)(-left) & x86_pmu.cntval_mask); =20 /* * Sign extend the Merge event counter's upper 16 bits since * we currently declare a 48-bit counter width */ if (is_counter_pair(hwc)) - wrmsrq(x86_pmu_event_addr(idx + 1), 0xffff); + msr_write_noser(x86_pmu_event_addr(idx + 1), 0xffff); =20 perf_event_update_userpage(event); =20 @@ -1575,10 +1575,10 @@ void perf_event_print_debug(void) return; =20 if (x86_pmu.version >=3D 2) { - rdmsrq(MSR_CORE_PERF_GLOBAL_CTRL, ctrl); - rdmsrq(MSR_CORE_PERF_GLOBAL_STATUS, status); - rdmsrq(MSR_CORE_PERF_GLOBAL_OVF_CTRL, overflow); - rdmsrq(MSR_ARCH_PERFMON_FIXED_CTR_CTRL, fixed); + ctrl =3D msr_read(MSR_CORE_PERF_GLOBAL_CTRL); + status =3D msr_read(MSR_CORE_PERF_GLOBAL_STATUS); + overflow =3D msr_read(MSR_CORE_PERF_GLOBAL_OVF_CTRL); + fixed =3D msr_read(MSR_ARCH_PERFMON_FIXED_CTR_CTRL); =20 pr_info("\n"); pr_info("CPU#%d: ctrl: %016llx\n", cpu, ctrl); @@ -1586,19 +1586,19 @@ void perf_event_print_debug(void) pr_info("CPU#%d: overflow: %016llx\n", cpu, overflow); pr_info("CPU#%d: fixed: %016llx\n", cpu, fixed); if (pebs_constraints) { - rdmsrq(MSR_IA32_PEBS_ENABLE, pebs); + pebs =3D msr_read(MSR_IA32_PEBS_ENABLE); pr_info("CPU#%d: pebs: %016llx\n", cpu, pebs); } if (x86_pmu.lbr_nr) { - rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); + debugctl =3D msr_read(MSR_IA32_DEBUGCTLMSR); pr_info("CPU#%d: debugctl: %016llx\n", cpu, debugctl); } } pr_info("CPU#%d: active: %016llx\n", cpu, *(u64 *)cpuc->active_mask); =20 for_each_set_bit(idx, cntr_mask, X86_PMC_IDX_MAX) { - rdmsrq(x86_pmu_config_addr(idx), pmc_ctrl); - rdmsrq(x86_pmu_event_addr(idx), pmc_count); + pmc_ctrl =3D msr_read(x86_pmu_config_addr(idx)); + pmc_count =3D msr_read(x86_pmu_event_addr(idx)); =20 prev_left =3D per_cpu(pmc_prev_left[idx], cpu); =20 @@ -1612,7 +1612,7 @@ void perf_event_print_debug(void) for_each_set_bit(idx, fixed_cntr_mask, X86_PMC_IDX_MAX) { if (fixed_counter_disabled(idx, cpuc->pmu)) continue; - rdmsrq(x86_pmu_fixed_ctr_addr(idx), pmc_count); + pmc_count =3D msr_read(x86_pmu_fixed_ctr_addr(idx)); =20 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n", cpu, idx, pmc_count); @@ -2560,9 +2560,9 @@ void perf_clear_dirty_counters(void) if (!test_bit(i - INTEL_PMC_IDX_FIXED, hybrid(cpuc->pmu, fixed_cntr_mas= k))) continue; =20 - wrmsrq(x86_pmu_fixed_ctr_addr(i - INTEL_PMC_IDX_FIXED), 0); + msr_write_noser(x86_pmu_fixed_ctr_addr(i - INTEL_PMC_IDX_FIXED), 0); } else { - wrmsrq(x86_pmu_event_addr(i), 0); + msr_write_noser(x86_pmu_event_addr(i), 0); } } =20 diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c index 76d6418c5055..09d5b2808727 100644 --- a/arch/x86/events/msr.c +++ b/arch/x86/events/msr.c @@ -158,7 +158,7 @@ static inline u64 msr_read_counter(struct perf_event *e= vent) u64 now; =20 if (event->hw.event_base) - rdmsrq(event->hw.event_base, now); + now =3D msr_read(event->hw.event_base); else now =3D rdtsc_ordered(); =20 diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index fad87d3c8b2c..cce2e7b67c01 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -1271,16 +1271,16 @@ static inline void __x86_pmu_enable_event(struct hw= _perf_event *hwc, u64 disable_mask =3D __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); =20 if (hwc->extra_reg.reg) - wrmsrq(hwc->extra_reg.reg, hwc->extra_reg.config); + msr_write_noser(hwc->extra_reg.reg, hwc->extra_reg.config); =20 /* * Add enabled Merge event on next counter * if large increment event being enabled on this counter */ if (is_counter_pair(hwc)) - wrmsrq(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair_en); + msr_write_noser(x86_pmu_config_addr(hwc->idx + 1), x86_pmu.perf_ctr_pair= _en); =20 - wrmsrq(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask); + msr_write_ser(hwc->config_base, (hwc->config | enable_mask) & ~disable_ma= sk); } =20 void x86_pmu_enable_all(int added); @@ -1296,10 +1296,10 @@ static inline void x86_pmu_disable_event(struct per= f_event *event) u64 disable_mask =3D __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); struct hw_perf_event *hwc =3D &event->hw; =20 - wrmsrq(hwc->config_base, hwc->config & ~disable_mask); + msr_write_ser(hwc->config_base, hwc->config & ~disable_mask); =20 if (is_counter_pair(hwc)) - wrmsrq(x86_pmu_config_addr(hwc->idx + 1), 0); + msr_write_ser(x86_pmu_config_addr(hwc->idx + 1), 0); } =20 void x86_pmu_enable_event(struct perf_event *event); @@ -1473,12 +1473,12 @@ static __always_inline void __amd_pmu_lbr_disable(v= oid) { u64 dbg_ctl, dbg_extn_cfg; =20 - rdmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg); - wrmsrq(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN); + dbg_extn_cfg =3D msr_read(MSR_AMD_DBG_EXTN_CFG); + msr_write_ser(MSR_AMD_DBG_EXTN_CFG, dbg_extn_cfg & ~DBG_EXTN_CFG_LBRV2EN); =20 if (cpu_feature_enabled(X86_FEATURE_AMD_LBR_PMC_FREEZE)) { - rdmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl); - wrmsrq(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); + dbg_ctl =3D msr_read(MSR_IA32_DEBUGCTLMSR); + msr_write_ser(MSR_IA32_DEBUGCTLMSR, dbg_ctl & ~DEBUGCTLMSR_FREEZE_LBRS_O= N_PMI); } } =20 @@ -1619,21 +1619,21 @@ static inline bool intel_pmu_has_bts(struct perf_ev= ent *event) =20 static __always_inline void __intel_pmu_pebs_disable_all(void) { - wrmsrq(MSR_IA32_PEBS_ENABLE, 0); + msr_write_ser(MSR_IA32_PEBS_ENABLE, 0); } =20 static __always_inline void __intel_pmu_arch_lbr_disable(void) { - wrmsrq(MSR_ARCH_LBR_CTL, 0); + msr_write_ser(MSR_ARCH_LBR_CTL, 0); } =20 static __always_inline void __intel_pmu_lbr_disable(void) { u64 debugctl; =20 - rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); + debugctl =3D msr_read(MSR_IA32_DEBUGCTLMSR); debugctl &=3D ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI); - wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctl); + msr_write_ser(MSR_IA32_DEBUGCTLMSR, debugctl); } =20 int intel_pmu_save_and_restart(struct perf_event *event); diff --git a/arch/x86/events/probe.c b/arch/x86/events/probe.c index bb719d0d3f0b..85d591fab26c 100644 --- a/arch/x86/events/probe.c +++ b/arch/x86/events/probe.c @@ -45,7 +45,7 @@ perf_msr_probe(struct perf_msr *msr, int cnt, bool zero, = void *data) if (msr[bit].test && !msr[bit].test(bit, data)) continue; /* Virt sucks; you cannot tell if a R/O MSR is present :/ */ - if (rdmsrq_safe(msr[bit].msr, &val)) + if (msr_read_safe(msr[bit].msr, &val)) continue; =20 mask =3D msr[bit].mask; diff --git a/arch/x86/events/rapl.c b/arch/x86/events/rapl.c index 8ed03c32f560..bb9ecf78fd90 100644 --- a/arch/x86/events/rapl.c +++ b/arch/x86/events/rapl.c @@ -193,7 +193,7 @@ static inline unsigned int get_rapl_pmu_idx(int cpu, in= t scope) static inline u64 rapl_read_counter(struct perf_event *event) { u64 raw; - rdmsrq(event->hw.event_base, raw); + raw =3D msr_read(event->hw.event_base); return raw; } =20 @@ -222,7 +222,7 @@ static u64 rapl_event_update(struct perf_event *event) =20 prev_raw_count =3D local64_read(&hwc->prev_count); do { - rdmsrq(event->hw.event_base, new_raw_count); + new_raw_count =3D msr_read(event->hw.event_base); } while (!local64_try_cmpxchg(&hwc->prev_count, &prev_raw_count, new_raw_count)); =20 @@ -611,8 +611,8 @@ static int rapl_check_hw_unit(void) u64 msr_rapl_power_unit_bits; int i; =20 - /* protect rdmsrq() to handle virtualization */ - if (rdmsrq_safe(rapl_model->msr_power_unit, &msr_rapl_power_unit_bits)) + /* protect msr_read() to handle virtualization */ + if (msr_read_safe(rapl_model->msr_power_unit, &msr_rapl_power_unit_bits)) return -1; for (i =3D 0; i < NR_RAPL_PKG_DOMAINS; i++) rapl_pkg_hw_unit[i] =3D (msr_rapl_power_unit_bits >> 8) & 0x1FULL; --=20 2.53.0 From nobody Sat Jun 20 04:58:29 2026 Received: from smtp-out2.suse.de (smtp-out2.suse.de [195.135.223.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9722938BF7F for ; Mon, 20 Apr 2026 09:17:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=195.135.223.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776676641; cv=none; b=MC2nITt7G5fGVRCG8a/EyotcLYkIBYn5z8JtgaKiG4bMGvRuVV5Vc3InDS5kNJr3Ho5mrozwREW5ksYsiss+ijKL9Pg7uDGPu4aDdqil4NXU72dvGYUGlskmDXnpB+t1LLrVOiWpFKQAHBITRltiUQ1t8falSufKTyyuIM6Sg8k= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776676641; c=relaxed/simple; bh=VpvBuRNPT3bhWJZbTkc34JdW51Anhsqf2oLWQPTM6EU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FZhU2YzATnsOohOha0vqMFXu0l1OYThggoskuPDDKRG2N/N32iHnC39aJlpWj+WwxmlsJJPyTVvh7334yFC3/RbxeY29t7HyDZe6uWd5zkGZ692Aw1FpSWvvTMp5lITOkm1xNybPbMV2c2yp7lGv3gmHLao/2PhkajKE9Wpa7qk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com; spf=pass smtp.mailfrom=suse.com; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=r2fWXTxK; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b=r2fWXTxK; arc=none smtp.client-ip=195.135.223.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=suse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=suse.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="r2fWXTxK"; dkim=pass (1024-bit key) header.d=suse.com header.i=@suse.com header.b="r2fWXTxK" Received: from imap1.dmz-prg2.suse.org (imap1.dmz-prg2.suse.org [IPv6:2a07:de40:b281:104:10:150:64:97]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by smtp-out2.suse.de (Postfix) with ESMTPS id 8DDBC5BCE0; Mon, 20 Apr 2026 09:17:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776676637; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nebyTL0m3dvY/T9luoQeVEXF9GNR4hCg59V5TI29xro=; b=r2fWXTxK0Rg7Rpvkd6V19+I6lK3slP9Dx/RJpOiFEzBps+pO8z2R1i7nVUMnJsUR0aGImc fOdlPCFPEIiFleahZ3mYwpIOWyzsjJbyjs7YPXTBeAmW4NjK+gy9lzFPu3tGNcldAAasml LWXNih/682QGG31mQWi7V8md8FmzUbQ= Authentication-Results: smtp-out2.suse.de; dkim=pass header.d=suse.com header.s=susede1 header.b=r2fWXTxK DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=suse.com; s=susede1; t=1776676637; h=from:from:reply-to:date:date:message-id:message-id:to:to:cc:cc: mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nebyTL0m3dvY/T9luoQeVEXF9GNR4hCg59V5TI29xro=; b=r2fWXTxK0Rg7Rpvkd6V19+I6lK3slP9Dx/RJpOiFEzBps+pO8z2R1i7nVUMnJsUR0aGImc fOdlPCFPEIiFleahZ3mYwpIOWyzsjJbyjs7YPXTBeAmW4NjK+gy9lzFPu3tGNcldAAasml LWXNih/682QGG31mQWi7V8md8FmzUbQ= Received: from imap1.dmz-prg2.suse.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by imap1.dmz-prg2.suse.org (Postfix) with ESMTPS id 50093593AE; Mon, 20 Apr 2026 09:17:17 +0000 (UTC) Received: from dovecot-director2.suse.de ([2a07:de40:b281:106:10:150:64:167]) by imap1.dmz-prg2.suse.org with ESMTPSA id rIN2Eh3v5WnhPQAAD6G6ig (envelope-from ); Mon, 20 Apr 2026 09:17:17 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, x86@kernel.org, linux-edac@vger.kernel.org Cc: Juergen Gross , Tony Luck , Borislav Petkov , Thomas Gleixner , Ingo Molnar , Dave Hansen , "H. Peter Anvin" Subject: [PATCH RFC 6/6] x86/cpu/mce: Switch code to use new MSR access functions Date: Mon, 20 Apr 2026 11:16:34 +0200 Message-ID: <20260420091634.128787-7-jgross@suse.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260420091634.128787-1-jgross@suse.com> References: <20260420091634.128787-1-jgross@suse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spamd-Result: default: False [-3.01 / 50.00]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; R_DKIM_ALLOW(-0.20)[suse.com:s=susede1]; NEURAL_HAM_SHORT(-0.20)[-1.000]; MIME_GOOD(-0.10)[text/plain]; MX_GOOD(-0.01)[]; URIBL_BLOCKED(0.00)[suse.com:mid,suse.com:dkim,suse.com:email,imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns]; TO_MATCH_ENVRCPT_ALL(0.00)[]; ARC_NA(0.00)[]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; TO_DN_SOME(0.00)[]; MIME_TRACE(0.00)[0:+]; FUZZY_RATELIMITED(0.00)[rspamd.com]; RBL_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:104:10:150:64:97:from]; RCVD_TLS_ALL(0.00)[]; DKIM_TRACE(0.00)[suse.com:+]; RCVD_COUNT_TWO(0.00)[2]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; SPAMHAUS_XBL(0.00)[2a07:de40:b281:104:10:150:64:97:from]; DNSWL_BLOCKED(0.00)[2a07:de40:b281:104:10:150:64:97:from]; RECEIVED_SPAMHAUS_BLOCKED_OPENRESOLVER(0.00)[2a07:de40:b281:106:10:150:64:167:received]; RCPT_COUNT_SEVEN(0.00)[10]; R_RATELIMIT(0.00)[to_ip_from(RLkdkdrsxe9hqhhs5ask8616i6)]; RCVD_VIA_SMTP_AUTH(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:mid,suse.com:dkim,suse.com:email,imap1.dmz-prg2.suse.org:helo,imap1.dmz-prg2.suse.org:rdns] X-Rspamd-Action: no action X-Spam-Flag: NO X-Spam-Score: -3.01 X-Spam-Level: X-Rspamd-Server: rspamd1.dmz-prg2.suse.org X-Rspamd-Queue-Id: 8DDBC5BCE0 Content-Type: text/plain; charset="utf-8" Switch the x86 MCE code to use the new msr_*() functions instead of the rdmsr*()/wrmsr*() ones. Signed-off-by: Juergen Gross --- arch/x86/kernel/cpu/mce/amd.c | 101 +++++++++++++++--------------- arch/x86/kernel/cpu/mce/core.c | 18 +++--- arch/x86/kernel/cpu/mce/inject.c | 40 ++++++------ arch/x86/kernel/cpu/mce/intel.c | 32 +++++----- arch/x86/kernel/cpu/mce/p5.c | 16 ++--- arch/x86/kernel/cpu/mce/winchip.c | 10 +-- 6 files changed, 109 insertions(+), 108 deletions(-) diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c index 6605a0224659..56cdf9c46d92 100644 --- a/arch/x86/kernel/cpu/mce/amd.c +++ b/arch/x86/kernel/cpu/mce/amd.c @@ -280,11 +280,11 @@ static void smca_configure(unsigned int bank, unsigne= d int cpu) u8 *bank_counts =3D this_cpu_ptr(smca_bank_counts); const struct smca_hwid *s_hwid; unsigned int i, hwid_mcatype; - u32 high, low; + struct msr val; u32 smca_config =3D MSR_AMD64_SMCA_MCx_CONFIG(bank); =20 /* Set appropriate bits in MCA_CONFIG */ - if (!rdmsr_safe(smca_config, &low, &high)) { + if (!msr_read_safe(smca_config, &val.q)) { /* * OS is required to set the MCAX bit to acknowledge that it is * now using the new MSR ranges and new registers under each @@ -294,7 +294,7 @@ static void smca_configure(unsigned int bank, unsigned = int cpu) * * MCA_CONFIG[MCAX] is bit 32 (0 in the high portion of the MSR.) */ - high |=3D BIT(0); + val.h |=3D BIT(0); =20 /* * SMCA sets the Deferred Error Interrupt type per bank. @@ -307,9 +307,9 @@ static void smca_configure(unsigned int bank, unsigned = int cpu) * APIC based interrupt. First, check that no interrupt has been * set. */ - if ((low & BIT(5)) && !((high >> 5) & 0x3) && data->dfr_intr_en) { + if ((val.l & BIT(5)) && !((val.h >> 5) & 0x3) && data->dfr_intr_en) { __set_bit(bank, data->dfr_intr_banks); - high |=3D BIT(5); + val.h |=3D BIT(5); } =20 /* @@ -324,33 +324,33 @@ static void smca_configure(unsigned int bank, unsigne= d int cpu) * The OS should set this to inform the platform that the OS is ready * to handle the MCA Thresholding interrupt. */ - if ((low & BIT(10)) && data->thr_intr_en) { + if ((val.l & BIT(10)) && data->thr_intr_en) { __set_bit(bank, data->thr_intr_banks); - high |=3D BIT(8); + val.h |=3D BIT(8); } =20 - this_cpu_ptr(mce_banks_array)[bank].lsb_in_status =3D !!(low & BIT(8)); + this_cpu_ptr(mce_banks_array)[bank].lsb_in_status =3D !!(val.l & BIT(8)); =20 - if (low & MCI_CONFIG_PADDRV) + if (val.l & MCI_CONFIG_PADDRV) this_cpu_ptr(smca_banks)[bank].paddrv =3D 1; =20 - wrmsr(smca_config, low, high); + msr_write_ser(smca_config, val.q); } =20 - if (rdmsr_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &low, &high)) { + if (msr_read_safe(MSR_AMD64_SMCA_MCx_IPID(bank), &val.q)) { pr_warn("Failed to read MCA_IPID for bank %d\n", bank); return; } =20 - hwid_mcatype =3D HWID_MCATYPE(high & MCI_IPID_HWID, - (high & MCI_IPID_MCATYPE) >> 16); + hwid_mcatype =3D HWID_MCATYPE(val.h & MCI_IPID_HWID, + (val.h & MCI_IPID_MCATYPE) >> 16); =20 for (i =3D 0; i < ARRAY_SIZE(smca_hwid_mcatypes); i++) { s_hwid =3D &smca_hwid_mcatypes[i]; =20 if (hwid_mcatype =3D=3D s_hwid->hwid_mcatype) { this_cpu_ptr(smca_banks)[bank].hwid =3D s_hwid; - this_cpu_ptr(smca_banks)[bank].id =3D low; + this_cpu_ptr(smca_banks)[bank].id =3D val.l; this_cpu_ptr(smca_banks)[bank].sysfs_id =3D bank_counts[s_hwid->bank_ty= pe]++; break; } @@ -432,50 +432,50 @@ static bool lvt_off_valid(struct threshold_block *b, = int apic, u32 lo, u32 hi) static void threshold_restart_block(void *_tr) { struct thresh_restart *tr =3D _tr; - u32 hi, lo; + struct msr val; =20 /* sysfs write might race against an offline operation */ if (!this_cpu_read(threshold_banks) && !tr->set_lvt_off) return; =20 - rdmsr(tr->b->address, lo, hi); + val.q =3D msr_read(tr->b->address); =20 /* * Reset error count and overflow bit. * This is done during init or after handling an interrupt. */ - if (hi & MASK_OVERFLOW_HI || tr->set_lvt_off) { - hi &=3D ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI); - hi |=3D THRESHOLD_MAX - tr->b->threshold_limit; + if (val.h & MASK_OVERFLOW_HI || tr->set_lvt_off) { + val.h &=3D ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI); + val.h |=3D THRESHOLD_MAX - tr->b->threshold_limit; } else if (tr->old_limit) { /* change limit w/o reset */ - int new_count =3D (hi & THRESHOLD_MAX) + + int new_count =3D (val.h & THRESHOLD_MAX) + (tr->old_limit - tr->b->threshold_limit); =20 - hi =3D (hi & ~MASK_ERR_COUNT_HI) | + val.h =3D (val.h & ~MASK_ERR_COUNT_HI) | (new_count & THRESHOLD_MAX); } =20 /* clear IntType */ - hi &=3D ~MASK_INT_TYPE_HI; + val.h &=3D ~MASK_INT_TYPE_HI; =20 if (!tr->b->interrupt_capable) goto done; =20 if (tr->set_lvt_off) { - if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) { + if (lvt_off_valid(tr->b, tr->lvt_off, val.l, val.h)) { /* set new lvt offset */ - hi &=3D ~MASK_LVTOFF_HI; - hi |=3D tr->lvt_off << 20; + val.h &=3D ~MASK_LVTOFF_HI; + val.h |=3D tr->lvt_off << 20; } } =20 if (tr->b->interrupt_enable) - hi |=3D INT_TYPE_APIC; + val.h |=3D INT_TYPE_APIC; =20 done: =20 - hi |=3D MASK_COUNT_EN_HI; - wrmsr(tr->b->address, lo, hi); + val.h |=3D MASK_COUNT_EN_HI; + msr_write_ser(tr->b->address, val.q); } =20 static void threshold_restart_bank(unsigned int bank, bool intr_en) @@ -658,12 +658,12 @@ static void disable_err_thresholding(struct cpuinfo_x= 86 *c, unsigned int bank) return; } =20 - rdmsrq(MSR_K7_HWCR, hwcr); + hwcr =3D msr_read(MSR_K7_HWCR); =20 /* McStatusWrEn has to be set */ need_toggle =3D !(hwcr & BIT(18)); if (need_toggle) - wrmsrq(MSR_K7_HWCR, hwcr | BIT(18)); + msr_write_ser(MSR_K7_HWCR, hwcr | BIT(18)); =20 /* Clear CntP bit safely */ for (i =3D 0; i < num_msrs; i++) @@ -671,7 +671,7 @@ static void disable_err_thresholding(struct cpuinfo_x86= *c, unsigned int bank) =20 /* restore old settings */ if (need_toggle) - wrmsrq(MSR_K7_HWCR, hwcr); + msr_write_ser(MSR_K7_HWCR, hwcr); } =20 static void amd_apply_cpu_quirks(struct cpuinfo_x86 *c) @@ -710,7 +710,7 @@ static void smca_enable_interrupt_vectors(void) if (!mce_flags.smca || !mce_flags.succor) return; =20 - if (rdmsrq_safe(MSR_CU_DEF_ERR, &mca_intr_cfg)) + if (msr_read_safe(MSR_CU_DEF_ERR, &mca_intr_cfg)) return; =20 offset =3D (mca_intr_cfg & SMCA_THR_LVT_OFF) >> 12; @@ -726,7 +726,8 @@ static void smca_enable_interrupt_vectors(void) void mce_amd_feature_init(struct cpuinfo_x86 *c) { unsigned int bank, block, cpu =3D smp_processor_id(); - u32 low =3D 0, high =3D 0, address =3D 0; + struct msr val =3D { .q =3D 0 }; + u32 address =3D 0; int offset =3D -1; =20 amd_apply_cpu_quirks(c); @@ -746,21 +747,21 @@ void mce_amd_feature_init(struct cpuinfo_x86 *c) disable_err_thresholding(c, bank); =20 for (block =3D 0; block < NR_BLOCKS; ++block) { - address =3D get_block_address(address, low, high, bank, block, cpu); + address =3D get_block_address(address, val.l, val.h, bank, block, cpu); if (!address) break; =20 - if (rdmsr_safe(address, &low, &high)) + if (msr_read_safe(address, &val.q)) break; =20 - if (!(high & MASK_VALID_HI)) + if (!(val.h & MASK_VALID_HI)) continue; =20 - if (!(high & MASK_CNTP_HI) || - (high & MASK_LOCKED_HI)) + if (!(val.h & MASK_CNTP_HI) || + (val.h & MASK_LOCKED_HI)) continue; =20 - offset =3D prepare_threshold_block(bank, block, address, offset, high); + offset =3D prepare_threshold_block(bank, block, address, offset, val.h); } } } @@ -969,13 +970,13 @@ store_threshold_limit(struct threshold_block *b, cons= t char *buf, size_t size) =20 static ssize_t show_error_count(struct threshold_block *b, char *buf) { - u32 lo, hi; + struct msr val; =20 /* CPU might be offline by now */ - if (rdmsr_on_cpu(b->cpu, b->address, &lo, &hi)) + if (msr_read_on_cpu(b->cpu, b->address, &val.q)) return -ENODEV; =20 - return sprintf(buf, "%u\n", ((hi & THRESHOLD_MAX) - + return sprintf(buf, "%u\n", ((val.h & THRESHOLD_MAX) - (THRESHOLD_MAX - b->threshold_limit))); } =20 @@ -1083,24 +1084,24 @@ static int allocate_threshold_blocks(unsigned int c= pu, struct threshold_bank *tb u32 address) { struct threshold_block *b =3D NULL; - u32 low, high; + struct msr val; int err; =20 if ((bank >=3D this_cpu_read(mce_num_banks)) || (block >=3D NR_BLOCKS)) return 0; =20 - if (rdmsr_safe(address, &low, &high)) + if (msr_read_safe(address, &val.q)) return 0; =20 - if (!(high & MASK_VALID_HI)) { + if (!(val.h & MASK_VALID_HI)) { if (block) goto recurse; else return 0; } =20 - if (!(high & MASK_CNTP_HI) || - (high & MASK_LOCKED_HI)) + if (!(val.h & MASK_CNTP_HI) || + (val.h & MASK_LOCKED_HI)) goto recurse; =20 b =3D kzalloc_obj(struct threshold_block); @@ -1112,7 +1113,7 @@ static int allocate_threshold_blocks(unsigned int cpu= , struct threshold_bank *tb b->cpu =3D cpu; b->address =3D address; b->interrupt_enable =3D 0; - b->interrupt_capable =3D lvt_interrupt_supported(bank, high); + b->interrupt_capable =3D lvt_interrupt_supported(bank, val.h); b->threshold_limit =3D get_thr_limit(); =20 if (b->interrupt_capable) { @@ -1124,13 +1125,13 @@ static int allocate_threshold_blocks(unsigned int c= pu, struct threshold_bank *tb =20 list_add(&b->miscj, &tb->miscj); =20 - mce_threshold_block_init(b, (high & MASK_LVTOFF_HI) >> 20); + mce_threshold_block_init(b, (val.h & MASK_LVTOFF_HI) >> 20); =20 err =3D kobject_init_and_add(&b->kobj, &threshold_ktype, tb->kobj, get_na= me(cpu, bank, b)); if (err) goto out_free; recurse: - address =3D get_block_address(address, low, high, bank, ++block, cpu); + address =3D get_block_address(address, val.l, val.h, bank, ++block, cpu); if (!address) return 0; =20 diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index 8dd424ac5de8..acd73d96cc01 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -1871,7 +1871,7 @@ static void __mcheck_cpu_cap_init(void) u64 cap; u8 b; =20 - rdmsrq(MSR_IA32_MCG_CAP, cap); + cap =3D msr_read(MSR_IA32_MCG_CAP); =20 b =3D cap & MCG_BANKCNT_MASK; =20 @@ -1890,9 +1890,9 @@ static void __mcheck_cpu_init_generic(void) { u64 cap; =20 - rdmsrq(MSR_IA32_MCG_CAP, cap); + cap =3D msr_read(MSR_IA32_MCG_CAP); if (cap & MCG_CTL_P) - wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff); + msr_write_ser(MSR_IA32_MCG_CTL, ~0ULL); } =20 static void __mcheck_cpu_init_prepare_banks(void) @@ -1919,10 +1919,10 @@ static void __mcheck_cpu_init_prepare_banks(void) if (!b->init) continue; =20 - wrmsrq(mca_msr_reg(i, MCA_CTL), b->ctl); - wrmsrq(mca_msr_reg(i, MCA_STATUS), 0); + msr_write_ser(mca_msr_reg(i, MCA_CTL), b->ctl); + msr_write_ser(mca_msr_reg(i, MCA_STATUS), 0); =20 - rdmsrq(mca_msr_reg(i, MCA_CTL), msrval); + msrval =3D msr_read(mca_msr_reg(i, MCA_CTL)); b->init =3D !!msrval; } } @@ -2240,7 +2240,7 @@ void mca_bsp_init(struct cpuinfo_x86 *c) if (mce_flags.smca) smca_bsp_init(); =20 - rdmsrq(MSR_IA32_MCG_CAP, cap); + cap =3D msr_read(MSR_IA32_MCG_CAP); =20 /* Use accurate RIP reporting if available. */ if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >=3D 9) @@ -2420,7 +2420,7 @@ static void mce_disable_error_reporting(void) struct mce_bank *b =3D &mce_banks[i]; =20 if (b->init) - wrmsrq(mca_msr_reg(i, MCA_CTL), 0); + msr_write_ser(mca_msr_reg(i, MCA_CTL), 0); } return; } @@ -2776,7 +2776,7 @@ static void mce_reenable_cpu(void) struct mce_bank *b =3D &mce_banks[i]; =20 if (b->init) - wrmsrq(mca_msr_reg(i, MCA_CTL), b->ctl); + msr_write_ser(mca_msr_reg(i, MCA_CTL), b->ctl); } } =20 diff --git a/arch/x86/kernel/cpu/mce/inject.c b/arch/x86/kernel/cpu/mce/inj= ect.c index d02c4f556cd0..157fb0777bd2 100644 --- a/arch/x86/kernel/cpu/mce/inject.c +++ b/arch/x86/kernel/cpu/mce/inject.c @@ -316,18 +316,18 @@ static struct notifier_block inject_nb =3D { */ static int toggle_hw_mce_inject(unsigned int cpu, bool enable) { - u32 l, h; + struct msr val; int err; =20 - err =3D rdmsr_on_cpu(cpu, MSR_K7_HWCR, &l, &h); + err =3D msr_read_on_cpu(cpu, MSR_K7_HWCR, &val.q); if (err) { pr_err("%s: error reading HWCR\n", __func__); return err; } =20 - enable ? (l |=3D BIT(18)) : (l &=3D ~BIT(18)); + enable ? (val.l |=3D BIT(18)) : (val.l &=3D ~BIT(18)); =20 - err =3D wrmsr_on_cpu(cpu, MSR_K7_HWCR, l, h); + err =3D msr_write_on_cpu(cpu, MSR_K7_HWCR, val.q); if (err) pr_err("%s: error writing HWCR\n", __func__); =20 @@ -476,27 +476,27 @@ static void prepare_msrs(void *info) struct mce m =3D *(struct mce *)info; u8 b =3D m.bank; =20 - wrmsrq(MSR_IA32_MCG_STATUS, m.mcgstatus); + msr_write_ser(MSR_IA32_MCG_STATUS, m.mcgstatus); =20 if (boot_cpu_has(X86_FEATURE_SMCA)) { if (m.inject_flags =3D=3D DFR_INT_INJ) { - wrmsrq(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); - wrmsrq(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); + msr_write_ser(MSR_AMD64_SMCA_MCx_DESTAT(b), m.status); + msr_write_ser(MSR_AMD64_SMCA_MCx_DEADDR(b), m.addr); } else { - wrmsrq(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); - wrmsrq(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); + msr_write_ser(MSR_AMD64_SMCA_MCx_STATUS(b), m.status); + msr_write_ser(MSR_AMD64_SMCA_MCx_ADDR(b), m.addr); } =20 - wrmsrq(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); + msr_write_ser(MSR_AMD64_SMCA_MCx_SYND(b), m.synd); =20 if (m.misc) - wrmsrq(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); + msr_write_ser(MSR_AMD64_SMCA_MCx_MISC(b), m.misc); } else { - wrmsrq(MSR_IA32_MCx_STATUS(b), m.status); - wrmsrq(MSR_IA32_MCx_ADDR(b), m.addr); + msr_write_ser(MSR_IA32_MCx_STATUS(b), m.status); + msr_write_ser(MSR_IA32_MCx_ADDR(b), m.addr); =20 if (m.misc) - wrmsrq(MSR_IA32_MCx_MISC(b), m.misc); + msr_write_ser(MSR_IA32_MCx_MISC(b), m.misc); } } =20 @@ -590,7 +590,7 @@ static int inj_bank_set(void *data, u64 val) u64 cap; =20 /* Get bank count on target CPU so we can handle non-uniform values. */ - rdmsrq_on_cpu(m->extcpu, MSR_IA32_MCG_CAP, &cap); + msr_read_on_cpu(m->extcpu, MSR_IA32_MCG_CAP, &cap); n_banks =3D cap & MCG_BANKCNT_MASK; =20 if (val >=3D n_banks) { @@ -614,7 +614,7 @@ static int inj_bank_set(void *data, u64 val) if (cpu_feature_enabled(X86_FEATURE_SMCA)) { u64 ipid; =20 - if (rdmsrq_on_cpu(m->extcpu, MSR_AMD64_SMCA_MCx_IPID(val), &ipid)) { + if (msr_read_on_cpu(m->extcpu, MSR_AMD64_SMCA_MCx_IPID(val), &ipid)) { pr_err("Error reading IPID on CPU%d\n", m->extcpu); return -EINVAL; } @@ -742,15 +742,15 @@ static void check_hw_inj_possible(void) u64 status =3D MCI_STATUS_VAL, ipid; =20 /* Check whether bank is populated */ - rdmsrq(MSR_AMD64_SMCA_MCx_IPID(bank), ipid); + ipid =3D msr_read(MSR_AMD64_SMCA_MCx_IPID(bank)); if (!ipid) continue; =20 toggle_hw_mce_inject(cpu, true); =20 - wrmsrq_safe(mca_msr_reg(bank, MCA_STATUS), status); - rdmsrq_safe(mca_msr_reg(bank, MCA_STATUS), &status); - wrmsrq_safe(mca_msr_reg(bank, MCA_STATUS), 0); + msr_write_safe_ser(mca_msr_reg(bank, MCA_STATUS), status); + msr_read_safe(mca_msr_reg(bank, MCA_STATUS), &status); + msr_write_safe_ser(mca_msr_reg(bank, MCA_STATUS), 0); =20 if (!status) { hw_injection_possible =3D false; diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/inte= l.c index 4655223ba560..cd24b55c6e0b 100644 --- a/arch/x86/kernel/cpu/mce/intel.c +++ b/arch/x86/kernel/cpu/mce/intel.c @@ -94,7 +94,7 @@ static bool cmci_supported(int *banks) if (!boot_cpu_has(X86_FEATURE_APIC) || lapic_get_maxlvt() < 6) return false; =20 - rdmsrq(MSR_IA32_MCG_CAP, cap); + cap =3D msr_read(MSR_IA32_MCG_CAP); *banks =3D min_t(unsigned, MAX_NR_BANKS, cap & MCG_BANKCNT_MASK); return !!(cap & MCG_CMCI_P); } @@ -106,7 +106,7 @@ static bool lmce_supported(void) if (mca_cfg.lmce_disabled) return false; =20 - rdmsrq(MSR_IA32_MCG_CAP, tmp); + tmp =3D msr_read(MSR_IA32_MCG_CAP); =20 /* * LMCE depends on recovery support in the processor. Hence both @@ -123,7 +123,7 @@ static bool lmce_supported(void) * WARN if the MSR isn't locked as init_ia32_feat_ctl() unconditionally * locks the MSR in the event that it wasn't already locked by BIOS. */ - rdmsrq(MSR_IA32_FEAT_CTL, tmp); + tmp =3D msr_read(MSR_IA32_FEAT_CTL); if (WARN_ON_ONCE(!(tmp & FEAT_CTL_LOCKED))) return false; =20 @@ -141,9 +141,9 @@ static void cmci_set_threshold(int bank, int thresh) u64 val; =20 raw_spin_lock_irqsave(&cmci_discover_lock, flags); - rdmsrq(MSR_IA32_MCx_CTL2(bank), val); + val =3D msr_read(MSR_IA32_MCx_CTL2(bank)); val &=3D ~MCI_CTL2_CMCI_THRESHOLD_MASK; - wrmsrq(MSR_IA32_MCx_CTL2(bank), val | thresh); + msr_write_ser(MSR_IA32_MCx_CTL2(bank), val | thresh); raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); } =20 @@ -184,7 +184,7 @@ static bool cmci_skip_bank(int bank, u64 *val) if (test_bit(bank, mce_banks_ce_disabled)) return true; =20 - rdmsrq(MSR_IA32_MCx_CTL2(bank), *val); + *val =3D msr_read(MSR_IA32_MCx_CTL2(bank)); =20 /* Already owned by someone else? */ if (*val & MCI_CTL2_CMCI_EN) { @@ -232,8 +232,8 @@ static void cmci_claim_bank(int bank, u64 val, int bios= _zero_thresh, int *bios_w struct mca_storm_desc *storm =3D this_cpu_ptr(&storm_desc); =20 val |=3D MCI_CTL2_CMCI_EN; - wrmsrq(MSR_IA32_MCx_CTL2(bank), val); - rdmsrq(MSR_IA32_MCx_CTL2(bank), val); + msr_write_ser(MSR_IA32_MCx_CTL2(bank), val); + val =3D msr_read(MSR_IA32_MCx_CTL2(bank)); =20 /* If the enable bit did not stick, this bank should be polled. */ if (!(val & MCI_CTL2_CMCI_EN)) { @@ -324,9 +324,9 @@ static void __cmci_disable_bank(int bank) =20 if (!test_bit(bank, this_cpu_ptr(mce_banks_owned))) return; - rdmsrq(MSR_IA32_MCx_CTL2(bank), val); + val =3D msr_read(MSR_IA32_MCx_CTL2(bank)); val &=3D ~MCI_CTL2_CMCI_EN; - wrmsrq(MSR_IA32_MCx_CTL2(bank), val); + msr_write_ser(MSR_IA32_MCx_CTL2(bank), val); __clear_bit(bank, this_cpu_ptr(mce_banks_owned)); =20 if ((val & MCI_CTL2_CMCI_THRESHOLD_MASK) =3D=3D CMCI_STORM_THRESHOLD) @@ -430,10 +430,10 @@ void intel_init_lmce(void) if (!lmce_supported()) return; =20 - rdmsrq(MSR_IA32_MCG_EXT_CTL, val); + val =3D msr_read(MSR_IA32_MCG_EXT_CTL); =20 if (!(val & MCG_EXT_CTL_LMCE_EN)) - wrmsrq(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); + msr_write_ser(MSR_IA32_MCG_EXT_CTL, val | MCG_EXT_CTL_LMCE_EN); } =20 void intel_clear_lmce(void) @@ -443,9 +443,9 @@ void intel_clear_lmce(void) if (!lmce_supported()) return; =20 - rdmsrq(MSR_IA32_MCG_EXT_CTL, val); + val =3D msr_read(MSR_IA32_MCG_EXT_CTL); val &=3D ~MCG_EXT_CTL_LMCE_EN; - wrmsrq(MSR_IA32_MCG_EXT_CTL, val); + msr_write_ser(MSR_IA32_MCG_EXT_CTL, val); } =20 /* @@ -460,10 +460,10 @@ static void intel_imc_init(struct cpuinfo_x86 *c) case INTEL_SANDYBRIDGE_X: case INTEL_IVYBRIDGE_X: case INTEL_HASWELL_X: - if (rdmsrq_safe(MSR_ERROR_CONTROL, &error_control)) + if (msr_read_safe(MSR_ERROR_CONTROL, &error_control)) return; error_control |=3D 2; - wrmsrq_safe(MSR_ERROR_CONTROL, error_control); + msr_write_safe_ser(MSR_ERROR_CONTROL, error_control); break; } } diff --git a/arch/x86/kernel/cpu/mce/p5.c b/arch/x86/kernel/cpu/mce/p5.c index 2272ad53fc33..973b98a90649 100644 --- a/arch/x86/kernel/cpu/mce/p5.c +++ b/arch/x86/kernel/cpu/mce/p5.c @@ -23,16 +23,16 @@ int mce_p5_enabled __read_mostly; /* Machine check handler for Pentium class Intel CPUs: */ noinstr void pentium_machine_check(struct pt_regs *regs) { - u32 loaddr, hi, lotype; + struct msr addr, type; =20 instrumentation_begin(); - rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); - rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); + addr.q =3D msr_read(MSR_IA32_P5_MC_ADDR); + type.q =3D msr_read(MSR_IA32_P5_MC_TYPE); =20 pr_emerg("CPU#%d: Machine Check Exception: 0x%8X (type 0x%8X).\n", - smp_processor_id(), loaddr, lotype); + smp_processor_id(), addr.l, type.l); =20 - if (lotype & (1<<5)) { + if (type.l & (1<<5)) { pr_emerg("CPU#%d: Possible thermal failure (CPU on fire ?).\n", smp_processor_id()); } @@ -44,7 +44,7 @@ noinstr void pentium_machine_check(struct pt_regs *regs) /* Set up machine check reporting for processors with Intel style MCE: */ void intel_p5_mcheck_init(struct cpuinfo_x86 *c) { - u32 l, h; + u64 val; =20 /* Default P5 to off as its often misconnected: */ if (!mce_p5_enabled) @@ -55,8 +55,8 @@ void intel_p5_mcheck_init(struct cpuinfo_x86 *c) return; =20 /* Read registers before enabling: */ - rdmsr(MSR_IA32_P5_MC_ADDR, l, h); - rdmsr(MSR_IA32_P5_MC_TYPE, l, h); + val =3D msr_read(MSR_IA32_P5_MC_ADDR); + val =3D msr_read(MSR_IA32_P5_MC_TYPE); pr_info("Intel old style machine check architecture supported.\n"); =20 /* Enable MCE: */ diff --git a/arch/x86/kernel/cpu/mce/winchip.c b/arch/x86/kernel/cpu/mce/wi= nchip.c index 6c99f2941909..425927c9dd5e 100644 --- a/arch/x86/kernel/cpu/mce/winchip.c +++ b/arch/x86/kernel/cpu/mce/winchip.c @@ -28,12 +28,12 @@ noinstr void winchip_machine_check(struct pt_regs *regs) /* Set up machine check reporting on the Winchip C6 series */ void winchip_mcheck_init(struct cpuinfo_x86 *c) { - u32 lo, hi; + struct msr val; =20 - rdmsr(MSR_IDT_FCR1, lo, hi); - lo |=3D (1<<2); /* Enable EIERRINT (int 18 MCE) */ - lo &=3D ~(1<<4); /* Enable MCE */ - wrmsr(MSR_IDT_FCR1, lo, hi); + val.q =3D msr_read(MSR_IDT_FCR1); + val.l |=3D (1<<2); /* Enable EIERRINT (int 18 MCE) */ + val.l &=3D ~(1<<4); /* Enable MCE */ + msr_write_ser(MSR_IDT_FCR1, val.q); =20 cr4_set_bits(X86_CR4_MCE); =20 --=20 2.53.0