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It has 16 IPC channels, compared to 3 on X1E80100 CPUCP. Signed-off-by: Deepti Jaggi Signed-off-by: Shawn Guo --- Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml= b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml index 90bfde66cc4a..2dd66a88c186 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -23,6 +23,7 @@ properties: - qcom,sm8750-cpucp-mbox - const: qcom,x1e80100-cpucp-mbox - enum: + - qcom,nord-cpucp-mbox - qcom,x1e80100-cpucp-mbox =20 reg: --=20 2.43.0 From nobody Thu Jun 18 08:27:00 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C29E37FF75 for ; Mon, 20 Apr 2026 03:52:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12c74a20c55sm13056111c88.13.2026.04.19.20.52.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Apr 2026 20:52:15 -0700 (PDT) From: Shawn Guo To: Jassi Brar Cc: Sibi Sankar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Dmitry Baryshkov , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Shawn Guo Subject: [PATCH 2/2] mailbox: qcom-cpucp: Add support for Nord CPUCP mailbox controller Date: Mon, 20 Apr 2026 11:49:32 +0800 Message-ID: <20260420034932.1247344-3-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260420034932.1247344-1-shengchao.guo@oss.qualcomm.com> References: <20260420034932.1247344-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: nS3X_iPy6nc1lgVYxzIhoAYJjRIyOLEB X-Proofpoint-ORIG-GUID: nS3X_iPy6nc1lgVYxzIhoAYJjRIyOLEB X-Authority-Analysis: v=2.4 cv=SNFykuvH c=1 sm=1 tr=0 ts=69e5a2f1 cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=OYxAFmqQ0AEWrUtYbScA:9 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIwMDAzMyBTYWx0ZWRfX8sKOOSRAkYi6 96kB9XdZH82eSSFXWmAz/p6lOa6S84Ze6NpOAgu7ChhgOg4plvUfwJErNcwSNbQqGL1JsFu+nmH D4JSsOxIL0Tca+UyXwCjce+gdo5WzJm0gsHUzUu6UlOLwNnRMqjEXwTaa35M2IG6D+Nuv5Huz1Z SZuG8jHYJXp3Rjm7gFbbk059/E+jD5AI45d/V/AhnlONs0ct2gMbqqbkSLoCdkZDYyHG/EqlyoI QHR4GLv2sXlHa5pxkgBwpvMNlJoFk9yBjB/kCVFeRq4I4YkNSQOrMPBVODhOLCMsQAhb069JV5j eAdQ64AaJkAmEAJsGmsJgf0eUBIIqC3cbEiU4uu+8a8me7NrDn75mIuu77lXP/uU9ERB4wwpcFO lOdjy/2Zu5Hb+B4cyZrCWBKYxkZk/bYLKtwJSk8GwYr6n2TtpN96LroEkNihoUH63CZObsDdC2S SZi/5kIQYyySaS9atUw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-19_07,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 phishscore=0 adultscore=0 malwarescore=0 bulkscore=0 suspectscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604200033 Content-Type: text/plain; charset="utf-8" From: Deepti Jaggi The Nord SoC CPUCP mailbox supports 16 IPC channels, compared to 3 on x1e80100. The existing driver hardcodes the channel count via a compile-time constant (APSS_CPUCP_IPC_CHAN_SUPPORTED), making it impossible to support hardware with a different number of channels. Introduce a qcom_cpucp_mbox_data per-hardware configuration struct that carries the channel count, and retrieve it via of_device_get_match_data() at probe time. Switch the channel array from a fixed-size member to a dynamically allocated buffer sized from the hardware data. Update the x1e80100 entry to supply its own data struct, and add a new Nord entry with num_chans =3D 16. Signed-off-by: Deepti Jaggi Signed-off-by: Shawn Guo --- drivers/mailbox/qcom-cpucp-mbox.c | 37 ++++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp= -mbox.c index 44f4ed15f818..624a4e9eb6c6 100644 --- a/drivers/mailbox/qcom-cpucp-mbox.c +++ b/drivers/mailbox/qcom-cpucp-mbox.c @@ -12,7 +12,6 @@ #include #include =20 -#define APSS_CPUCP_IPC_CHAN_SUPPORTED 3 #define APSS_CPUCP_MBOX_CMD_OFF 0x4 =20 /* Tx Registers */ @@ -26,15 +25,23 @@ #define APSS_CPUCP_RX_MBOX_EN 0x4c00 #define APSS_CPUCP_RX_MBOX_CMD_MASK GENMASK_ULL(63, 0) =20 +/** + * struct qcom_cpucp_mbox_data - Per-hardware mailbox configuration data + * @num_chans: Number of IPC channels supported by this hardware + */ +struct qcom_cpucp_mbox_data { + int num_chans; +}; + /** * struct qcom_cpucp_mbox - Holder for the mailbox driver - * @chans: The mailbox channel + * @chans: The mailbox channels (dynamically allocated) * @mbox: The mailbox controller * @tx_base: Base address of the CPUCP tx registers * @rx_base: Base address of the CPUCP rx registers */ struct qcom_cpucp_mbox { - struct mbox_chan chans[APSS_CPUCP_IPC_CHAN_SUPPORTED]; + struct mbox_chan *chans; struct mbox_controller mbox; void __iomem *tx_base; void __iomem *rx_base; @@ -53,7 +60,7 @@ static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *= data) =20 status =3D readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); =20 - for_each_set_bit(i, (unsigned long *)&status, APSS_CPUCP_IPC_CHAN_SUPPORT= ED) { + for_each_set_bit(i, (unsigned long *)&status, cpucp->mbox.num_chans) { u32 val =3D readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUC= P_MBOX_CMD_OFF); struct mbox_chan *chan =3D &cpucp->chans[i]; unsigned long flags; @@ -112,15 +119,24 @@ static const struct mbox_chan_ops qcom_cpucp_mbox_cha= n_ops =3D { =20 static int qcom_cpucp_mbox_probe(struct platform_device *pdev) { + const struct qcom_cpucp_mbox_data *data; struct device *dev =3D &pdev->dev; struct qcom_cpucp_mbox *cpucp; struct mbox_controller *mbox; int irq, ret; =20 + data =3D of_device_get_match_data(dev); + if (!data) + return dev_err_probe(dev, -EINVAL, "No match data found\n"); + cpucp =3D devm_kzalloc(dev, sizeof(*cpucp), GFP_KERNEL); if (!cpucp) return -ENOMEM; =20 + cpucp->chans =3D devm_kcalloc(dev, data->num_chans, sizeof(*cpucp->chans)= , GFP_KERNEL); + if (!cpucp->chans) + return -ENOMEM; + cpucp->rx_base =3D devm_of_iomap(dev, dev->of_node, 0, NULL); if (IS_ERR(cpucp->rx_base)) return PTR_ERR(cpucp->rx_base); @@ -146,7 +162,7 @@ static int qcom_cpucp_mbox_probe(struct platform_device= *pdev) =20 mbox =3D &cpucp->mbox; mbox->dev =3D dev; - mbox->num_chans =3D APSS_CPUCP_IPC_CHAN_SUPPORTED; + mbox->num_chans =3D data->num_chans; mbox->chans =3D cpucp->chans; mbox->ops =3D &qcom_cpucp_mbox_chan_ops; =20 @@ -157,8 +173,17 @@ static int qcom_cpucp_mbox_probe(struct platform_devic= e *pdev) return 0; } =20 +static const struct qcom_cpucp_mbox_data qcom_x1e80100_mbox_data =3D { + .num_chans =3D 3, +}; + +static const struct qcom_cpucp_mbox_data qcom_nord_mbox_data =3D { + .num_chans =3D 16, +}; + static const struct of_device_id qcom_cpucp_mbox_of_match[] =3D { - { .compatible =3D "qcom,x1e80100-cpucp-mbox" }, + { .compatible =3D "qcom,nord-cpucp-mbox", .data =3D &qcom_nord_mbox_data = }, + { .compatible =3D "qcom,x1e80100-cpucp-mbox", .data =3D &qcom_x1e80100_mb= ox_data }, {} }; MODULE_DEVICE_TABLE(of, qcom_cpucp_mbox_of_match); --=20 2.43.0