From nobody Tue Jun 16 12:41:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44FC937EFEE; Mon, 20 Apr 2026 02:50:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776653413; cv=none; b=DwAaRvlX6O1hUdEpGDvpP9/dc1Z3YhxbJ7bhTVnjAqUMnemxPSrwAdf7bIvyHUgh8kmoZAedaPsNjDA9u7CTrLDReXCID4muYINj76x5ZDZxG0Yov4aRI/tm2+VF/GPBzvtvXeV4T5U3vlNI1BXOcZCc1kMBZH9+Cn1C5XYaaUc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776653413; c=relaxed/simple; bh=Qkh5yZr3vefHZXHn+qNZLM8IegPI8fk/2+sfH3oU/uo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WBMKhTb8URBrE8/0LwNhVkC2dj0bCIRxVIbfx0cSBO5htgSzS70MZFIzYihcE0RxPuNvawZn4A3Errbgj5jeTxZnB0PQr8ppDX4jPzdTPdfSUikauGQ4GjRnYSk31MTzFjV505r+KPpDY1dD93pFS+20DBufRDBXoamtF01AjLU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=AFrs9ygn; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="AFrs9ygn" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776653413; x=1808189413; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Qkh5yZr3vefHZXHn+qNZLM8IegPI8fk/2+sfH3oU/uo=; b=AFrs9ygnHcNjonH4Rh8bGOejEYUyDuxUSs9nHSYGA1qN7tCPMLuxeGWD 52p55w7fXpjg4/wMQaKrWxChUbb59pPBc8G4Ntbjjaus00IkOW3ZmhLi+ Ng08dJ3YvhhXJNmV8Qb/pl9uG6bu5M9YoucOCk1WRhkC8zIz5GboPc49q OL1C+WCnLSTpO4u9QrpRVvXuKnZsy2gdflj27RWvLMXnfH3SHUgu+to8I emhHcYu2yZX/SjkiwtfMGe9Gpq+iEfv/Dwqf0XRo+CogqRZNfHRhV+zHo +JiJHejK7ZkTHyGS6OY/Pwh0F5RGMpeXu+/pvUumpGm7OPrd600TC3eUa g==; X-CSE-ConnectionGUID: nYQa5f5VTGuK91+bDVP1tA== X-CSE-MsgGUID: 8Lhl3ABfRyO5zDXbppZQBQ== X-IronPort-AV: E=McAfee;i="6800,10657,11762"; a="81442156" X-IronPort-AV: E=Sophos;i="6.23,189,1770624000"; d="scan'208";a="81442156" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2026 19:50:12 -0700 X-CSE-ConnectionGUID: c0aCffKXQUGhrTfroEsWBA== X-CSE-MsgGUID: 31K6dTS8Tom1MiZriN7NOQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,189,1770624000"; d="scan'208";a="228908001" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa008.fm.intel.com with ESMTP; 19 Apr 2026 19:50:08 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi , stable@vger.kernel.org Subject: [Patch v2 1/4] perf/x86/intel: Clear stale ACR mask before updating new mask Date: Mon, 20 Apr 2026 10:45:25 +0800 Message-Id: <20260420024528.2130065-2-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420024528.2130065-1-dapeng1.mi@linux.intel.com> References: <20260420024528.2130065-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current implementation forgets to clear the ACR mask before applying a new one. During event rescheduling, this allow bits from a previous stale ACR mask to persist, leading to an incorrect hardware state. Ensure that the ACR mask is zeroed out before setting the new mask to prevent state pollution. Cc: stable@vger.kernel.org Fixes: ec980e4facef ("perf/x86/intel: Support auto counter reload") Signed-off-by: Dapeng Mi --- V2: Clear stale acr_mask for all events. arch/x86/events/intel/core.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 4768236c054b..774ae9a4eeaf 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3334,6 +3334,12 @@ static void intel_pmu_acr_late_setup(struct cpu_hw_e= vents *cpuc) struct perf_event *event, *leader; int i, j, idx; =20 + /* Clear stale ACR mask first. */ + for (i =3D 0; i < cpuc->n_events; i++) { + event =3D cpuc->event_list[i]; + event->hw.config1 =3D 0; + } + for (i =3D 0; i < cpuc->n_events; i++) { leader =3D cpuc->event_list[i]; if (!is_acr_event_group(leader)) --=20 2.34.1 From nobody Tue Jun 16 12:41:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 019BA33C532; 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arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="XRFftsbm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776653416; x=1808189416; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b/5DCeyOn3HCo+CywoQtIGpp6WPDQ+hggIO7xPY2XAM=; b=XRFftsbmGKQOSFwwILwRH8PLfe6BCMmBziSGSK6ssa3zIS1ehqYlrxwL 6NbcKFIfWkPhpuk+waLipM/Mhl5aH7odsegFOHr0orUO4UKZ8b4xDt/9q CwMviicBuBEcDMbgom4jkglLLKzC4fSahWx2D83XPpsK8F0WbEhhU3rwW JciAfHpMU6ZlDUImboivRXGpqa0Ms/vsIBCq3QpWIgWgFJF4s6g3r4H2W YmST6VOCiPopnXworj8kdce2W3eEIRsypsDdXcVQYRpaTLM1ehAstkzVz nlM4bO7NHWv//HmZ6XjUSukI4g8CTaP+m+Rf2HVYo+wibUALxGF4dqxyT Q==; X-CSE-ConnectionGUID: qM19FzMVQA+z7Drpg1yMZw== X-CSE-MsgGUID: ZqH2PVjOTxWI3cMV04U2Jg== X-IronPort-AV: E=McAfee;i="6800,10657,11762"; a="81442168" X-IronPort-AV: E=Sophos;i="6.23,189,1770624000"; d="scan'208";a="81442168" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2026 19:50:16 -0700 X-CSE-ConnectionGUID: 97rGiKMDQH+4EIRXPxZ5sA== X-CSE-MsgGUID: pfuor1LkQkW3Sjab8DB8+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,189,1770624000"; d="scan'208";a="228908011" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa008.fm.intel.com with ESMTP; 19 Apr 2026 19:50:12 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi , stable@vger.kernel.org Subject: [Patch v2 2/4] perf/x86/intel: Disable PMI for self-reloaded ACR events Date: Mon, 20 Apr 2026 10:45:26 +0800 Message-Id: <20260420024528.2130065-3-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420024528.2130065-1-dapeng1.mi@linux.intel.com> References: <20260420024528.2130065-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On platforms with Auto Counter Reload (ACR) support, such as NVL, a "NMI received for unknown reason 30" warning is observed when running multiple events in a group with ACR enabled: $ perf record -e '{instructions/period=3D20000,acr_mask=3D0x2/u,\ cycles/period=3D40000,acr_mask=3D0x3/u}' ./test The warning occurs because the Performance Monitoring Interrupt (PMI) is enabled for the self-reloaded event (the cycles event in this case). According to the Intel SDM, the overflow bit (IA32_PERF_GLOBAL_STATUS.PMCn_OVF) is never set for self-reloaded events. Since the bit is not set, the perf NMI handler cannot identify the source of the interrupt, leading to the "unknown reason" message. Furthermore, enabling PMI for self-reloaded events is unnecessary and can lead to extraneous records that pollute the user's requested data. Disable the interrupt bit for all events configured with ACR self-reload. Reported-by: Andi Kleen Cc: stable@vger.kernel.org Fixes: ec980e4facef ("perf/x86/intel: Support auto counter reload") Signed-off-by: Dapeng Mi --- arch/x86/events/intel/core.c | 17 +++++++++++++---- arch/x86/events/perf_event.h | 10 ++++++++++ 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 774ae9a4eeaf..510b087c9e89 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3118,11 +3118,11 @@ static void intel_pmu_enable_fixed(struct perf_even= t *event) intel_set_masks(event, idx); =20 /* - * Enable IRQ generation (0x8), if not PEBS, - * and enable ring-3 counting (0x2) and ring-0 counting (0x1) - * if requested: + * Enable IRQ generation (0x8), if not PEBS and self-reloaded + * ACR event, and enable ring-3 counting (0x2) and ring-0 + * counting (0x1) if requested: */ - if (!event->attr.precise_ip) + if (!event->attr.precise_ip && !is_acr_self_reload_event(event)) bits |=3D INTEL_FIXED_0_ENABLE_PMI; if (hwc->config & ARCH_PERFMON_EVENTSEL_USR) bits |=3D INTEL_FIXED_0_USER; @@ -3306,6 +3306,15 @@ static void intel_pmu_enable_event(struct perf_event= *event) intel_set_masks(event, idx); static_call_cond(intel_pmu_enable_acr_event)(event); static_call_cond(intel_pmu_enable_event_ext)(event); + /* + * For self-reloaded ACR event, don't enable PMI since + * HW won't set overflow bit in GLOBAL_STATUS. Otherwise, + * the PMI would be recognized as a suspicious NMI. + */ + if (is_acr_self_reload_event(event)) + hwc->config &=3D ~ARCH_PERFMON_EVENTSEL_INT; + else if (!event->attr.precise_ip) + hwc->config |=3D ARCH_PERFMON_EVENTSEL_INT; __x86_pmu_enable_event(hwc, enable_mask); break; case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index fad87d3c8b2c..524668dcf4cc 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -137,6 +137,16 @@ static inline bool is_acr_event_group(struct perf_even= t *event) return check_leader_group(event->group_leader, PERF_X86_EVENT_ACR); } =20 +static inline bool is_acr_self_reload_event(struct perf_event *event) +{ + struct hw_perf_event *hwc =3D &event->hw; + + if (hwc->idx < 0) + return false; + + return test_bit(hwc->idx, (unsigned long *)&hwc->config1); +} + struct amd_nb { int nb_id; /* NorthBridge id */ int refcnt; /* reference count */ --=20 2.34.1 From nobody Tue Jun 16 12:41:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93A7637EFE2; Mon, 20 Apr 2026 02:50:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776653420; cv=none; b=N0O31znXcon4PTvnnKj/3ijlMqbZs/ftgyefgEaFltx9bH8pY9witvnUrMKI07ra0BE/CkrI/da+qYRyXQ+ZByDd4tGy3kopJBD0JpfOdw3IBuKv6T9E1UET63Nb719cR0Y9z/3MbkXiiMa4v4p3OxlRKuQcp4PYzlqY3WrOtXc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776653420; c=relaxed/simple; bh=kMqwokR32BTLt39tHBsnECxD5tRPyKYHB08MUi1kLvM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=Q/e/WiZ+V08A/AV5syCMhA9sw0T1qxCz34TjUvTTg8QI/K6Lp/5baON8lW4ZuC0bYXMHT13Ahs4puqKeEPqq2+035qUDRXcPyKGyDoZ7gJ9WF/ixHcyWnvs92TLzkyk9dl+sp8Vn8dbtwcqTFW+xeTFfmrPTGNG3uC5Si0tGM+s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gzkOmSXs; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gzkOmSXs" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776653420; x=1808189420; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kMqwokR32BTLt39tHBsnECxD5tRPyKYHB08MUi1kLvM=; b=gzkOmSXs+RpnyeBr3d6/Neu0UabpK+CFnEaSiys4KJ0VNRYtdOcrUIyV ksgvFwDvnAsmwisnc7wLuFdWz0Qv1DQll+xb+HFLbYhG0RAHzprhytpoB ZL5wJ0z1MdK/JBC6g9IRc23Ejm6pbRfdg6CCGEvRG0ffRmdZGl4pGjKAc rDFBEfvlZTll6cehBxchsVBlBdBFnBrOrmQe711itdBx8qkpMzDSW8Ia3 b4v58AjLi2uG1MF8K8VNUHpVNkceycNb1EHeirfJ6D/+4CrsaU7mN/Sip F/F/eWMdJOjhYV3aBIiwbtJpqOwQr07QPlp/PwQ/bfbQWIunCzX2kHOGu A==; X-CSE-ConnectionGUID: i/5GbbflTbmnQEwfA3FWsQ== X-CSE-MsgGUID: t7ODjzkGRdaIV1EYFbQ27g== X-IronPort-AV: E=McAfee;i="6800,10657,11762"; a="81442179" X-IronPort-AV: E=Sophos;i="6.23,189,1770624000"; d="scan'208";a="81442179" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2026 19:50:20 -0700 X-CSE-ConnectionGUID: OnPnkz01RcWWFnFx7baGsw== X-CSE-MsgGUID: hdxUWPRUQnCSy0MxCu1Zmw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,189,1770624000"; d="scan'208";a="228908019" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa008.fm.intel.com with ESMTP; 19 Apr 2026 19:50:16 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi , stable@vger.kernel.org Subject: [Patch v2 3/4] perf/x86/intel: Enable auto counter reload for DMR Date: Mon, 20 Apr 2026 10:45:27 +0800 Message-Id: <20260420024528.2130065-4-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420024528.2130065-1-dapeng1.mi@linux.intel.com> References: <20260420024528.2130065-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Panther cove =C2=B5arch starts to support auto counter reload (ACR), but the static_call intel_pmu_enable_acr_event() is not updated for the Panther Cove =C2=B5arch used by DMR. It leads to the auto counter reload is not really enabled on DMR. Update static_call intel_pmu_enable_acr_event() in intel_pmu_init_pnc(). Cc: stable@vger.kernel.org Fixes: d345b6bb8860 ("perf/x86/intel: Add core PMU support for DMR") Signed-off-by: Dapeng Mi --- V2: New patch. arch/x86/events/intel/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 510b087c9e89..fa4073bf18fe 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -7506,6 +7506,7 @@ static __always_inline void intel_pmu_init_pnc(struct= pmu *pmu) hybrid(pmu, event_constraints) =3D intel_pnc_event_constraints; hybrid(pmu, pebs_constraints) =3D intel_pnc_pebs_event_constraints; hybrid(pmu, extra_regs) =3D intel_pnc_extra_regs; + static_call_update(intel_pmu_enable_acr_event, intel_pmu_enable_acr); } =20 static __always_inline void intel_pmu_init_skt(struct pmu *pmu) --=20 2.34.1 From nobody Tue Jun 16 12:41:12 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 130F437EFE0; Mon, 20 Apr 2026 02:50:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776653424; cv=none; b=FsZACBIk9MtHlowhVXSMAciUWxizN4Roikw5BmKcdZkfWF3ziCKO6IPkCjJloZnsQObVkp0USObNHWXLVXgCSmZvoQkUVGnMKx0Zo6eyDCb8B+rddMaxI8O77NzQYT34pu0EgCOuXAP+P9xaxdlWLag8LlJL5Kddl8D2K4NLYyg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776653424; c=relaxed/simple; bh=2bf08aeEUxhfg1cK5fNzAhUOWDp4cmQTN0IHH56OVw8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qT8IdscHxexzvW06NqcOnmjOGFBRbRWVoxNYS2ne1vafS8qcT8/noZlLlFERjm70KwHRELThJQe/9D3v16e3gJ22NijsfounXohnjZhnO3xLpozON2wACUmb03zjuuvC/A93URaWT3vpiXY/dK/FCv+hShy1U3W7OWcEdzt6TXU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=QH+B+ZZr; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="QH+B+ZZr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776653423; x=1808189423; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2bf08aeEUxhfg1cK5fNzAhUOWDp4cmQTN0IHH56OVw8=; b=QH+B+ZZrEYKzQHdzpHZGQs+2ma/V87R8o5hqst0agShKhFvqr3F/2pyg FZQApdlndtR02lQN/P8dwZhSE+r8+yVbr6Wzp90zMwU+d1eqh4H+4/7MN UjMgF9J30BdDXL74TsHIjlGLWQkRgG4uDqr4Pd5Cv3USmzP6i+M7melyr T4z0gqq/IjE32YsW8ZJfxgS0JGcr3xs5ZA47U4M41vvmzAzVzJQEc7++Y Y6BaPFTJly5E2qUHDG8LaCndwtRlYmvImB6yGM3ida2Q9EjIC+/C7PLqz OVv3HH4haFAbp2cYI5DNxE1ZvJayWeTqmTSuK1H17AVLa238E9dOwQxy9 Q==; X-CSE-ConnectionGUID: kIWtPM84QMqhWJar5y5zOg== X-CSE-MsgGUID: e3ykd4R5S8y0ZdS05r4Bpw== X-IronPort-AV: E=McAfee;i="6800,10657,11762"; a="81442190" X-IronPort-AV: E=Sophos;i="6.23,189,1770624000"; d="scan'208";a="81442190" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Apr 2026 19:50:23 -0700 X-CSE-ConnectionGUID: MIp3dRJbQnutHoXTOTISLA== X-CSE-MsgGUID: eJxJ5q7/S5a9VO6J4j55uw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,189,1770624000"; d="scan'208";a="228908022" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa008.fm.intel.com with ESMTP; 19 Apr 2026 19:50:19 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Zide Chen , Falcon Thomas , Xudong Hao , Dapeng Mi Subject: [Patch v2 4/4] perf/x86/intel: Consolidate MSR_IA32_PERF_CFG_C tracking Date: Mon, 20 Apr 2026 10:45:28 +0800 Message-Id: <20260420024528.2130065-5-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260420024528.2130065-1-dapeng1.mi@linux.intel.com> References: <20260420024528.2130065-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Both Auto Counter Reload (ACR) and Architectural PEBS use the PERF_CFG_C MSRs to configure event behavior. Currently, the driver maintains two independent variables acr_cfg_c and cfg_c_val to cache the values intended for these MSRs. Using separate variables to track a single hardware register state is error-prone and can lead to configuration conflicts. Consolidate the tracking into a single cfg_c_val variable to ensure a unified and consistent view of the PERF_CFG_C MSR state. Signed-off-by: Dapeng Mi --- V2: New patch. arch/x86/events/intel/core.c | 13 +++++++------ arch/x86/events/perf_event.h | 4 +--- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index fa4073bf18fe..667917baf7f2 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3169,10 +3169,10 @@ static void intel_pmu_config_acr(int idx, u64 mask,= u32 reload) wrmsrl(msr_b + msr_offset, mask); cpuc->acr_cfg_b[idx] =3D mask; } - /* Only need to update the reload value when there is a valid config valu= e. */ - if (mask && cpuc->acr_cfg_c[idx] !=3D reload) { + /* Only update CFG_C reload when ACR is actively enabled (mask !=3D 0) */ + if (mask && ((cpuc->cfg_c_val[idx] & ARCH_PEBS_RELOAD) !=3D reload)) { wrmsrl(msr_c + msr_offset, reload); - cpuc->acr_cfg_c[idx] =3D reload; + cpuc->cfg_c_val[idx] =3D reload; } } =20 @@ -3198,14 +3198,15 @@ static void intel_pmu_enable_event_ext(struct perf_= event *event) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); struct hw_perf_event *hwc =3D &event->hw; - union arch_pebs_index old, new; - struct arch_pebs_cap cap; u64 ext =3D 0; =20 - cap =3D hybrid(cpuc->pmu, arch_pebs_cap); + if (is_acr_event_group(event)) + ext |=3D (-hwc->sample_period) & ARCH_PEBS_RELOAD; =20 if (event->attr.precise_ip) { u64 pebs_data_cfg =3D intel_get_arch_pebs_data_config(event); + struct arch_pebs_cap cap =3D hybrid(cpuc->pmu, arch_pebs_cap); + union arch_pebs_index old, new; =20 ext |=3D ARCH_PEBS_EN; if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 524668dcf4cc..40d6fe0afc4a 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -322,10 +322,8 @@ struct cpu_hw_events { u64 fixed_ctrl_val; u64 active_fixed_ctrl_val; =20 - /* Intel ACR configuration */ + /* Intel ACR/arch-PEBS configuration */ u64 acr_cfg_b[X86_PMC_IDX_MAX]; - u64 acr_cfg_c[X86_PMC_IDX_MAX]; - /* Cached CFG_C values */ u64 cfg_c_val[X86_PMC_IDX_MAX]; =20 /* --=20 2.34.1