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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2e53ab8b89csm12556600eec.12.2026.04.19.19.14.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Apr 2026 19:14:26 -0700 (PDT) From: Shawn Guo To: Georgi Djakov Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Odelu Kukatla , Konrad Dybcio , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 1/2] dt-bindings: interconnect: Document RPMh Network-On-Chip for Qualcomm Nord SoC Date: Mon, 20 Apr 2026 10:13:50 +0800 Message-ID: <20260420021351.1239355-2-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260420021351.1239355-1-shengchao.guo@oss.qualcomm.com> References: <20260420021351.1239355-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=HbokiCE8 c=1 sm=1 tr=0 ts=69e58c03 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=3U7udxK0YKKcqa3c1UMA:9 a=PxkB5W3o20Ba91AHUih5:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-GUID: RgHnEoUigUc5cZIDeSU2Z5r7DWSHFSbq X-Proofpoint-ORIG-GUID: RgHnEoUigUc5cZIDeSU2Z5r7DWSHFSbq X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIwMDAxOSBTYWx0ZWRfX3elLEQatsLac U/o3T2MC+M0AlFb6JRqJPRZps6FYtADC7P5E/b1hIk/90y6Hm7LaR6T219FNT6fl1RMcA7E2QoP NDYH1SXo0PQT0dNIUjoCcpr7QalpTW4VjvsxDxppy7Znku/krGM3DsmtQ5wNNB86GPW/B1pwMkt dNCNp8gwSeNHFYABM1onNw6KhygkwoSyMDtpMEBpxGUKZ3KbCldyFcRxch+3Tq6fZxMHzWXOv3s BYRH0lCAkHHayLBJlH+mYNU63ha2Y752Lcr+Q8JYSKea5JV1zZYzrhURzFfctlEAgCz7j0JNNAD vDX5aRtU50MySDkN0LDAj8dVSUBhF01yqL9lht/dBZKowJLTcA8gKSuyNWu6C4WoZUqync07/rT b0jDvSNKVrHL6T3oGjIt7DE2uVAIVl1UCMurDZ2f1ukthdtgAggVL+v2qleN1F4MrRKPs6q2Flc T6waCR6qiRxTNxYtuHA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-19_07,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 bulkscore=0 spamscore=0 clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 suspectscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604200019 Content-Type: text/plain; charset="utf-8" From: Odelu Kukatla Add RPMh Network-On-Chip interconnect bindings for Qualcomm Nord SoC. Signed-off-by: Odelu Kukatla Signed-off-by: Shawn Guo Reviewed-by: Krzysztof Kozlowski --- .../bindings/interconnect/qcom,nord-rpmh.yaml | 131 +++++++++++ .../dt-bindings/interconnect/qcom,nord-rpmh.h | 217 ++++++++++++++++++ 2 files changed, 348 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,nor= d-rpmh.yaml create mode 100644 include/dt-bindings/interconnect/qcom,nord-rpmh.h diff --git a/Documentation/devicetree/bindings/interconnect/qcom,nord-rpmh.= yaml b/Documentation/devicetree/bindings/interconnect/qcom,nord-rpmh.yaml new file mode 100644 index 000000000000..3650d3d5b918 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,nord-rpmh.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,nord-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Nord + +maintainers: + - Odelu Kukatla + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provide= r is + able to communicate with the BCM through the Resource State Coordinator = (RSC) + associated with each execution environment. Provider nodes must point to= at + least one RPMh device child node pertaining to their RSC and each provid= er + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,nord-rpmh.h + +properties: + compatible: + enum: + - qcom,nord-aggre1-noc + - qcom,nord-aggre1-noc-tile + - qcom,nord-aggre2-noc + - qcom,nord-aggre2-noc-tile + - qcom,nord-clk-virt + - qcom,nord-cnoc-cfg + - qcom,nord-cnoc-main + - qcom,nord-hpass-ag-noc + - qcom,nord-hscnoc + - qcom,nord-mc-virt + - qcom,nord-mmss-noc + - qcom,nord-nsp-data-noc-0 + - qcom,nord-nsp-data-noc-1 + - qcom,nord-nsp-data-noc-2 + - qcom,nord-nsp-data-noc-3 + - qcom,nord-pcie-cfg + - qcom,nord-pcie-data-inbound + - qcom,nord-pcie-data-outbound + - qcom,nord-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-clk-virt + - qcom,nord-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-aggre1-noc-tile + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB2 AXI clock + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-aggre1-noc-tile + - qcom,nord-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + clk_virt: interconnect-clk-virt { + compatible =3D "qcom,nord-clk-virt"; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + }; + + aggre1_noc_tile: interconnect@1720000 { + compatible =3D "qcom,nord-aggre1-noc-tile"; + reg =3D <0x01720000 0x23400>; + #interconnect-cells =3D <2>; + qcom,bcm-voters =3D <&apps_bcm_voter>; + clocks =3D <&ne_gcc_aggre_noc_ufs_phy_axi_clk>, + <&ne_gcc_aggre_noc_usb2_axi_clk>, + <&ne_gcc_aggre_noc_usb3_prim_axi_clk>, + <&ne_gcc_aggre_noc_usb3_sec_axi_clk>; + }; diff --git a/include/dt-bindings/interconnect/qcom,nord-rpmh.h b/include/dt= -bindings/interconnect/qcom,nord-rpmh.h new file mode 100644 index 000000000000..5bdce6a9bab7 --- /dev/null +++ b/include/dt-bindings/interconnect/qcom,nord-rpmh.h @@ -0,0 +1,217 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_NORD_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_NORD_H + +#define MASTER_QSPI_0 0 +#define MASTER_SAILSS_MD1 1 +#define MASTER_QUP_3 2 +#define SLAVE_A1NOC_SNOC 3 + +#define MASTER_QUP_2 0 +#define MASTER_CRYPTO_CORE0 1 +#define MASTER_CRYPTO_CORE1 2 +#define MASTER_CRYPTO_CORE2 3 +#define MASTER_SDCC_4 4 +#define MASTER_UFS_MEM 5 +#define MASTER_USB2 6 +#define MASTER_USB3_0 7 +#define MASTER_USB3_1 8 +#define SLAVE_A1NOC_HSCNOC 9 + +#define MASTER_IPA 0 +#define MASTER_SOCCP_AGGR_NOC 1 +#define MASTER_QDSS_ETR 2 +#define MASTER_QDSS_ETR_1 3 +#define SLAVE_A2NOC_SNOC 4 + +#define MASTER_QUP_0 0 +#define MASTER_QUP_1 1 +#define MASTER_EMAC_0 2 +#define MASTER_EMAC_1 3 +#define SLAVE_A2NOC_HSCNOC 4 + +#define MASTER_QUP_CORE_0 0 +#define MASTER_QUP_CORE_1 1 +#define MASTER_QUP_CORE_2 2 +#define MASTER_QUP_CORE_3 3 +#define SLAVE_QUP_CORE_0 4 +#define SLAVE_QUP_CORE_1 5 +#define SLAVE_QUP_CORE_2 6 +#define SLAVE_QUP_CORE_3 7 + +#define MASTER_CNOC_CFG 0 +#define SLAVE_PS_ETH_0 1 +#define SLAVE_PS_ETH_1 2 +#define SLAVE_SHS_SERVER 3 +#define SLAVE_AHB2PHY_0 4 +#define SLAVE_AHB2PHY_1 5 +#define SLAVE_AHB2PHY_2 6 +#define SLAVE_AHB2PHY_3 7 +#define SLAVE_AHB2PHY_ETH_0 8 +#define SLAVE_AHB2PHY_ETH_1 9 +#define SLAVE_CAMERA_CFG 10 +#define SLAVE_CLK_CTL 11 +#define SLAVE_CRYPTO_0_CFG 12 +#define SLAVE_CRYPTO_1_CFG 13 +#define SLAVE_CRYPTO_2_CFG 14 +#define SLAVE_DISPLAY_1_CFG 15 +#define SLAVE_DISPLAY_CFG 16 +#define SLAVE_DPRX0 17 +#define SLAVE_DPRX1 18 +#define SLAVE_EVA_CFG 19 +#define SLAVE_GFX3D_CFG 20 +#define SLAVE_GFX3D_1_CFG 21 +#define SLAVE_I2C 22 +#define SLAVE_IMEM_CFG 23 +#define SLAVE_MCW_PCIE 24 +#define SLAVE_MM_RSCC 25 +#define SLAVE_NE_CLK_CTL 26 +#define SLAVE_NSPSS0_CFG 27 +#define SLAVE_NSPSS1_CFG 28 +#define SLAVE_NSPSS2_CFG 29 +#define SLAVE_NSPSS3_CFG 30 +#define SLAVE_NW_CLK_CTL 31 +#define SLAVE_PRNG 32 +#define SLAVE_QDSS_CFG 33 +#define SLAVE_QSPI_0 34 +#define SLAVE_QUP_0 35 +#define SLAVE_QUP_3 36 +#define SLAVE_QUP_1 37 +#define SLAVE_QUP_2 38 +#define SLAVE_SAFEDMA_CFG 39 +#define SLAVE_SDCC_4 40 +#define SLAVE_SE_CLK_CTL 41 +#define SLAVE_TCSR 42 +#define SLAVE_TLMM 43 +#define SLAVE_TSC_CFG 44 +#define SLAVE_UFS_MEM_CFG 45 +#define SLAVE_USB2 46 +#define SLAVE_USB3_0 47 +#define SLAVE_USB3_1 48 +#define SLAVE_VENUS_CFG 49 +#define SLAVE_COMPUTENOC_CFG 50 +#define SLAVE_PCIE_NOC_CFG 51 +#define SLAVE_QTC_CFG 52 +#define SLAVE_QDSS_STM 53 +#define SLAVE_SYS_TCU0_CFG 54 +#define SLAVE_SYS_TCU1_CFG 55 +#define SLAVE_SYS_TCU2_CFG 56 + +#define MASTER_MM_RSCC 0 +#define MASTER_HSCNOC_CNOC 1 +#define SLAVE_AOSS 2 +#define SLAVE_HBCU 3 +#define SLAVE_IPA_CFG 4 +#define SLAVE_IPC_ROUTER_CFG 5 +#define SLAVE_SOCCP 6 +#define SLAVE_TME_CFG 7 +#define SLAVE_PCIE_DMA 8 +#define SLAVE_CNOC_CFG 9 +#define SLAVE_DDRSS_CFG 10 +#define SLAVE_IMEM 11 + +#define MASTER_HPASS_PROC_0 0 +#define MASTER_HPASS_PROC_1 1 +#define MASTER_HPASS_PROC_2 2 +#define SLAVE_HPASS_AGNOC_AUDIO 3 + +#define MASTER_GPU_TCU 0 +#define MASTER_QTC_TCU 1 +#define MASTER_SYS_TCU_0 2 +#define MASTER_SYS_TCU_1 3 +#define MASTER_SYS_TCU_2 4 +#define MASTER_APPSS_PROC 5 +#define MASTER_A1NOC_TILE_HSCNOC 6 +#define MASTER_A2NOC_TILE_HSCNOC 7 +#define MASTER_GFX3D 8 +#define MASTER_GFX3D_1 9 +#define MASTER_HPASS_ADAS_HSCNOC 10 +#define MASTER_HPASS_AUDIO_HSCNOC 11 +#define MASTER_MNOC_HF_MEM_NOC 12 +#define MASTER_MNOC_SF_MEM_NOC 13 +#define MASTER_NSP0_HSCNOC 14 +#define MASTER_NSP1_HSCNOC 15 +#define MASTER_NSP2_HSCNOC 16 +#define MASTER_NSP3_HSCNOC 17 +#define MASTER_ANOC_PCIE_GEM_NOC 18 +#define MASTER_SAILSS_MD0_HSCNOC 19 +#define MASTER_SNOC_SF_MEM_NOC 20 +#define MASTER_GIC 21 +#define SLAVE_HSCNOC_CNOC 22 +#define SLAVE_LLCC 23 +#define SLAVE_MEM_NOC_PCIE_SNOC 24 + +#define MASTER_LLCC 0 +#define SLAVE_EBI1 1 + +#define MASTER_CAMNOC_HF 0 +#define MASTER_CAMNOC_NRT_ICP_SF 1 +#define MASTER_CAMNOC_RT_CDM_SF 2 +#define MASTER_CAMNOC_SF 3 +#define MASTER_DPRX0 4 +#define MASTER_DPRX1 5 +#define MASTER_MDP0 6 +#define MASTER_MDP1 7 +#define MASTER_VIDEO_CV_PROC 8 +#define MASTER_VIDEO_EVA 9 +#define MASTER_VIDEO_MVP0 10 +#define MASTER_VIDEO_MVP1 11 +#define MASTER_VIDEO_V_PROC 12 +#define SLAVE_MNOC_HF_MEM_NOC 13 +#define SLAVE_MNOC_SF_MEM_NOC 14 + +#define MASTER_NSP0_PROC 0 +#define SLAVE_NSP0_HSC_NOC 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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2e53ab8b89csm12556600eec.12.2026.04.19.19.14.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Apr 2026 19:14:30 -0700 (PDT) From: Shawn Guo To: Georgi Djakov Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dmitry Baryshkov , Odelu Kukatla , Konrad Dybcio , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Shawn Guo Subject: [PATCH 2/2] interconnect: qcom: Add interconnect provider driver for Nord SoC Date: Mon, 20 Apr 2026 10:13:51 +0800 Message-ID: <20260420021351.1239355-3-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260420021351.1239355-1-shengchao.guo@oss.qualcomm.com> References: <20260420021351.1239355-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIwMDAxOSBTYWx0ZWRfX3cT7acS7Twvy jVeBBrY2yDX3rLJ+AjMnk92loKmF79DOsBFNvWZFjkKdEegUjiDVZBW9JFYlv/hWOLQ0BGM8dCb 5W6zgGwIy69FkxoAalTwn1tEkcAL86yP96c4kCHe17EUBOujuh4P9LO8xd2bdpd1GNz2HjhPPyL eaEMnMUe8DFi2Gle+UMKJCKWGpfD5v7OjAy+EsQgUxRnGNcB7o10WoIIikBhzWdNMDuLd1KRXts UUDDdLMu3LPuMhwqYHo2Feb1MqQ2q95+cF/pFxHYyTq9XEsmFU7RpQ4RqKlxFjqsOKEoAnCkCqB 2UyZpPWeLIjBnijZRX7uIdNcNg29HYubbCYUAGls2W84Mg4LF4UX70VWoPE5w6hllHSu78kFyPt sJk7U/2mjXcwLTdjB8Ca4ps/DTmeBvuK8aYebfJbd6vdX4wDxZ/0WtAZYHYmybD13TKPiqQ7lkk fpggALgOseMRirXaJiA== X-Authority-Analysis: v=2.4 cv=dcywG3Xe c=1 sm=1 tr=0 ts=69e58c09 cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=dw5cIN1h9ciE3QL4M0UA:9 a=vBUdepa8ALXHeOFLBtFW:22 X-Proofpoint-ORIG-GUID: VIFsK_5OCx7U9bPyekIILhwri_jzWjMO X-Proofpoint-GUID: VIFsK_5OCx7U9bPyekIILhwri_jzWjMO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-19_07,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 bulkscore=0 clxscore=1015 impostorscore=0 lowpriorityscore=0 suspectscore=0 phishscore=0 malwarescore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604200019 Content-Type: text/plain; charset="utf-8" From: Odelu Kukatla Add driver for the Qualcomm interconnect buses found on Nord SoC. The topology consists of several NoCs that are controlled by a remote processor that collects the aggregated bandwidth for each master-slave pair. Signed-off-by: Odelu Kukatla Signed-off-by: Shawn Guo Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio --- drivers/interconnect/qcom/Kconfig | 11 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/nord.c | 2682 ++++++++++++++++++++++++++++ 3 files changed, 2695 insertions(+) create mode 100644 drivers/interconnect/qcom/nord.c diff --git a/drivers/interconnect/qcom/Kconfig b/drivers/interconnect/qcom/= Kconfig index 786b4eda44b4..32808772c363 100644 --- a/drivers/interconnect/qcom/Kconfig +++ b/drivers/interconnect/qcom/Kconfig @@ -107,6 +107,17 @@ config INTERCONNECT_QCOM_MSM8996 This is a driver for the Qualcomm Network-on-Chip on msm8996-based platforms. =20 +config INTERCONNECT_QCOM_NORD + tristate "Qualcomm Nord interconnect driver" + depends on INTERCONNECT_QCOM_RPMH_POSSIBLE + select INTERCONNECT_QCOM_RPMH + select INTERCONNECT_QCOM_BCM_VOTER + help + This is a driver for the Qualcomm Network-on-Chip on Nord-based + platforms. The topology consists of several NoCs controlled by + the RPMh hardware and communicates via Bus Clock Manager (BCM) + through the Resource State Coordinator (RSC). + config INTERCONNECT_QCOM_OSM_L3 tristate "Qualcomm OSM L3 interconnect driver" depends on INTERCONNECT_QCOM || COMPILE_TEST diff --git a/drivers/interconnect/qcom/Makefile b/drivers/interconnect/qcom= /Makefile index cdf2c6c9fbf3..988fa8b0f509 100644 --- a/drivers/interconnect/qcom/Makefile +++ b/drivers/interconnect/qcom/Makefile @@ -16,6 +16,7 @@ qnoc-msm8953-objs :=3D msm8953.o qnoc-msm8974-objs :=3D msm8974.o qnoc-msm8976-objs :=3D msm8976.o qnoc-msm8996-objs :=3D msm8996.o +qnoc-nord-objs :=3D nord.o icc-osm-l3-objs :=3D osm-l3.o qnoc-qcm2290-objs :=3D qcm2290.o qnoc-qcs404-objs :=3D qcs404.o @@ -61,6 +62,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_MSM8953) +=3D qnoc-msm8953= .o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) +=3D qnoc-msm8974.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8976) +=3D qnoc-msm8976.o obj-$(CONFIG_INTERCONNECT_QCOM_MSM8996) +=3D qnoc-msm8996.o +obj-$(CONFIG_INTERCONNECT_QCOM_NORD) +=3D qnoc-nord.o obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) +=3D icc-osm-l3.o obj-$(CONFIG_INTERCONNECT_QCOM_QCM2290) +=3D qnoc-qcm2290.o obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) +=3D qnoc-qcs404.o diff --git a/drivers/interconnect/qcom/nord.c b/drivers/interconnect/qcom/n= ord.c new file mode 100644 index 000000000000..598a9c15632c --- /dev/null +++ b/drivers/interconnect/qcom/nord.c @@ -0,0 +1,2682 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * + */ + +#include +#include +#include +#include +#include +#include + +#include "bcm-voter.h" +#include "icc-rpmh.h" + +static struct qcom_icc_node qup0_core_slave =3D { + .name =3D "qup0_core_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup1_core_slave =3D { + .name =3D "qup1_core_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup2_core_slave =3D { + .name =3D "qup2_core_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qup3_core_slave =3D { + .name =3D "qup3_core_slave", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ps_eth_0 =3D { + .name =3D "ps_eth_0", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ps_eth_1 =3D { + .name =3D "ps_eth_1", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node ps_shs_server =3D { + .name =3D "ps_shs_server", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy0 =3D { + .name =3D "qhs_ahb2phy0", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy1 =3D { + .name =3D "qhs_ahb2phy1", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy2 =3D { + .name =3D "qhs_ahb2phy2", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy3 =3D { + .name =3D "qhs_ahb2phy3", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy_eth_0 =3D { + .name =3D "qhs_ahb2phy_eth_0", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ahb2phy_eth_1 =3D { + .name =3D "qhs_ahb2phy_eth_1", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_camera_cfg =3D { + .name =3D "qhs_camera_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_clk_ctl =3D { + .name =3D "qhs_clk_ctl", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto0_cfg =3D { + .name =3D "qhs_crypto0_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto1_cfg =3D { + .name =3D "qhs_crypto1_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_crypto2_cfg =3D { + .name =3D "qhs_crypto2_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display_1_cfg =3D { + .name =3D "qhs_display_1_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_display_cfg =3D { + .name =3D "qhs_display_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dprx0 =3D { + .name =3D "qhs_dprx0", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_dprx1 =3D { + .name =3D "qhs_dprx1", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_eva_cfg =3D { + .name =3D "qhs_eva_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_gpuss_0_cfg =3D { + .name =3D "qhs_gpuss_0_cfg", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_gpuss_1_cfg =3D { + .name =3D "qhs_gpuss_1_cfg", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_i2c =3D { + .name =3D "qhs_i2c", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_imem_cfg =3D { + .name =3D "qhs_imem_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mcw_pcie =3D { + .name =3D "qhs_mcw_pcie", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_mm_rscc =3D { + .name =3D "qhs_mm_rscc", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ne_clk_ctl =3D { + .name =3D "qhs_ne_clk_ctl", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_nspss0_cfg =3D { + .name =3D "qhs_nspss0_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_nspss1_cfg =3D { + .name =3D "qhs_nspss1_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_nspss2_cfg =3D { + .name =3D "qhs_nspss2_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_nspss3_cfg =3D { + .name =3D "qhs_nspss3_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_nw_clk_ctl =3D { + .name =3D "qhs_nw_clk_ctl", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_prng =3D { + .name =3D "qhs_prng", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qdss_cfg =3D { + .name =3D "qhs_qdss_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qspi =3D { + .name =3D "qhs_qspi", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup0 =3D { + .name =3D "qhs_qup0", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup02 =3D { + .name =3D "qhs_qup02", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup1 =3D { + .name =3D "qhs_qup1", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_qup2 =3D { + .name =3D "qhs_qup2", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_safedma_cfg =3D { + .name =3D "qhs_safedma_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_sdc4 =3D { + .name =3D "qhs_sdc4", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_se_clk_ctl =3D { + .name =3D "qhs_se_clk_ctl", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tcsr =3D { + .name =3D "qhs_tcsr", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tlmm =3D { + .name =3D "qhs_tlmm", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tsc_cfg =3D { + .name =3D "qhs_tsc_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ufs_mem_cfg =3D { + .name =3D "qhs_ufs_mem_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb2 =3D { + .name =3D "qhs_usb2", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_0 =3D { + .name =3D "qhs_usb3_0", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_usb3_1 =3D { + .name =3D "qhs_usb3_1", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_venus_cfg =3D { + .name =3D "qhs_venus_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qss_computenoc_cfg =3D { + .name =3D "qss_computenoc_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qss_qtc_cfg =3D { + .name =3D "qss_qtc_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_qdss_stm =3D { + .name =3D "xs_qdss_stm", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node xs_sys_tcu0_cfg =3D { + .name =3D "xs_sys_tcu0_cfg", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_sys_tcu1_cfg =3D { + .name =3D "xs_sys_tcu1_cfg", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_sys_tcu2_cfg =3D { + .name =3D "xs_sys_tcu2_cfg", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qhs_aoss =3D { + .name =3D "qhs_aoss", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_hbcu =3D { + .name =3D "qhs_hbcu", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipa =3D { + .name =3D "qhs_ipa", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_ipc_router =3D { + .name =3D "qhs_ipc_router", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_soccp =3D { + .name =3D "qhs_soccp", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_tme_cfg =3D { + .name =3D "qhs_tme_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qss_ddrss_cfg =3D { + .name =3D "qss_ddrss_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qxs_imem =3D { + .name =3D "qxs_imem", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node ebi =3D { + .name =3D "ebi", + .channels =3D 16, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_ahb2phy_cfg =3D { + .name =3D "qhs_pcie_ahb2phy_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_cfg_0 =3D { + .name =3D "qhs_pcie_cfg_0", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_cfg_1 =3D { + .name =3D "qhs_pcie_cfg_1", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_cfg_2 =3D { + .name =3D "qhs_pcie_cfg_2", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_cfg_3 =3D { + .name =3D "qhs_pcie_cfg_3", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_dma_0_cfg =3D { + .name =3D "qhs_pcie_dma_0_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_dma_1_cfg =3D { + .name =3D "qhs_pcie_dma_1_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qhs_pcie_dma_2_cfg =3D { + .name =3D "qhs_pcie_dma_2_cfg", + .channels =3D 1, + .buswidth =3D 4, +}; + +static struct qcom_icc_node qxs_pcie_dma_0 =3D { + .name =3D "qxs_pcie_dma_0", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pcie_dma_1 =3D { + .name =3D "qxs_pcie_dma_1", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qxs_pcie_dma_2 =3D { + .name =3D "qxs_pcie_dma_2", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node xs_pcie_0 =3D { + .name =3D "xs_pcie_0", + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node xs_pcie_1 =3D { + .name =3D "xs_pcie_1", + .channels =3D 1, + .buswidth =3D 32, +}; + +static struct qcom_icc_node xs_pcie_2 =3D { + .name =3D "xs_pcie_2", + .channels =3D 1, + .buswidth =3D 16, +}; + +static struct qcom_icc_node xs_pcie_3 =3D { + .name =3D "xs_pcie_3", + .channels =3D 1, + .buswidth =3D 8, +}; + +static struct qcom_icc_node qup0_core_master =3D { + .name =3D "qup0_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qup0_core_slave }, +}; + +static struct qcom_icc_node qup1_core_master =3D { + .name =3D "qup1_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qup1_core_slave }, +}; + +static struct qcom_icc_node qup2_core_master =3D { + .name =3D "qup2_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qup2_core_slave }, +}; + +static struct qcom_icc_node qup3_core_master =3D { + .name =3D "qup3_core_master", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qup3_core_slave }, +}; + +static struct qcom_icc_node llcc_mc =3D { + .name =3D "llcc_mc", + .channels =3D 16, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &ebi }, +}; + +static struct qcom_icc_node qsm_pcie_noc_cfg =3D { + .name =3D "qsm_pcie_noc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 8, + .link_nodes =3D { &qhs_pcie_ahb2phy_cfg, &qhs_pcie_cfg_0, + &qhs_pcie_cfg_1, &qhs_pcie_cfg_2, + &qhs_pcie_cfg_3, &qhs_pcie_dma_0_cfg, + &qhs_pcie_dma_1_cfg, &qhs_pcie_dma_2_cfg }, +}; + +static struct qcom_icc_node qnm_cnoc_pcie_dma =3D { + .name =3D "qnm_cnoc_pcie_dma", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 3, + .link_nodes =3D { &qxs_pcie_dma_0, &qxs_pcie_dma_1, + &qxs_pcie_dma_2 }, +}; + +static struct qcom_icc_node qnm_hscnoc_pcie =3D { + .name =3D "qnm_hscnoc_pcie", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 4, + .link_nodes =3D { &xs_pcie_0, &xs_pcie_1, + &xs_pcie_2, &xs_pcie_3 }, +}; + +static struct qcom_icc_node qnm_pcie_ibnoc_dma =3D { + .name =3D "qnm_pcie_ibnoc_dma", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &xs_pcie_0 }, +}; + +static struct qcom_icc_node qss_pcie_noc_cfg =3D { + .name =3D "qss_pcie_noc_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qsm_pcie_noc_cfg }, +}; + +static struct qcom_icc_node qns_pcie_dma =3D { + .name =3D "qns_pcie_dma", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_cnoc_pcie_dma }, +}; + +static struct qcom_icc_node qns_llcc =3D { + .name =3D "qns_llcc", + .channels =3D 16, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &llcc_mc }, +}; + +static struct qcom_icc_node qns_pcie =3D { + .name =3D "qns_pcie", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_hscnoc_pcie }, +}; + +static struct qcom_icc_node qns_pcie_obnoc_dma =3D { + .name =3D "qns_pcie_obnoc_dma", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_pcie_ibnoc_dma }, +}; + +static struct qcom_icc_node qsm_cfg =3D { + .name =3D "qsm_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 56, + .link_nodes =3D { &ps_eth_0, &ps_eth_1, + &ps_shs_server, &qhs_ahb2phy0, + &qhs_ahb2phy1, &qhs_ahb2phy2, + &qhs_ahb2phy3, &qhs_ahb2phy_eth_0, + &qhs_ahb2phy_eth_1, &qhs_camera_cfg, + &qhs_clk_ctl, &qhs_crypto0_cfg, + &qhs_crypto1_cfg, &qhs_crypto2_cfg, + &qhs_display_1_cfg, &qhs_display_cfg, + &qhs_dprx0, &qhs_dprx1, + &qhs_eva_cfg, &qhs_gpuss_0_cfg, + &qhs_gpuss_1_cfg, &qhs_i2c, + &qhs_imem_cfg, &qhs_mcw_pcie, + &qhs_mm_rscc, &qhs_ne_clk_ctl, + &qhs_nspss0_cfg, &qhs_nspss1_cfg, + &qhs_nspss2_cfg, &qhs_nspss3_cfg, + &qhs_nw_clk_ctl, &qhs_prng, + &qhs_qdss_cfg, &qhs_qspi, + &qhs_qup0, &qhs_qup02, + &qhs_qup1, &qhs_qup2, + &qhs_safedma_cfg, &qhs_sdc4, + &qhs_se_clk_ctl, &qhs_tcsr, + &qhs_tlmm, &qhs_tsc_cfg, + &qhs_ufs_mem_cfg, &qhs_usb2, + &qhs_usb3_0, &qhs_usb3_1, + &qhs_venus_cfg, &qss_computenoc_cfg, + &qss_pcie_noc_cfg, &qss_qtc_cfg, + &xs_qdss_stm, &xs_sys_tcu0_cfg, + &xs_sys_tcu1_cfg, &xs_sys_tcu2_cfg }, +}; + +static struct qcom_icc_node xm_gic =3D { + .name =3D "xm_gic", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa44000 }, + .prio =3D 4, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_node qss_cfg =3D { + .name =3D "qss_cfg", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qsm_cfg }, +}; + +static struct qcom_icc_node qhm_mm_rscc =3D { + .name =3D "qhm_mm_rscc", + .channels =3D 1, + .buswidth =3D 4, + .num_links =3D 1, + .link_nodes =3D { &qss_cfg }, +}; + +static struct qcom_icc_node qnm_hscnoc =3D { + .name =3D "qnm_hscnoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 10, + .link_nodes =3D { &qhs_aoss, &qhs_hbcu, + &qhs_ipa, &qhs_ipc_router, + &qhs_soccp, &qhs_tme_cfg, + &qns_pcie_dma, &qss_cfg, + &qss_ddrss_cfg, &qxs_imem }, +}; + +static struct qcom_icc_node qns_hscnoc_cnoc =3D { + .name =3D "qns_hscnoc_cnoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_hscnoc }, +}; + +static struct qcom_icc_node alm_gpu_tcu =3D { + .name =3D "alm_gpu_tcu", + .channels =3D 2, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x930000, 0xa45000 }, + .prio =3D 1, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 2, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node alm_qtc =3D { + .name =3D "alm_qtc", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x242000 }, + .prio =3D 3, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 2, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node alm_sys_tcu0 =3D { + .name =3D "alm_sys_tcu0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa42000 }, + .prio =3D 6, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 2, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node alm_sys_tcu1 =3D { + .name =3D "alm_sys_tcu1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x81c000 }, + .prio =3D 6, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 2, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node alm_sys_tcu2 =3D { + .name =3D "alm_sys_tcu2", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x30000 }, + .prio =3D 6, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 2, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node chm_apps =3D { + .name =3D "chm_apps", + .channels =3D 6, + .buswidth =3D 32, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_aggre_north =3D { + .name =3D "qnm_aggre_north", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x935000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_aggre_south =3D { + .name =3D "qnm_aggre_south", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x31000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_gpu0 =3D { + .name =3D "qnm_gpu0", + .channels =3D 4, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 4, + .port_offsets =3D { 0x931000, 0x932000, 0x933000, 0x934000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_gpu1 =3D { + .name =3D "qnm_gpu1", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0xa40000, 0xa41000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_hpass_adas_hscnoc =3D { + .name =3D "qnm_hpass_adas_hscnoc", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x240000, 0x245000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_hpass_audio_hscnoc =3D { + .name =3D "qnm_hpass_audio_hscnoc", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x241000 }, + .prio =3D 3, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mnoc_hf =3D { + .name =3D "qnm_mnoc_hf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x81a000, 0x81d000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_mnoc_sf =3D { + .name =3D "qnm_mnoc_sf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x81b000, 0x81e000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_nsp0_hscnoc =3D { + .name =3D "qnm_nsp0_hscnoc", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x32000, 0x33000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_nsp1_hscnoc =3D { + .name =3D "qnm_nsp1_hscnoc", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x34000, 0x35000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_nsp2_hscnoc =3D { + .name =3D "qnm_nsp2_hscnoc", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x36000, 0x37000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_nsp3_hscnoc =3D { + .name =3D "qnm_nsp3_hscnoc", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x38000, 0x39000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_pcie =3D { + .name =3D "qnm_pcie", + .channels =3D 1, + .buswidth =3D 64, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x244000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 2, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc }, +}; + +static struct qcom_icc_node qnm_sailss_md0_hscnoc =3D { + .name =3D "qnm_sailss_md0_hscnoc", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x243000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qnm_snoc_sf =3D { + .name =3D "qnm_snoc_sf", + .channels =3D 1, + .buswidth =3D 64, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0xa43000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 3, + .link_nodes =3D { &qns_hscnoc_cnoc, &qns_llcc, + &qns_pcie }, +}; + +static struct qcom_icc_node qns_a1noc_hscnoc =3D { + .name =3D "qns_a1noc_hscnoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_aggre_north }, +}; + +static struct qcom_icc_node qns_a2noc_hscnoc =3D { + .name =3D "qns_a2noc_hscnoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_aggre_south }, +}; + +static struct qcom_icc_node qns_hpass_agnoc_audio =3D { + .name =3D "qns_hpass_agnoc_audio", + .channels =3D 1, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_hpass_audio_hscnoc }, +}; + +static struct qcom_icc_node qns_mem_noc_hf =3D { + .name =3D "qns_mem_noc_hf", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_mnoc_hf }, +}; + +static struct qcom_icc_node qns_mem_noc_sf =3D { + .name =3D "qns_mem_noc_sf", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_mnoc_sf }, +}; + +static struct qcom_icc_node qns_nsp0_hsc_noc =3D { + .name =3D "qns_nsp0_hsc_noc", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_nsp0_hscnoc }, +}; + +static struct qcom_icc_node qns_nsp1_hsc_noc =3D { + .name =3D "qns_nsp1_hsc_noc", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_nsp1_hscnoc }, +}; + +static struct qcom_icc_node qns_nsp2_hsc_noc =3D { + .name =3D "qns_nsp2_hsc_noc", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_nsp2_hscnoc }, +}; + +static struct qcom_icc_node qns_nsp3_hsc_noc =3D { + .name =3D "qns_nsp3_hsc_noc", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qnm_nsp3_hscnoc }, +}; + +static struct qcom_icc_node qns_pcie_hscnoc =3D { + .name =3D "qns_pcie_hscnoc", + .channels =3D 1, + .buswidth =3D 64, + .num_links =3D 1, + .link_nodes =3D { &qnm_pcie }, +}; + +static struct qcom_icc_node qns_hscnoc_sf =3D { + .name =3D "qns_hscnoc_sf", + .channels =3D 1, + .buswidth =3D 64, + .num_links =3D 1, + .link_nodes =3D { &qnm_snoc_sf }, +}; + +static struct qcom_icc_node qhm_qup2 =3D { + .name =3D "qhm_qup2", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1b000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_hscnoc }, +}; + +static struct qcom_icc_node qxm_crypto_0 =3D { + .name =3D "qxm_crypto_0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1c000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_hscnoc }, +}; + +static struct qcom_icc_node qxm_crypto_1 =3D { + .name =3D "qxm_crypto_1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1d000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_hscnoc }, +}; + +static struct qcom_icc_node qxm_crypto_2 =3D { + .name =3D "qxm_crypto_2", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1e000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_hscnoc }, +}; + +static struct qcom_icc_node xm_sdc4 =3D { + .name =3D "xm_sdc4", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_hscnoc }, +}; + +static struct qcom_icc_node xm_ufs_mem =3D { + .name =3D "xm_ufs_mem", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_hscnoc }, +}; + +static struct qcom_icc_node xm_usb2 =3D { + .name =3D "xm_usb2", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x19000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_hscnoc }, +}; + +static struct qcom_icc_node xm_usb3_0 =3D { + .name =3D "xm_usb3_0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_hscnoc }, +}; + +static struct qcom_icc_node xm_usb3_1 =3D { + .name =3D "xm_usb3_1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1a000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_hscnoc }, +}; + +static struct qcom_icc_node qhm_qup0 =3D { + .name =3D "qhm_qup0", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_hscnoc }, +}; + +static struct qcom_icc_node qhm_qup1 =3D { + .name =3D "qhm_qup1", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_hscnoc }, +}; + +static struct qcom_icc_node xm_emac_0 =3D { + .name =3D "xm_emac_0", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_hscnoc }, +}; + +static struct qcom_icc_node xm_emac_1 =3D { + .name =3D "xm_emac_1", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_hscnoc }, +}; + +static struct qcom_icc_node qnm_hpass_dsp0 =3D { + .name =3D "qnm_hpass_dsp0", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qns_hpass_agnoc_audio }, +}; + +static struct qcom_icc_node qnm_hpass_dsp1 =3D { + .name =3D "qnm_hpass_dsp1", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qns_hpass_agnoc_audio }, +}; + +static struct qcom_icc_node qnm_hpass_dsp2 =3D { + .name =3D "qnm_hpass_dsp2", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qns_hpass_agnoc_audio }, +}; + +static struct qcom_icc_node qnm_camnoc_hf =3D { + .name =3D "qnm_camnoc_hf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x57000, 0x58000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_camnoc_nrt_icp_sf =3D { + .name =3D "qnm_camnoc_nrt_icp_sf", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1a000 }, + .prio =3D 4, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_rt_cdm_sf =3D { + .name =3D "qnm_camnoc_rt_cdm_sf", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x5b000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_camnoc_sf =3D { + .name =3D "qnm_camnoc_sf", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x1b000, 0x1c000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_dprx0 =3D { + .name =3D "qnm_dprx0", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x5c000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_dprx1 =3D { + .name =3D "qnm_dprx1", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x5d000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_mdp0 =3D { + .name =3D "qnm_mdp0", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x59000, 0x5a000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_mdp1 =3D { + .name =3D "qnm_mdp1", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x5e000, 0x5f000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_node qnm_video_cv_cpu =3D { + .name =3D "qnm_video_cv_cpu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x21000 }, + .prio =3D 4, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_eva =3D { + .name =3D "qnm_video_eva", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x22000, 0x23000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_mvp0 =3D { + .name =3D "qnm_video_mvp0", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x1d000, 0x1e000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_mvp1 =3D { + .name =3D "qnm_video_mvp1", + .channels =3D 2, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 2, + .port_offsets =3D { 0x1f000, 0x20000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_video_v_cpu =3D { + .name =3D "qnm_video_v_cpu", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x24000 }, + .prio =3D 4, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_mem_noc_sf }, +}; + +static struct qcom_icc_node qnm_nsp_data00 =3D { + .name =3D "qnm_nsp_data00", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qns_nsp0_hsc_noc }, +}; + +static struct qcom_icc_node qnm_nsp_data01 =3D { + .name =3D "qnm_nsp_data01", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qns_nsp1_hsc_noc }, +}; + +static struct qcom_icc_node qnm_nsp_data02 =3D { + .name =3D "qnm_nsp_data02", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qns_nsp2_hsc_noc }, +}; + +static struct qcom_icc_node qnm_nsp_data03 =3D { + .name =3D "qnm_nsp_data03", + .channels =3D 2, + .buswidth =3D 32, + .num_links =3D 1, + .link_nodes =3D { &qns_nsp3_hsc_noc }, +}; + +static struct qcom_icc_node qxm_pcie_dma_0 =3D { + .name =3D "qxm_pcie_dma_0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x49000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 2, + .link_nodes =3D { &qns_pcie_hscnoc, &qns_pcie_obnoc_dma }, +}; + +static struct qcom_icc_node qxm_pcie_dma_1 =3D { + .name =3D "qxm_pcie_dma_1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x4a000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 2, + .link_nodes =3D { &qns_pcie_hscnoc, &qns_pcie_obnoc_dma }, +}; + +static struct qcom_icc_node qxm_pcie_dma_2 =3D { + .name =3D "qxm_pcie_dma_2", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x4b000 }, + .prio =3D 0, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 2, + .link_nodes =3D { &qns_pcie_hscnoc, &qns_pcie_obnoc_dma }, +}; + +static struct qcom_icc_node xm_pcie_0 =3D { + .name =3D "xm_pcie_0", + .channels =3D 1, + .buswidth =3D 64, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_pcie_hscnoc }, +}; + +static struct qcom_icc_node xm_pcie_1 =3D { + .name =3D "xm_pcie_1", + .channels =3D 1, + .buswidth =3D 32, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x19000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_pcie_hscnoc }, +}; + +static struct qcom_icc_node xm_pcie_2 =3D { + .name =3D "xm_pcie_2", + .channels =3D 1, + .buswidth =3D 16, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1a000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_pcie_hscnoc }, +}; + +static struct qcom_icc_node xm_pcie_3 =3D { + .name =3D "xm_pcie_3", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1b000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_pcie_hscnoc }, +}; + +static struct qcom_icc_node qnm_aggre1_noc =3D { + .name =3D "qnm_aggre1_noc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qns_hscnoc_sf }, +}; + +static struct qcom_icc_node qnm_aggre2_noc =3D { + .name =3D "qnm_aggre2_noc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qns_hscnoc_sf }, +}; + +static struct qcom_icc_node qnm_cnoc_data =3D { + .name =3D "qnm_cnoc_data", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1a000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_hscnoc_sf }, +}; + +static struct qcom_icc_node qnm_nsi_noc =3D { + .name =3D "qnm_nsi_noc", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x19000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_hscnoc_sf }, +}; + +static struct qcom_icc_node qnm_safe_dma =3D { + .name =3D "qnm_safe_dma", + .channels =3D 1, + .buswidth =3D 64, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x1b000 }, + .prio =3D 0, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 0, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_hscnoc_sf }, +}; + +static struct qcom_icc_node qns_a1noc_snoc =3D { + .name =3D "qns_a1noc_snoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_node qns_a2noc_snoc =3D { + .name =3D "qns_a2noc_snoc", + .channels =3D 1, + .buswidth =3D 16, + .num_links =3D 1, + .link_nodes =3D { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_node qhm_qspi =3D { + .name =3D "qhm_qspi", + .channels =3D 1, + .buswidth =3D 4, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x18000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qnm_sailss_md1 =3D { + .name =3D "qnm_sailss_md1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_qup02 =3D { + .name =3D "qxm_qup02", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x17000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a1noc_snoc }, +}; + +static struct qcom_icc_node qxm_ipa =3D { + .name =3D "qxm_ipa", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x13000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node qxm_soccp =3D { + .name =3D "qxm_soccp", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x16000 }, + .prio =3D 2, + .urg_fwd =3D 1, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_0 =3D { + .name =3D "xm_qdss_etr_0", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x14000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_node xm_qdss_etr_1 =3D { + .name =3D "xm_qdss_etr_1", + .channels =3D 1, + .buswidth =3D 8, + .qosbox =3D &(const struct qcom_icc_qosbox) { + .num_ports =3D 1, + .port_offsets =3D { 0x15000 }, + .prio =3D 2, + .urg_fwd =3D 0, + .prio_fwd_disable =3D 1, + }, + .num_links =3D 1, + .link_nodes =3D { &qns_a2noc_snoc }, +}; + +static struct qcom_icc_bcm bcm_c0n0 =3D { + .name =3D "C0N0", + .enable_mask =3D BIT(0), + .num_nodes =3D 2, + .nodes =3D { &qnm_nsp_data00, &qns_nsp0_hsc_noc }, +}; + +static struct qcom_icc_bcm bcm_c1n0 =3D { + .name =3D "C1N0", + .enable_mask =3D BIT(0), + .num_nodes =3D 2, + .nodes =3D { &qnm_nsp_data01, &qns_nsp1_hsc_noc }, +}; + +static struct qcom_icc_bcm bcm_c2n0 =3D { + .name =3D "C2N0", + .enable_mask =3D BIT(0), + .num_nodes =3D 2, + .nodes =3D { &qnm_nsp_data02, &qns_nsp2_hsc_noc }, +}; + +static struct qcom_icc_bcm bcm_c3n0 =3D { + .name =3D "C3N0", + .enable_mask =3D BIT(0), + .num_nodes =3D 2, + .nodes =3D { &qnm_nsp_data03, &qns_nsp3_hsc_noc }, +}; + +static struct qcom_icc_bcm bcm_ce0 =3D { + .name =3D "CE0", + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto_0 }, +}; + +static struct qcom_icc_bcm bcm_ce1 =3D { + .name =3D "CE1", + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto_1 }, +}; + +static struct qcom_icc_bcm bcm_ce2 =3D { + .name =3D "CE2", + .num_nodes =3D 1, + .nodes =3D { &qxm_crypto_2 }, +}; + +static struct qcom_icc_bcm bcm_cn0 =3D { + .name =3D "CN0", + .keepalive =3D true, + .enable_mask =3D BIT(0), + .num_nodes =3D 6, + .nodes =3D { &qsm_cfg, &qhm_mm_rscc, + &qnm_hscnoc, &qnm_cnoc_pcie_dma, + &qnm_hscnoc_pcie, &qnm_pcie_ibnoc_dma }, +}; + +static struct qcom_icc_bcm bcm_cn1 =3D { + .name =3D "CN1", + .num_nodes =3D 2, + .nodes =3D { &qhs_display_1_cfg, &qhs_display_cfg }, +}; + +static struct qcom_icc_bcm bcm_mc0 =3D { + .name =3D "MC0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &ebi }, +}; + +static struct qcom_icc_bcm bcm_mm0 =3D { + .name =3D "MM0", + .num_nodes =3D 1, + .nodes =3D { &qns_mem_noc_hf }, +}; + +static struct qcom_icc_bcm bcm_mm1 =3D { + .name =3D "MM1", + .enable_mask =3D BIT(0), + .num_nodes =3D 14, + .nodes =3D { &qnm_camnoc_hf, &qnm_camnoc_nrt_icp_sf, + &qnm_camnoc_rt_cdm_sf, &qnm_camnoc_sf, + &qnm_dprx0, &qnm_dprx1, + &qnm_mdp0, &qnm_mdp1, + &qnm_video_cv_cpu, &qnm_video_eva, + &qnm_video_mvp0, &qnm_video_mvp1, + &qnm_video_v_cpu, &qns_mem_noc_sf }, +}; + +static struct qcom_icc_bcm bcm_qup0 =3D { + .name =3D "QUP0", + .vote_scale =3D 1, + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qup0_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup1 =3D { + .name =3D "QUP1", + .vote_scale =3D 1, + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qup1_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup2 =3D { + .name =3D "QUP2", + .vote_scale =3D 1, + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qup2_core_slave }, +}; + +static struct qcom_icc_bcm bcm_qup3 =3D { + .name =3D "QUP3", + .vote_scale =3D 1, + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qup3_core_slave }, +}; + +static struct qcom_icc_bcm bcm_sh0 =3D { + .name =3D "SH0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_llcc }, +}; + +static struct qcom_icc_bcm bcm_sh1 =3D { + .name =3D "SH1", + .enable_mask =3D BIT(0), + .num_nodes =3D 24, + .nodes =3D { &alm_gpu_tcu, &alm_qtc, + &alm_sys_tcu0, &alm_sys_tcu1, + &alm_sys_tcu2, &chm_apps, + &qnm_aggre_north, &qnm_aggre_south, + &qnm_gpu0, &qnm_gpu1, + &qnm_hpass_adas_hscnoc, &qnm_hpass_audio_hscnoc, + &qnm_mnoc_hf, &qnm_mnoc_sf, + &qnm_nsp0_hscnoc, &qnm_nsp1_hscnoc, + &qnm_nsp2_hscnoc, &qnm_nsp3_hscnoc, + &qnm_pcie, &qnm_sailss_md0_hscnoc, + &qnm_snoc_sf, &xm_gic, + &qns_hscnoc_cnoc, &qns_pcie }, +}; + +static struct qcom_icc_bcm bcm_sn0 =3D { + .name =3D "SN0", + .keepalive =3D true, + .num_nodes =3D 1, + .nodes =3D { &qns_hscnoc_sf }, +}; + +static struct qcom_icc_bcm bcm_sn1 =3D { + .name =3D "SN1", + .enable_mask =3D BIT(0), + .num_nodes =3D 14, + .nodes =3D { &qns_a1noc_hscnoc, &qns_a2noc_hscnoc, + &qxm_pcie_dma_0, &qxm_pcie_dma_1, + &qxm_pcie_dma_2, &xm_pcie_0, + &xm_pcie_1, &xm_pcie_2, + &xm_pcie_3, &qns_pcie_hscnoc, + &qns_pcie_obnoc_dma, &qnm_cnoc_data, + &qnm_nsi_noc, &qnm_safe_dma }, +}; + +static struct qcom_icc_bcm bcm_sn2 =3D { + .name =3D "SN2", + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre1_noc }, +}; + +static struct qcom_icc_bcm bcm_sn3 =3D { + .name =3D "SN3", + .num_nodes =3D 1, + .nodes =3D { &qnm_aggre2_noc }, +}; + +static struct qcom_icc_node * const aggre1_noc_nodes[] =3D { + [MASTER_QSPI_0] =3D &qhm_qspi, + [MASTER_SAILSS_MD1] =3D &qnm_sailss_md1, + [MASTER_QUP_3] =3D &qxm_qup02, + [SLAVE_A1NOC_SNOC] =3D &qns_a1noc_snoc, +}; + +static const struct regmap_config nord_aggre1_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1c400, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_aggre1_noc =3D { + .config =3D &nord_aggre1_noc_regmap_config, + .nodes =3D aggre1_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre1_noc_nodes), +}; + +static struct qcom_icc_bcm * const aggre1_noc_tile_bcms[] =3D { + &bcm_ce0, + &bcm_ce1, + &bcm_ce2, + &bcm_sn1, +}; + +static struct qcom_icc_node * const aggre1_noc_tile_nodes[] =3D { + [MASTER_QUP_2] =3D &qhm_qup2, + [MASTER_CRYPTO_CORE0] =3D &qxm_crypto_0, + [MASTER_CRYPTO_CORE1] =3D &qxm_crypto_1, + [MASTER_CRYPTO_CORE2] =3D &qxm_crypto_2, + [MASTER_SDCC_4] =3D &xm_sdc4, + [MASTER_UFS_MEM] =3D &xm_ufs_mem, + [MASTER_USB2] =3D &xm_usb2, + [MASTER_USB3_0] =3D &xm_usb3_0, + [MASTER_USB3_1] =3D &xm_usb3_1, + [SLAVE_A1NOC_HSCNOC] =3D &qns_a1noc_hscnoc, +}; + +static const struct regmap_config nord_aggre1_noc_tile_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x23400, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_aggre1_noc_tile =3D { + .config =3D &nord_aggre1_noc_tile_regmap_config, + .nodes =3D aggre1_noc_tile_nodes, + .num_nodes =3D ARRAY_SIZE(aggre1_noc_tile_nodes), + .bcms =3D aggre1_noc_tile_bcms, + .num_bcms =3D ARRAY_SIZE(aggre1_noc_tile_bcms), +}; + +static struct qcom_icc_node * const aggre2_noc_nodes[] =3D { + [MASTER_IPA] =3D &qxm_ipa, + [MASTER_SOCCP_AGGR_NOC] =3D &qxm_soccp, + [MASTER_QDSS_ETR] =3D &xm_qdss_etr_0, + [MASTER_QDSS_ETR_1] =3D &xm_qdss_etr_1, + [SLAVE_A2NOC_SNOC] =3D &qns_a2noc_snoc, +}; + +static const struct regmap_config nord_aggre2_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1b400, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_aggre2_noc =3D { + .config =3D &nord_aggre2_noc_regmap_config, + .nodes =3D aggre2_noc_nodes, + .num_nodes =3D ARRAY_SIZE(aggre2_noc_nodes), +}; + +static struct qcom_icc_bcm * const aggre2_noc_tile_bcms[] =3D { + &bcm_sn1, +}; + +static struct qcom_icc_node * const aggre2_noc_tile_nodes[] =3D { + [MASTER_QUP_0] =3D &qhm_qup0, + [MASTER_QUP_1] =3D &qhm_qup1, + [MASTER_EMAC_0] =3D &xm_emac_0, + [MASTER_EMAC_1] =3D &xm_emac_1, + [SLAVE_A2NOC_HSCNOC] =3D &qns_a2noc_hscnoc, +}; + +static const struct regmap_config nord_aggre2_noc_tile_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1b400, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_aggre2_noc_tile =3D { + .config =3D &nord_aggre2_noc_tile_regmap_config, + .nodes =3D aggre2_noc_tile_nodes, + .num_nodes =3D ARRAY_SIZE(aggre2_noc_tile_nodes), + .bcms =3D aggre2_noc_tile_bcms, + .num_bcms =3D ARRAY_SIZE(aggre2_noc_tile_bcms), +}; + +static struct qcom_icc_bcm * const clk_virt_bcms[] =3D { + &bcm_qup0, + &bcm_qup1, + &bcm_qup2, + &bcm_qup3, +}; + +static struct qcom_icc_node * const clk_virt_nodes[] =3D { + [MASTER_QUP_CORE_0] =3D &qup0_core_master, + [MASTER_QUP_CORE_1] =3D &qup1_core_master, + [MASTER_QUP_CORE_2] =3D &qup2_core_master, + [MASTER_QUP_CORE_3] =3D &qup3_core_master, + [SLAVE_QUP_CORE_0] =3D &qup0_core_slave, + [SLAVE_QUP_CORE_1] =3D &qup1_core_slave, + [SLAVE_QUP_CORE_2] =3D &qup2_core_slave, + [SLAVE_QUP_CORE_3] =3D &qup3_core_slave, +}; + +static const struct qcom_icc_desc nord_clk_virt =3D { + .nodes =3D clk_virt_nodes, + .num_nodes =3D ARRAY_SIZE(clk_virt_nodes), + .bcms =3D clk_virt_bcms, + .num_bcms =3D ARRAY_SIZE(clk_virt_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_cfg_bcms[] =3D { + &bcm_cn0, + &bcm_cn1, +}; + +static struct qcom_icc_node * const cnoc_cfg_nodes[] =3D { + [MASTER_CNOC_CFG] =3D &qsm_cfg, + [SLAVE_PS_ETH_0] =3D &ps_eth_0, + [SLAVE_PS_ETH_1] =3D &ps_eth_1, + [SLAVE_SHS_SERVER] =3D &ps_shs_server, + [SLAVE_AHB2PHY_0] =3D &qhs_ahb2phy0, + [SLAVE_AHB2PHY_1] =3D &qhs_ahb2phy1, + [SLAVE_AHB2PHY_2] =3D &qhs_ahb2phy2, + [SLAVE_AHB2PHY_3] =3D &qhs_ahb2phy3, + [SLAVE_AHB2PHY_ETH_0] =3D &qhs_ahb2phy_eth_0, + [SLAVE_AHB2PHY_ETH_1] =3D &qhs_ahb2phy_eth_1, + [SLAVE_CAMERA_CFG] =3D &qhs_camera_cfg, + [SLAVE_CLK_CTL] =3D &qhs_clk_ctl, + [SLAVE_CRYPTO_0_CFG] =3D &qhs_crypto0_cfg, + [SLAVE_CRYPTO_1_CFG] =3D &qhs_crypto1_cfg, + [SLAVE_CRYPTO_2_CFG] =3D &qhs_crypto2_cfg, + [SLAVE_DISPLAY_1_CFG] =3D &qhs_display_1_cfg, + [SLAVE_DISPLAY_CFG] =3D &qhs_display_cfg, + [SLAVE_DPRX0] =3D &qhs_dprx0, + [SLAVE_DPRX1] =3D &qhs_dprx1, + [SLAVE_EVA_CFG] =3D &qhs_eva_cfg, + [SLAVE_GFX3D_CFG] =3D &qhs_gpuss_0_cfg, + [SLAVE_GFX3D_1_CFG] =3D &qhs_gpuss_1_cfg, + [SLAVE_I2C] =3D &qhs_i2c, + [SLAVE_IMEM_CFG] =3D &qhs_imem_cfg, + [SLAVE_MCW_PCIE] =3D &qhs_mcw_pcie, + [SLAVE_MM_RSCC] =3D &qhs_mm_rscc, + [SLAVE_NE_CLK_CTL] =3D &qhs_ne_clk_ctl, + [SLAVE_NSPSS0_CFG] =3D &qhs_nspss0_cfg, + [SLAVE_NSPSS1_CFG] =3D &qhs_nspss1_cfg, + [SLAVE_NSPSS2_CFG] =3D &qhs_nspss2_cfg, + [SLAVE_NSPSS3_CFG] =3D &qhs_nspss3_cfg, + [SLAVE_NW_CLK_CTL] =3D &qhs_nw_clk_ctl, + [SLAVE_PRNG] =3D &qhs_prng, + [SLAVE_QDSS_CFG] =3D &qhs_qdss_cfg, + [SLAVE_QSPI_0] =3D &qhs_qspi, + [SLAVE_QUP_0] =3D &qhs_qup0, + [SLAVE_QUP_3] =3D &qhs_qup02, + [SLAVE_QUP_1] =3D &qhs_qup1, + [SLAVE_QUP_2] =3D &qhs_qup2, + [SLAVE_SAFEDMA_CFG] =3D &qhs_safedma_cfg, + [SLAVE_SDCC_4] =3D &qhs_sdc4, + [SLAVE_SE_CLK_CTL] =3D &qhs_se_clk_ctl, + [SLAVE_TCSR] =3D &qhs_tcsr, + [SLAVE_TLMM] =3D &qhs_tlmm, + [SLAVE_TSC_CFG] =3D &qhs_tsc_cfg, + [SLAVE_UFS_MEM_CFG] =3D &qhs_ufs_mem_cfg, + [SLAVE_USB2] =3D &qhs_usb2, + [SLAVE_USB3_0] =3D &qhs_usb3_0, + [SLAVE_USB3_1] =3D &qhs_usb3_1, + [SLAVE_VENUS_CFG] =3D &qhs_venus_cfg, + [SLAVE_COMPUTENOC_CFG] =3D &qss_computenoc_cfg, + [SLAVE_PCIE_NOC_CFG] =3D &qss_pcie_noc_cfg, + [SLAVE_QTC_CFG] =3D &qss_qtc_cfg, + [SLAVE_QDSS_STM] =3D &xs_qdss_stm, + [SLAVE_SYS_TCU0_CFG] =3D &xs_sys_tcu0_cfg, + [SLAVE_SYS_TCU1_CFG] =3D &xs_sys_tcu1_cfg, + [SLAVE_SYS_TCU2_CFG] =3D &xs_sys_tcu2_cfg, +}; + +static const struct regmap_config nord_cnoc_cfg_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0xd200, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_cnoc_cfg =3D { + .config =3D &nord_cnoc_cfg_regmap_config, + .nodes =3D cnoc_cfg_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_cfg_nodes), + .bcms =3D cnoc_cfg_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_cfg_bcms), +}; + +static struct qcom_icc_bcm * const cnoc_main_bcms[] =3D { + &bcm_cn0, +}; + +static struct qcom_icc_node * const cnoc_main_nodes[] =3D { + [MASTER_MM_RSCC] =3D &qhm_mm_rscc, + [MASTER_HSCNOC_CNOC] =3D &qnm_hscnoc, + [SLAVE_AOSS] =3D &qhs_aoss, + [SLAVE_HBCU] =3D &qhs_hbcu, + [SLAVE_IPA_CFG] =3D &qhs_ipa, + [SLAVE_IPC_ROUTER_CFG] =3D &qhs_ipc_router, + [SLAVE_SOCCP] =3D &qhs_soccp, + [SLAVE_TME_CFG] =3D &qhs_tme_cfg, + [SLAVE_PCIE_DMA] =3D &qns_pcie_dma, + [SLAVE_CNOC_CFG] =3D &qss_cfg, + [SLAVE_DDRSS_CFG] =3D &qss_ddrss_cfg, + [SLAVE_IMEM] =3D &qxs_imem, +}; + +static const struct regmap_config nord_cnoc_main_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1d200, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_cnoc_main =3D { + .config =3D &nord_cnoc_main_regmap_config, + .nodes =3D cnoc_main_nodes, + .num_nodes =3D ARRAY_SIZE(cnoc_main_nodes), + .bcms =3D cnoc_main_bcms, + .num_bcms =3D ARRAY_SIZE(cnoc_main_bcms), +}; + +static struct qcom_icc_node * const hpass_ag_noc_nodes[] =3D { + [MASTER_HPASS_PROC_0] =3D &qnm_hpass_dsp0, + [MASTER_HPASS_PROC_1] =3D &qnm_hpass_dsp1, + [MASTER_HPASS_PROC_2] =3D &qnm_hpass_dsp2, + [SLAVE_HPASS_AGNOC_AUDIO] =3D &qns_hpass_agnoc_audio, +}; + +static const struct regmap_config nord_hpass_ag_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x37080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_hpass_ag_noc =3D { + .config =3D &nord_hpass_ag_noc_regmap_config, + .nodes =3D hpass_ag_noc_nodes, + .num_nodes =3D ARRAY_SIZE(hpass_ag_noc_nodes), +}; + +static struct qcom_icc_bcm * const hscnoc_bcms[] =3D { + &bcm_sh0, + &bcm_sh1, +}; + +static struct qcom_icc_node * const hscnoc_nodes[] =3D { + [MASTER_GPU_TCU] =3D &alm_gpu_tcu, + [MASTER_QTC_TCU] =3D &alm_qtc, + [MASTER_SYS_TCU_0] =3D &alm_sys_tcu0, + [MASTER_SYS_TCU_1] =3D &alm_sys_tcu1, + [MASTER_SYS_TCU_2] =3D &alm_sys_tcu2, + [MASTER_APPSS_PROC] =3D &chm_apps, + [MASTER_A1NOC_TILE_HSCNOC] =3D &qnm_aggre_north, + [MASTER_A2NOC_TILE_HSCNOC] =3D &qnm_aggre_south, + [MASTER_GFX3D] =3D &qnm_gpu0, + [MASTER_GFX3D_1] =3D &qnm_gpu1, + [MASTER_HPASS_ADAS_HSCNOC] =3D &qnm_hpass_adas_hscnoc, + [MASTER_HPASS_AUDIO_HSCNOC] =3D &qnm_hpass_audio_hscnoc, + [MASTER_MNOC_HF_MEM_NOC] =3D &qnm_mnoc_hf, + [MASTER_MNOC_SF_MEM_NOC] =3D &qnm_mnoc_sf, + [MASTER_NSP0_HSCNOC] =3D &qnm_nsp0_hscnoc, + [MASTER_NSP1_HSCNOC] =3D &qnm_nsp1_hscnoc, + [MASTER_NSP2_HSCNOC] =3D &qnm_nsp2_hscnoc, + [MASTER_NSP3_HSCNOC] =3D &qnm_nsp3_hscnoc, + [MASTER_ANOC_PCIE_GEM_NOC] =3D &qnm_pcie, + [MASTER_SAILSS_MD0_HSCNOC] =3D &qnm_sailss_md0_hscnoc, + [MASTER_SNOC_SF_MEM_NOC] =3D &qnm_snoc_sf, + [MASTER_GIC] =3D &xm_gic, + [SLAVE_HSCNOC_CNOC] =3D &qns_hscnoc_cnoc, + [SLAVE_LLCC] =3D &qns_llcc, + [SLAVE_MEM_NOC_PCIE_SNOC] =3D &qns_pcie, +}; + +static const struct regmap_config nord_hscnoc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x45080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_hscnoc =3D { + .config =3D &nord_hscnoc_regmap_config, + .nodes =3D hscnoc_nodes, + .num_nodes =3D ARRAY_SIZE(hscnoc_nodes), + .bcms =3D hscnoc_bcms, + .num_bcms =3D ARRAY_SIZE(hscnoc_bcms), +}; + +static struct qcom_icc_bcm * const mc_virt_bcms[] =3D { + &bcm_mc0, +}; + +static struct qcom_icc_node * const mc_virt_nodes[] =3D { + [MASTER_LLCC] =3D &llcc_mc, + [SLAVE_EBI1] =3D &ebi, +}; + +static const struct qcom_icc_desc nord_mc_virt =3D { + .nodes =3D mc_virt_nodes, + .num_nodes =3D ARRAY_SIZE(mc_virt_nodes), + .bcms =3D mc_virt_bcms, + .num_bcms =3D ARRAY_SIZE(mc_virt_bcms), +}; + +static struct qcom_icc_bcm * const mmss_noc_bcms[] =3D { + &bcm_mm0, + &bcm_mm1, +}; + +static struct qcom_icc_node * const mmss_noc_nodes[] =3D { + [MASTER_CAMNOC_HF] =3D &qnm_camnoc_hf, + [MASTER_CAMNOC_NRT_ICP_SF] =3D &qnm_camnoc_nrt_icp_sf, + [MASTER_CAMNOC_RT_CDM_SF] =3D &qnm_camnoc_rt_cdm_sf, + [MASTER_CAMNOC_SF] =3D &qnm_camnoc_sf, + [MASTER_DPRX0] =3D &qnm_dprx0, + [MASTER_DPRX1] =3D &qnm_dprx1, + [MASTER_MDP0] =3D &qnm_mdp0, + [MASTER_MDP1] =3D &qnm_mdp1, + [MASTER_VIDEO_CV_PROC] =3D &qnm_video_cv_cpu, + [MASTER_VIDEO_EVA] =3D &qnm_video_eva, + [MASTER_VIDEO_MVP0] =3D &qnm_video_mvp0, + [MASTER_VIDEO_MVP1] =3D &qnm_video_mvp1, + [MASTER_VIDEO_V_PROC] =3D &qnm_video_v_cpu, + [SLAVE_MNOC_HF_MEM_NOC] =3D &qns_mem_noc_hf, + [SLAVE_MNOC_SF_MEM_NOC] =3D &qns_mem_noc_sf, +}; + +static const struct regmap_config nord_mmss_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x72800, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_mmss_noc =3D { + .config =3D &nord_mmss_noc_regmap_config, + .nodes =3D mmss_noc_nodes, + .num_nodes =3D ARRAY_SIZE(mmss_noc_nodes), + .bcms =3D mmss_noc_bcms, + .num_bcms =3D ARRAY_SIZE(mmss_noc_bcms), +}; + +static struct qcom_icc_bcm * const nsp_data_noc_0_bcms[] =3D { + &bcm_c0n0, +}; + +static struct qcom_icc_node * const nsp_data_noc_0_nodes[] =3D { + [MASTER_NSP0_PROC] =3D &qnm_nsp_data00, + [SLAVE_NSP0_HSC_NOC] =3D &qns_nsp0_hsc_noc, +}; + +static const struct regmap_config nord_nsp_data_noc_0_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x2a200, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_nsp_data_noc_0 =3D { + .config =3D &nord_nsp_data_noc_0_regmap_config, + .nodes =3D nsp_data_noc_0_nodes, + .num_nodes =3D ARRAY_SIZE(nsp_data_noc_0_nodes), + .bcms =3D nsp_data_noc_0_bcms, + .num_bcms =3D ARRAY_SIZE(nsp_data_noc_0_bcms), +}; + +static struct qcom_icc_bcm * const nsp_data_noc_1_bcms[] =3D { + &bcm_c1n0, +}; + +static struct qcom_icc_node * const nsp_data_noc_1_nodes[] =3D { + [MASTER_NSP1_PROC] =3D &qnm_nsp_data01, + [SLAVE_NSP1_HSC_NOC] =3D &qns_nsp1_hsc_noc, +}; + +static const struct regmap_config nord_nsp_data_noc_1_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x2a200, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_nsp_data_noc_1 =3D { + .config =3D &nord_nsp_data_noc_1_regmap_config, + .nodes =3D nsp_data_noc_1_nodes, + .num_nodes =3D ARRAY_SIZE(nsp_data_noc_1_nodes), + .bcms =3D nsp_data_noc_1_bcms, + .num_bcms =3D ARRAY_SIZE(nsp_data_noc_1_bcms), +}; + +static struct qcom_icc_bcm * const nsp_data_noc_2_bcms[] =3D { + &bcm_c2n0, +}; + +static struct qcom_icc_node * const nsp_data_noc_2_nodes[] =3D { + [MASTER_NSP2_PROC] =3D &qnm_nsp_data02, + [SLAVE_NSP2_HSC_NOC] =3D &qns_nsp2_hsc_noc, +}; + +static const struct regmap_config nord_nsp_data_noc_2_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x2a200, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_nsp_data_noc_2 =3D { + .config =3D &nord_nsp_data_noc_2_regmap_config, + .nodes =3D nsp_data_noc_2_nodes, + .num_nodes =3D ARRAY_SIZE(nsp_data_noc_2_nodes), + .bcms =3D nsp_data_noc_2_bcms, + .num_bcms =3D ARRAY_SIZE(nsp_data_noc_2_bcms), +}; + +static struct qcom_icc_bcm * const nsp_data_noc_3_bcms[] =3D { + &bcm_c3n0, +}; + +static struct qcom_icc_node * const nsp_data_noc_3_nodes[] =3D { + [MASTER_NSP3_PROC] =3D &qnm_nsp_data03, + [SLAVE_NSP3_HSC_NOC] =3D &qns_nsp3_hsc_noc, +}; + +static const struct regmap_config nord_nsp_data_noc_3_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x2a200, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_nsp_data_noc_3 =3D { + .config =3D &nord_nsp_data_noc_3_regmap_config, + .nodes =3D nsp_data_noc_3_nodes, + .num_nodes =3D ARRAY_SIZE(nsp_data_noc_3_nodes), + .bcms =3D nsp_data_noc_3_bcms, + .num_bcms =3D ARRAY_SIZE(nsp_data_noc_3_bcms), +}; + +static struct qcom_icc_node * const pcie_cfg_nodes[] =3D { + [MASTER_PCIE_NOC_CFG] =3D &qsm_pcie_noc_cfg, + [SLAVE_PCIE_AHB2PHY_CFG] =3D &qhs_pcie_ahb2phy_cfg, + [SLAVE_PCIE_CFG_0] =3D &qhs_pcie_cfg_0, + [SLAVE_PCIE_CFG_1] =3D &qhs_pcie_cfg_1, + [SLAVE_PCIE_CFG_2] =3D &qhs_pcie_cfg_2, + [SLAVE_PCIE_CFG_3] =3D &qhs_pcie_cfg_3, + [SLAVE_PCIE_DMA_0_CFG] =3D &qhs_pcie_dma_0_cfg, + [SLAVE_PCIE_DMA_1_CFG] =3D &qhs_pcie_dma_1_cfg, + [SLAVE_PCIE_DMA_2_CFG] =3D &qhs_pcie_dma_2_cfg, +}; + +static const struct regmap_config nord_pcie_cfg_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x7200, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_pcie_cfg =3D { + .config =3D &nord_pcie_cfg_regmap_config, + .nodes =3D pcie_cfg_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_cfg_nodes), +}; + +static struct qcom_icc_bcm * const pcie_data_inbound_bcms[] =3D { + &bcm_sn1, +}; + +static struct qcom_icc_node * const pcie_data_inbound_nodes[] =3D { + [MASTER_PCIE_DMA_0] =3D &qxm_pcie_dma_0, + [MASTER_PCIE_DMA_1] =3D &qxm_pcie_dma_1, + [MASTER_PCIE_DMA_2] =3D &qxm_pcie_dma_2, + [MASTER_PCIE_0] =3D &xm_pcie_0, + [MASTER_PCIE_1] =3D &xm_pcie_1, + [MASTER_PCIE_2] =3D &xm_pcie_2, + [MASTER_PCIE_3] =3D &xm_pcie_3, + [SLAVE_PCIE_HSCNOC] =3D &qns_pcie_hscnoc, + [SLAVE_PCIE_OBNOC_DMA] =3D &qns_pcie_obnoc_dma, +}; + +static const struct regmap_config nord_pcie_data_inbound_regmap_config =3D= { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x4b080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_pcie_data_inbound =3D { + .config =3D &nord_pcie_data_inbound_regmap_config, + .nodes =3D pcie_data_inbound_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_data_inbound_nodes), + .bcms =3D pcie_data_inbound_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_data_inbound_bcms), +}; + +static struct qcom_icc_bcm * const pcie_data_outbound_bcms[] =3D { + &bcm_cn0, +}; + +static struct qcom_icc_node * const pcie_data_outbound_nodes[] =3D { + [MASTER_CNOC_PCIE_DMA] =3D &qnm_cnoc_pcie_dma, + [MASTER_ANOC_PCIE_HSCNOC] =3D &qnm_hscnoc_pcie, + [MASTER_PCIE_IBNOC_DMA] =3D &qnm_pcie_ibnoc_dma, + [SLAVE_PCIE_DMA_0] =3D &qxs_pcie_dma_0, + [SLAVE_PCIE_DMA_1] =3D &qxs_pcie_dma_1, + [SLAVE_PCIE_DMA_2] =3D &qxs_pcie_dma_2, + [SLAVE_PCIE_0] =3D &xs_pcie_0, + [SLAVE_PCIE_1] =3D &xs_pcie_1, + [SLAVE_PCIE_2] =3D &xs_pcie_2, + [SLAVE_PCIE_3] =3D &xs_pcie_3, +}; + +static const struct regmap_config nord_pcie_data_outbound_regmap_config = =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x17000, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_pcie_data_outbound =3D { + .config =3D &nord_pcie_data_outbound_regmap_config, + .nodes =3D pcie_data_outbound_nodes, + .num_nodes =3D ARRAY_SIZE(pcie_data_outbound_nodes), + .bcms =3D pcie_data_outbound_bcms, + .num_bcms =3D ARRAY_SIZE(pcie_data_outbound_bcms), +}; + +static struct qcom_icc_bcm * const system_noc_bcms[] =3D { + &bcm_sn0, + &bcm_sn1, + &bcm_sn2, + &bcm_sn3, +}; + +static struct qcom_icc_node * const system_noc_nodes[] =3D { + [MASTER_A1NOC_SNOC] =3D &qnm_aggre1_noc, + [MASTER_A2NOC_SNOC] =3D &qnm_aggre2_noc, + [MASTER_CNOC_SNOC] =3D &qnm_cnoc_data, + [MASTER_NSINOC_SNOC] =3D &qnm_nsi_noc, + [MASTER_SAFE_DMA] =3D &qnm_safe_dma, + [SLAVE_SNOC_HSCNOC_SF] =3D &qns_hscnoc_sf, +}; + +static const struct regmap_config nord_system_noc_regmap_config =3D { + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .max_register =3D 0x1c080, + .fast_io =3D true, +}; + +static const struct qcom_icc_desc nord_system_noc =3D { + .config =3D &nord_system_noc_regmap_config, + .nodes =3D system_noc_nodes, + .num_nodes =3D ARRAY_SIZE(system_noc_nodes), + .bcms =3D system_noc_bcms, + .num_bcms =3D ARRAY_SIZE(system_noc_bcms), +}; + +static const struct of_device_id qnoc_of_match[] =3D { + { .compatible =3D "qcom,nord-aggre1-noc", .data =3D &nord_aggre1_noc }, + { .compatible =3D "qcom,nord-aggre1-noc-tile", .data =3D &nord_aggre1_noc= _tile }, + { .compatible =3D "qcom,nord-aggre2-noc", .data =3D &nord_aggre2_noc }, + { .compatible =3D "qcom,nord-aggre2-noc-tile", .data =3D &nord_aggre2_noc= _tile }, + { .compatible =3D "qcom,nord-clk-virt", .data =3D &nord_clk_virt }, + { .compatible =3D "qcom,nord-cnoc-cfg", .data =3D &nord_cnoc_cfg }, + { .compatible =3D "qcom,nord-cnoc-main", .data =3D &nord_cnoc_main }, + { .compatible =3D "qcom,nord-hpass-ag-noc", .data =3D &nord_hpass_ag_noc = }, + { .compatible =3D "qcom,nord-hscnoc", .data =3D &nord_hscnoc }, + { .compatible =3D "qcom,nord-mc-virt", .data =3D &nord_mc_virt }, + { .compatible =3D "qcom,nord-mmss-noc", .data =3D &nord_mmss_noc }, + { .compatible =3D "qcom,nord-nsp-data-noc-0", .data =3D &nord_nsp_data_no= c_0 }, + { .compatible =3D "qcom,nord-nsp-data-noc-1", .data =3D &nord_nsp_data_no= c_1 }, + { .compatible =3D "qcom,nord-nsp-data-noc-2", .data =3D &nord_nsp_data_no= c_2 }, + { .compatible =3D "qcom,nord-nsp-data-noc-3", .data =3D &nord_nsp_data_no= c_3 }, + { .compatible =3D "qcom,nord-pcie-cfg", .data =3D &nord_pcie_cfg }, + { .compatible =3D "qcom,nord-pcie-data-inbound", .data =3D &nord_pcie_dat= a_inbound }, + { .compatible =3D "qcom,nord-pcie-data-outbound", .data =3D &nord_pcie_da= ta_outbound }, + { .compatible =3D "qcom,nord-system-noc", .data =3D &nord_system_noc }, + { } +}; +MODULE_DEVICE_TABLE(of, qnoc_of_match); + +static struct platform_driver qnoc_driver =3D { + .probe =3D qcom_icc_rpmh_probe, + .remove =3D qcom_icc_rpmh_remove, + .driver =3D { + .name =3D "qnoc-nord", + .of_match_table =3D qnoc_of_match, + .sync_state =3D icc_sync_state, + }, +}; + +static int __init qnoc_driver_init(void) +{ + return platform_driver_register(&qnoc_driver); +} +core_initcall(qnoc_driver_init); + +static void __exit qnoc_driver_exit(void) +{ + platform_driver_unregister(&qnoc_driver); +} +module_exit(qnoc_driver_exit); + +MODULE_DESCRIPTION("Qualcomm Nord NoC driver"); +MODULE_LICENSE("GPL"); --=20 2.43.0