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The vdda-qreftx*, vdda-qrefrpt*, and vdda-qrefrx* supplies map to common QREF TX/RPT/RX components, while SoC-specific topology and instance count differ. Document them here for qcom,glymur-tcsr. Signed-off-by: Qiang Yu --- .../bindings/clock/qcom,sm8550-tcsr.yaml | 40 ++++++++++++++++++= ++++ 1 file changed, 40 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml = b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 1ccdf4b0f5dd..0cf612e6d7ee 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -51,6 +51,46 @@ properties: '#reset-cells': const: 1 =20 + vdda-refgen-0p9-supply: true + vdda-refgen-1p2-supply: true + vdda-qrefrx0-0p9-supply: true + vdda-qrefrx1-0p9-supply: true + vdda-qrefrx2-0p9-supply: true + vdda-qrefrx4-0p9-supply: true + vdda-qrefrx5-0p9-supply: true + vdda-qreftx0-0p9-supply: true + vdda-qreftx0-1p2-supply: true + vdda-qreftx1-0p9-supply: true + vdda-qrefrpt0-0p9-supply: true + vdda-qrefrpt1-0p9-supply: true + vdda-qrefrpt2-0p9-supply: true + vdda-qrefrpt3-0p9-supply: true + vdda-qrefrpt4-0p9-supply: true + +allOf: + - if: + properties: + compatible: + contains: + const: qcom,glymur-tcsr + else: + properties: + vdda-refgen-0p9-supply: false + vdda-refgen-1p2-supply: false + vdda-qrefrx0-0p9-supply: false + vdda-qrefrx1-0p9-supply: false + vdda-qrefrx2-0p9-supply: false + vdda-qrefrx4-0p9-supply: false + vdda-qrefrx5-0p9-supply: false + vdda-qreftx0-0p9-supply: false + vdda-qreftx0-1p2-supply: false + vdda-qreftx1-0p9-supply: false + vdda-qrefrpt0-0p9-supply: false + vdda-qrefrpt1-0p9-supply: false + vdda-qrefrpt2-0p9-supply: false + vdda-qrefrpt3-0p9-supply: false + vdda-qrefrpt4-0p9-supply: false + required: - compatible - clocks --=20 2.34.1 From nobody Tue Jun 16 12:49:08 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8696D38553D for ; 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QREF is powered by dedicated LDO rails, and the clkref_en register controls whether refclk is gated through to the PHY side. These clkref controls are different from typical GCC branch clocks: - only a single enable bit is present, without branch-style config bits - regulators must be voted before enable and unvoted after disable Model this as a dedicated clk_ref clock type with custom clk_ops instead of reusing struct clk_branch semantics. Also provide a common registration/probe API so the same clkref model can be reused regardless of where clkref_en registers are placed, e.g. TCSR on glymur and TLMM on SM8750. Signed-off-by: Qiang Yu --- drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-ref.c | 202 +++++++++++++++++++++++++++++++++++++++++= ++++ include/linux/clk/qcom.h | 69 ++++++++++++++++ 3 files changed, 272 insertions(+) diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 89d07c35e4d9..1659e9d9afa9 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -8,6 +8,7 @@ clk-qcom-y +=3D clk-pll.o clk-qcom-y +=3D clk-rcg.o clk-qcom-y +=3D clk-rcg2.o clk-qcom-y +=3D clk-branch.o +clk-qcom-y +=3D clk-ref.o clk-qcom-y +=3D clk-regmap-divider.o clk-qcom-y +=3D clk-regmap-mux.o clk-qcom-y +=3D clk-regmap-mux-div.o diff --git a/drivers/clk/qcom/clk-ref.c b/drivers/clk/qcom/clk-ref.c new file mode 100644 index 000000000000..ea2ed03460f2 --- /dev/null +++ b/drivers/clk/qcom/clk-ref.c @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define QCOM_CLK_REF_EN_MASK BIT(0) + +struct qcom_clk_ref_provider { + struct qcom_clk_ref *refs; + size_t num_refs; +}; + +static inline struct qcom_clk_ref *to_qcom_clk_ref(struct clk_hw *hw) +{ + return container_of(hw, struct qcom_clk_ref, hw); +} + +static const struct clk_parent_data qcom_clk_ref_parent_data =3D { + .index =3D 0, +}; + +static int qcom_clk_ref_prepare(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + int ret; + + if (!rclk->desc.num_regulators) + return 0; + + ret =3D regulator_bulk_enable(rclk->desc.num_regulators, rclk->regulators= ); + if (ret) + pr_err("Failed to enable regulators for %s: %d\n", + clk_hw_get_name(hw), ret); + + return ret; +} + +static void qcom_clk_ref_unprepare(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + + if (rclk->desc.num_regulators) + regulator_bulk_disable(rclk->desc.num_regulators, rclk->regulators); +} + +static int qcom_clk_ref_enable(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + int ret; + + ret =3D regmap_update_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_= EN_MASK, + QCOM_CLK_REF_EN_MASK); + if (ret) + return ret; + + udelay(10); + + return 0; +} + +static void qcom_clk_ref_disable(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + + regmap_update_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_MASK,= 0); + udelay(10); +} + +static int qcom_clk_ref_is_enabled(struct clk_hw *hw) +{ + struct qcom_clk_ref *rclk =3D to_qcom_clk_ref(hw); + u32 val; + int ret; + + ret =3D regmap_read(rclk->regmap, rclk->desc.offset, &val); + if (ret) + return ret; + + return !!(val & QCOM_CLK_REF_EN_MASK); +} + +static const struct clk_ops qcom_clk_ref_ops =3D { + .prepare =3D qcom_clk_ref_prepare, + .unprepare =3D qcom_clk_ref_unprepare, + .enable =3D qcom_clk_ref_enable, + .disable =3D qcom_clk_ref_disable, + .is_enabled =3D qcom_clk_ref_is_enabled, +}; + +static int qcom_clk_ref_register(struct device *dev, struct regmap *regmap, + struct qcom_clk_ref *clk_refs, + const struct qcom_clk_ref_desc *descs, + size_t num_clk_refs) +{ + const struct qcom_clk_ref_desc *desc; + struct qcom_clk_ref *clk_ref; + size_t clk_idx; + unsigned int i; + int ret; + + for (clk_idx =3D 0; clk_idx < num_clk_refs; clk_idx++) { + clk_ref =3D &clk_refs[clk_idx]; + desc =3D &descs[clk_idx]; + + if (!desc->name) + return -EINVAL; + + clk_ref->regmap =3D regmap; + clk_ref->desc =3D *desc; + + if (clk_ref->desc.num_regulators) { + clk_ref->regulators =3D devm_kcalloc(dev, clk_ref->desc.num_regulators, + sizeof(*clk_ref->regulators), + GFP_KERNEL); + if (!clk_ref->regulators) + return -ENOMEM; + + for (i =3D 0; i < clk_ref->desc.num_regulators; i++) + clk_ref->regulators[i].supply =3D + clk_ref->desc.regulator_names[i]; + + ret =3D devm_regulator_bulk_get(dev, clk_ref->desc.num_regulators, + clk_ref->regulators); + if (ret) + return dev_err_probe(dev, ret, + "Failed to get regulators for %s\n", + clk_ref->desc.name); + } + + clk_ref->init_data.name =3D clk_ref->desc.name; + clk_ref->init_data.parent_data =3D &qcom_clk_ref_parent_data; + clk_ref->init_data.num_parents =3D 1; + clk_ref->init_data.ops =3D &qcom_clk_ref_ops; + clk_ref->hw.init =3D &clk_ref->init_data; + + ret =3D devm_clk_hw_register(dev, &clk_ref->hw); + if (ret) + return ret; + } + + return 0; +} + +static struct clk_hw *qcom_clk_ref_provider_get(struct of_phandle_args *cl= kspec, void *data) +{ + struct qcom_clk_ref_provider *provider =3D data; + unsigned int idx =3D clkspec->args[0]; + + if (idx >=3D provider->num_refs) + return ERR_PTR(-EINVAL); + + return &provider->refs[idx].hw; +} + +int qcom_clk_ref_probe(struct platform_device *pdev, + const struct regmap_config *config, + const struct qcom_clk_ref_desc *descs, + size_t num_clk_refs) +{ + struct qcom_clk_ref_provider *provider; + struct device *dev =3D &pdev->dev; + struct regmap *regmap; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap =3D devm_regmap_init_mmio(dev, base, config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + provider =3D devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL); + if (!provider) + return -ENOMEM; + + provider->refs =3D devm_kcalloc(dev, num_clk_refs, sizeof(*provider->refs= ), + GFP_KERNEL); + if (!provider->refs) + return -ENOMEM; + + provider->num_refs =3D num_clk_refs; + + ret =3D qcom_clk_ref_register(dev, regmap, provider->refs, descs, + provider->num_refs); + if (ret) + return ret; + + return devm_of_clk_add_hw_provider(dev, qcom_clk_ref_provider_get, provid= er); +} +EXPORT_SYMBOL_GPL(qcom_clk_ref_probe); diff --git a/include/linux/clk/qcom.h b/include/linux/clk/qcom.h new file mode 100644 index 000000000000..09e2e3178cfb --- /dev/null +++ b/include/linux/clk/qcom.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#ifndef __LINUX_CLK_QCOM_H +#define __LINUX_CLK_QCOM_H + +#include +#include +#include +#include +#include + +struct device; +struct platform_device; +struct regulator_bulk_data; + +/** + * struct qcom_clk_ref_desc - descriptor for a clkref_en gate clock + * @name: clock name exposed to the common clock framework + * @offset: clkref_en register offset from the block base + * @regulator_names: optional supply names enabled while preparing the clo= ck + * @num_regulators: number of entries in @regulator_names + */ +struct qcom_clk_ref_desc { + const char *name; + u32 offset; + const char * const *regulator_names; + unsigned int num_regulators; +}; + +/** + * struct qcom_clk_ref - per-clock data for a clkref_en gate clock + * @hw: common clock framework hardware clock handle + * @init_data: common clock framework registration data + * @regmap: register map backing the clkref_en register + * @desc: clock descriptor copied at registration time + * @regulators: optional bulk regulator handles for @desc.regulator_names + */ +struct qcom_clk_ref { + struct clk_hw hw; + struct clk_init_data init_data; + struct regmap *regmap; + struct qcom_clk_ref_desc desc; + struct regulator_bulk_data *regulators; +}; + +#if IS_ENABLED(CONFIG_COMMON_CLK_QCOM) + +int qcom_clk_ref_probe(struct platform_device *pdev, + const struct regmap_config *config, + const struct qcom_clk_ref_desc *descs, + size_t num_clk_refs); + +#else + +static inline int +qcom_clk_ref_probe(struct platform_device *pdev, + const struct regmap_config *config, + const struct qcom_clk_ref_desc *descs, + size_t num_clk_refs) +{ + return -EOPNOTSUPP; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12c74a18a2bsm19866217c88.10.2026.04.20.00.42.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2026 00:42:56 -0700 (PDT) From: Qiang Yu Date: Mon, 20 Apr 2026 00:42:54 -0700 Subject: [PATCH v2 3/4] clk: qcom: tcsrcc-glymur: Migrate tcsr_pcie_N_clkref_en to clk_ref common helper Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260420-vote_qref_in_tcsrcc-v2-3-589a23ae640a@oss.qualcomm.com> References: <20260420-vote_qref_in_tcsrcc-v2-0-589a23ae640a@oss.qualcomm.com> In-Reply-To: <20260420-vote_qref_in_tcsrcc-v2-0-589a23ae640a@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776670973; l=11221; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=n1rUnxUioBDy/pkAI4pH6mkjd2iZyXulJZo7i6Vdk14=; b=kWesH7qPV0S0hmGEv/0h6mEmcPwxiRR4wBd++9oc9n8gPw5oz7nwkxYbDEkxwN3FBFjOXYZyb qV6GY0Hppw7DRQqixs8FdityoS8c6Ip5o2h5/C0DpVwvK1OdZaUcuWX X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=GthyPE1C c=1 sm=1 tr=0 ts=69e5d902 cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=t2MV0Cpg_TU8-8Jkrg8A:9 a=QEXdDO2ut3YA:10 a=vBUdepa8ALXHeOFLBtFW:22 X-Proofpoint-GUID: et4T2bX_SSlXKYalD0ZUEQt-r3Zw0EE7 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIwMDA3NCBTYWx0ZWRfXwITHOAOqcfS+ IoqXiVfy9CDu7hVvKwNxJ0k2f2phtcRfSfWg21btXdnLdiO3VBbMSLcMPeXhQGP1GQqlaPPOd2u TioNZHQlwdCs3h+v4mRiM5GRjUOI+2w80lhFw6CXbHaoOFr3Gkom+hzGNZe6acICKzF69KcL80I Tr5JWsnKe3lBLpbpjQLcLNo27HjqtABjAwD6OQgf3dcfdyCZ5U7r7pobOYxp0uYGD1n2DihmhjS 4CMZ8fBVPgIqWmXZ9LdyqdLM2myc2gf0knRtSLLkAxb6NC4WJvU/jBvymgZ5JUfZfTACsucaVCd yPEUnGkKDIIGv8FryQRXC3lhZb33qGu6zVquBHslyOSbP4U3cjj2qL4eMxE2zvqy4OGur5PGaKi KZbM6fDOAvp0tGhoKnHoWgV+DJZ/vyHbmjTB+vpDEwv7hKxzB9JqSM5kfcIPy3GQmJQuBH1zI2h OghaWx50dbhE0UykzyQ== X-Proofpoint-ORIG-GUID: et4T2bX_SSlXKYalD0ZUEQt-r3Zw0EE7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-20_01,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 spamscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604200074 Replace local clk_branch-based clkref definitions with descriptor-based registration via qcom_clk_ref_probe(). This keeps the glymur driver focused on clock metadata and reuses common runtime logic for regulator handling, enable/disable sequencing, and OF provider wiring. Signed-off-by: Qiang Yu --- drivers/clk/qcom/tcsrcc-glymur.c | 340 +++++++++++------------------------= ---- 1 file changed, 93 insertions(+), 247 deletions(-) diff --git a/drivers/clk/qcom/tcsrcc-glymur.c b/drivers/clk/qcom/tcsrcc-gly= mur.c index 9c0edebcdbb1..585f87b23af2 100644 --- a/drivers/clk/qcom/tcsrcc-glymur.c +++ b/drivers/clk/qcom/tcsrcc-glymur.c @@ -4,265 +4,115 @@ */ =20 #include +#include #include #include +#include #include #include =20 #include =20 -#include "clk-alpha-pll.h" -#include "clk-branch.h" -#include "clk-pll.h" -#include "clk-rcg.h" -#include "clk-regmap.h" -#include "clk-regmap-divider.h" -#include "clk-regmap-mux.h" -#include "common.h" -#include "gdsc.h" -#include "reset.h" - -enum { - DT_BI_TCXO_PAD, -}; - -static struct clk_branch tcsr_edp_clkref_en =3D { - .halt_reg =3D 0x60, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x60, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_edp_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, +static const char * const tcsr_pcie_1_regulators[] =3D { + "vdda-refgen-0p9", + "vdda-refgen-1p2", + "vdda-qrefrx5-0p9", + "vdda-qreftx0-0p9", + "vdda-qreftx0-1p2", +}; + +static const char * const tcsr_pcie_2_regulators[] =3D { + "vdda-refgen-0p9", + "vdda-refgen-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrpt2-0p9", + "vdda-qrefrx2-0p9", +}; + +static const char * const tcsr_pcie_3_regulators[] =3D { + "vdda-refgen-0p9", + "vdda-refgen-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrx1-0p9", +}; + +static const char * const tcsr_pcie_4_regulators[] =3D { + "vdda-refgen-0p9", + "vdda-refgen-1p2", + "vdda-qreftx1-0p9", + "vdda-qrefrpt0-0p9", + "vdda-qrefrpt1-0p9", + "vdda-qrefrpt2-0p9", + "vdda-qrefrx2-0p9", +}; + +static const struct qcom_clk_ref_desc tcsr_cc_glymur_clk_descs[] =3D { + [TCSR_EDP_CLKREF_EN] =3D { + .name =3D "tcsr_edp_clkref_en", + .offset =3D 0x60, }, -}; - -static struct clk_branch tcsr_pcie_1_clkref_en =3D { - .halt_reg =3D 0x48, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x48, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_1_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_1_clkref_en", + .offset =3D 0x48, + .regulator_names =3D tcsr_pcie_1_regulators, + .num_regulators =3D ARRAY_SIZE(tcsr_pcie_1_regulators), }, -}; - -static struct clk_branch tcsr_pcie_2_clkref_en =3D { - .halt_reg =3D 0x4c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x4c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_2_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_2_clkref_en", + .offset =3D 0x4c, + .regulator_names =3D tcsr_pcie_2_regulators, + .num_regulators =3D ARRAY_SIZE(tcsr_pcie_2_regulators), }, -}; - -static struct clk_branch tcsr_pcie_3_clkref_en =3D { - .halt_reg =3D 0x54, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x54, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_3_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_3_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_3_clkref_en", + .offset =3D 0x54, + .regulator_names =3D tcsr_pcie_3_regulators, + .num_regulators =3D ARRAY_SIZE(tcsr_pcie_3_regulators), }, -}; - -static struct clk_branch tcsr_pcie_4_clkref_en =3D { - .halt_reg =3D 0x58, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x58, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_pcie_4_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_PCIE_4_CLKREF_EN] =3D { + .name =3D "tcsr_pcie_4_clkref_en", + .offset =3D 0x58, + .regulator_names =3D tcsr_pcie_4_regulators, + .num_regulators =3D ARRAY_SIZE(tcsr_pcie_4_regulators), }, -}; - -static struct clk_branch tcsr_usb2_1_clkref_en =3D { - .halt_reg =3D 0x6c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x6c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_1_clkref_en", + .offset =3D 0x6c, }, -}; - -static struct clk_branch tcsr_usb2_2_clkref_en =3D { - .halt_reg =3D 0x70, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x70, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_2_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_2_clkref_en", + .offset =3D 0x70, }, -}; - -static struct clk_branch tcsr_usb2_3_clkref_en =3D { - .halt_reg =3D 0x74, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x74, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_3_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_3_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_3_clkref_en", + .offset =3D 0x74, }, -}; - -static struct clk_branch tcsr_usb2_4_clkref_en =3D { - .halt_reg =3D 0x88, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x88, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb2_4_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB2_4_CLKREF_EN] =3D { + .name =3D "tcsr_usb2_4_clkref_en", + .offset =3D 0x88, }, -}; - -static struct clk_branch tcsr_usb3_0_clkref_en =3D { - .halt_reg =3D 0x64, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x64, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb3_0_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB3_0_CLKREF_EN] =3D { + .name =3D "tcsr_usb3_0_clkref_en", + .offset =3D 0x64, }, -}; - -static struct clk_branch tcsr_usb3_1_clkref_en =3D { - .halt_reg =3D 0x68, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x68, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb3_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB3_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb3_1_clkref_en", + .offset =3D 0x68, }, -}; - -static struct clk_branch tcsr_usb4_1_clkref_en =3D { - .halt_reg =3D 0x44, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x44, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb4_1_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB4_1_CLKREF_EN] =3D { + .name =3D "tcsr_usb4_1_clkref_en", + .offset =3D 0x44, }, -}; - -static struct clk_branch tcsr_usb4_2_clkref_en =3D { - .halt_reg =3D 0x5c, - .halt_check =3D BRANCH_HALT_DELAY, - .clkr =3D { - .enable_reg =3D 0x5c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "tcsr_usb4_2_clkref_en", - .parent_data =3D &(const struct clk_parent_data){ - .index =3D DT_BI_TCXO_PAD, - }, - .num_parents =3D 1, - .ops =3D &clk_branch2_ops, - }, + [TCSR_USB4_2_CLKREF_EN] =3D { + .name =3D "tcsr_usb4_2_clkref_en", + .offset =3D 0x5c, }, }; =20 -static struct clk_regmap *tcsr_cc_glymur_clocks[] =3D { - [TCSR_EDP_CLKREF_EN] =3D &tcsr_edp_clkref_en.clkr, - [TCSR_PCIE_1_CLKREF_EN] =3D &tcsr_pcie_1_clkref_en.clkr, - [TCSR_PCIE_2_CLKREF_EN] =3D &tcsr_pcie_2_clkref_en.clkr, - [TCSR_PCIE_3_CLKREF_EN] =3D &tcsr_pcie_3_clkref_en.clkr, - [TCSR_PCIE_4_CLKREF_EN] =3D &tcsr_pcie_4_clkref_en.clkr, - [TCSR_USB2_1_CLKREF_EN] =3D &tcsr_usb2_1_clkref_en.clkr, - [TCSR_USB2_2_CLKREF_EN] =3D &tcsr_usb2_2_clkref_en.clkr, - [TCSR_USB2_3_CLKREF_EN] =3D &tcsr_usb2_3_clkref_en.clkr, - [TCSR_USB2_4_CLKREF_EN] =3D &tcsr_usb2_4_clkref_en.clkr, - [TCSR_USB3_0_CLKREF_EN] =3D &tcsr_usb3_0_clkref_en.clkr, - [TCSR_USB3_1_CLKREF_EN] =3D &tcsr_usb3_1_clkref_en.clkr, - [TCSR_USB4_1_CLKREF_EN] =3D &tcsr_usb4_1_clkref_en.clkr, - [TCSR_USB4_2_CLKREF_EN] =3D &tcsr_usb4_2_clkref_en.clkr, -}; - static const struct regmap_config tcsr_cc_glymur_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -271,11 +121,12 @@ static const struct regmap_config tcsr_cc_glymur_regm= ap_config =3D { .fast_io =3D true, }; =20 -static const struct qcom_cc_desc tcsr_cc_glymur_desc =3D { - .config =3D &tcsr_cc_glymur_regmap_config, - .clks =3D tcsr_cc_glymur_clocks, - .num_clks =3D ARRAY_SIZE(tcsr_cc_glymur_clocks), -}; +static int tcsr_cc_glymur_probe(struct platform_device *pdev) +{ + return qcom_clk_ref_probe(pdev, &tcsr_cc_glymur_regmap_config, + tcsr_cc_glymur_clk_descs, + ARRAY_SIZE(tcsr_cc_glymur_clk_descs)); +} =20 static const struct of_device_id tcsr_cc_glymur_match_table[] =3D { { .compatible =3D "qcom,glymur-tcsr" }, @@ -283,11 +134,6 @@ static const struct of_device_id tcsr_cc_glymur_match_= table[] =3D { }; MODULE_DEVICE_TABLE(of, tcsr_cc_glymur_match_table); =20 -static int tcsr_cc_glymur_probe(struct platform_device *pdev) -{ - return qcom_cc_probe(pdev, &tcsr_cc_glymur_desc); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12c74a18a2bsm19866217c88.10.2026.04.20.00.42.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Apr 2026 00:42:57 -0700 (PDT) From: Qiang Yu Date: Mon, 20 Apr 2026 00:42:55 -0700 Subject: [PATCH v2 4/4] arm64: dts: qcom: glymur: Add QREF regulator supplies to TCSR Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260420-vote_qref_in_tcsrcc-v2-4-589a23ae640a@oss.qualcomm.com> References: <20260420-vote_qref_in_tcsrcc-v2-0-589a23ae640a@oss.qualcomm.com> In-Reply-To: <20260420-vote_qref_in_tcsrcc-v2-0-589a23ae640a@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Taniya Das , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776670973; l=1676; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=yyksNRbGKOAS3rMbPtNPWOGGGB0beDwIaP5hEkpK2Zw=; b=UjbA4bhllGno/fFkdCg/oALlowFVUfHEJ8HcU/WnxT545RvQkiHf5PCftELeaYbzb4OhkHYLD ipzY2gsIbw3DYoxY/N9Hunvs+4RwTaq/bbbOb2AX9zeHpvJP8SV1TJ/ X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=GthyPE1C c=1 sm=1 tr=0 ts=69e5d903 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=Gcy0W0cHAWauOcWtTx0A:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-GUID: oFJK6UzcA01eNpQfCFXu-BK0rSi3BhwK X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDIwMDA3NCBTYWx0ZWRfXxqMaqoWYUUi3 m+OP8M9LumYE7J6rpkmT+MPg9Nljsdk5/tRYHWZTKa5ZPMZvzdEWSP6baEcSfr53y3VXNF04i2i zNPpP1IDpYrSFjhFbDBQXvbK6KmdqNY3LmJddSfbycEsg5ipxcrc7QETwj49YoBxChKbkY6ebQw rOGZuov6zNQntZjyHzteXWhmAeaI/9bf5bvl7xUw00BzEyHa8tlCH7f5iyPYZuwB538fwUql6i0 2tnhG19M8ofBdJsgmVhmt/4fN9K/8erhCkiU/lBUn52auYjE4XFYqOjfIO9Gy69XKW7RZ4v7LaY UUbUjdlFzFvel2+csgGX/SLPfaPE0efCvJfGMengplmmhBUU9muqWc+zBoFx6yR4TwpXHtIcKUO inqHKDl1JCfqdPiccF07Swy47j+a+esyQDA/RIZ/7tFBzfp2bibjBb3LmNUyMKejwBiJstEUGWq +MQcjpvvi9ijNviyBBA== X-Proofpoint-ORIG-GUID: oFJK6UzcA01eNpQfCFXu-BK0rSi3BhwK X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-20_01,2026-04-17_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 priorityscore=1501 malwarescore=0 spamscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604200074 The TCSR clkref clocks gate the QREF block which provides reference clocks to the PCIe PHYs. Wire up the LDO supplies required by the QREF and refgen blocks on the CRD board: - vdda-refgen_0p9/1p2: LDOs for the refgen block that generates the reference voltage for QREF - vdda-qrefrx/tx/rpt: LDOs for the QREF receiver, transmitter and repeater circuits Signed-off-by: Qiang Yu --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/= qcom/glymur-crd.dts index 35aaf09e4e2b..382398e44296 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -358,6 +358,25 @@ &usb_1 { status =3D "okay"; }; =20 +&tcsr { + vdda-refgen-0p9-supply =3D <&vreg_l1f_e1_0p82>; + vdda-refgen-1p2-supply =3D <&vreg_l4f_e1_1p08>; + + vdda-qrefrx5-0p9-supply =3D <&vreg_l3f_e0_0p72>; + vdda-qreftx0-0p9-supply =3D <&vreg_l3f_e0_0p72>; + vdda-qreftx0-1p2-supply =3D <&vreg_l4h_e0_1p2>; + vdda-qrefrpt0-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt1-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt2-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrpt3-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrpt4-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qrefrx0-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx1-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx2-0p9-supply =3D <&vreg_l2f_e1_0p83>; + vdda-qrefrx4-0p9-supply =3D <&vreg_l2h_e0_0p72>; + vdda-qreftx1-0p9-supply =3D <&vreg_l1f_e1_0p82>; +}; + &usb_1_dwc3_hs { remote-endpoint =3D <&pmic_glink_hs_in1>; }; --=20 2.34.1