From nobody Tue Jun 16 10:24:48 2026 Received: from mail-43101.protonmail.ch (mail-43101.protonmail.ch [185.70.43.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 561503A5E82; Mon, 20 Apr 2026 14:28:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.70.43.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776695290; cv=none; b=p5G2TWGrVilXH6FcZ9zssD8OM3hsSQEnXkg5bZWkkhuLLt6kmmr+VOrNNmFTilkGawd3LOdyBdZVxeU211hILmHlIxIIelxzyI2SMHvWXFFQnaF/63AJhGDeleV6JIhpPU7JPPUyPUdmnCfjohySJcHTKGbO7z/sxNIJQqjrL/0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776695290; c=relaxed/simple; bh=mhsuqBnDYaNy0r1jBQ7ImxEqI134ijo5W6BiMiwFb0o=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=geQS0csqmu8EObpk5K224c6V5imWfHeKUbyqKKj+1PyjzCd7x5PmB0pw0fo379YETEX0XmkBzEnHuoS+ZqLJ6dj/jleHq67o65NcyBigPPQ4nO4Yj12iemqDUB6n+EDmYK2OJItf9wvec2yNXfHlAxcoVd7TKPCo+Wg+3gxmTUA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=PPA3xX8X; arc=none smtp.client-ip=185.70.43.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="PPA3xX8X" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1776695281; x=1776954481; bh=t1pQgxgFpCDa+wxeiNLcdVPuUfml1zmjp4HoS0YAPLA=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=PPA3xX8Xbq3gADe1O1VMbaliOrQkXO8eCFkVkJIu20J8ugh0jFHoEOphW/xbTAOaN pA53Pwm36SFWwGSWuLodjA2GtwNrdv/ecPWd04udJuqSdpjMyOx3+gZ8U0GvoLTt15 NkOpC97FMBOS9eKbCICtMd3tCggm8RPjSi7XKmrd+RxSaDqeBt8ngGEjg0zB9yuvzU 8el/DBXeLiq0s4rs+lD7NVXf8eYosf632rjgz0IL0ne3G1WlNbwYV4UNAn0yAodMJH 6ryZ0xRGlk4R3c0cy0bRjvhmlPMA756Lt7lZBQVPkikvTWsm4DmDPyqD3IteDscH3p No8bTBBTMd95w== Date: Mon, 20 Apr 2026 14:27:55 +0000 To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa From: Alexander Koskovich Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Alexander Koskovich Subject: [PATCH v2 1/2] dt-bindings: pinctrl: qcom,eliza-tlmm: Update function list Message-ID: <20260420-fix-eliza-pinctrl-v2-1-b68329fd6701@pm.me> In-Reply-To: <20260420-fix-eliza-pinctrl-v2-0-b68329fd6701@pm.me> References: <20260420-fix-eliza-pinctrl-v2-0-b68329fd6701@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 33ab825d1686fd732bc5eb1ecb05ef1ac44dc102 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update the function list to include the QUPs whose lanes can have more than one GPIO option. This allows devicetrees to override the function for say, SE6 I2C SCL pin from 54 to 42. Signed-off-by: Alexander Koskovich --- .../devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml | 13 +++++++++= +--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml= b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml index 282650426487..9010226bf1a0 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml @@ -86,9 +86,16 @@ $defs: qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable, qlink_big_request, qlink_little_enable, qlink_little_request, qlink_wmss, qspi0, qspi_clk, - qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, - qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, - qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, + qspi_cs, qup1_se0, qup1_se1, qup1_se2_l0, qup1_se2_l1, + qup1_se2_l2_mira, qup1_se2_l2_mirb, qup1_se2_l3_mira, + qup1_se2_l3_mirb, qup1_se2_l4, qup1_se2_l5, qup1_se2_l6, + qup1_se3, qup1_se4, qup1_se5, qup1_se6_l0, qup1_se6_l1_mir= a, + qup1_se6_l1_mirb, qup1_se6_l2, qup1_se6_l3_mira, + qup1_se6_l3_mirb, qup1_se7_l0_mira, qup1_se7_l0_mirb, + qup1_se7_l1_mira, qup1_se7_l1_mirb, qup1_se7_l2, qup1_se7_= l3, + qup2_se0, qup2_se1, qup2_se2, qup2_se3_l0_mira, + qup2_se3_l0_mirb, qup2_se3_l1_mira, qup2_se3_l1_mirb, + qup2_se3_l2, qup2_se3_l3, qup2_se4, qup2_se5, qup2_se6, qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2, sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, --=20 2.53.0 From nobody Tue Jun 16 10:24:48 2026 Received: from mail-244121.protonmail.ch (mail-244121.protonmail.ch [109.224.244.121]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 387EA3D1CC5; Mon, 20 Apr 2026 14:28:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=109.224.244.121 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776695299; cv=none; b=RLRkF68N8hr1qV5nvDFcpcLbNAL1Owr2hXi3c9vsAoImzWC4eJFWBsuDEsenV1zqKIsB+7do+9G7OuyVOxIx4zouqWSx2uGeMSZ3rw7AWAQBsPtSnAaiu4zeYqxQDEUedrdtcbPD8+ZHQTT/e91421ILo8a1ZkQgqdX9cT1+EbI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776695299; c=relaxed/simple; bh=9tLbAL/IkJ8RXG3NKCcoFK7v5tgajuxUZOxxl45bQkw=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=e+CFHx2mpXjubuDO+wifjEV+FM1ixBX+4F9mkerxlJ1tGIP2MNQvHMC/0iqMZoHgi5F2+zaM7M7pDW6mFQmV4h4N/AT+jdmT+kaGWeTA0rmyJG+VY+B4cxxM+dGx7jqVHDcz7V256RoKtyfjIXnz91l4eMzlegqNz6bwdfkVneY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me; spf=pass smtp.mailfrom=pm.me; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b=VyICU1GJ; arc=none smtp.client-ip=109.224.244.121 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=pm.me Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pm.me Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=pm.me header.i=@pm.me header.b="VyICU1GJ" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pm.me; s=protonmail3; t=1776695289; x=1776954489; bh=9tLbAL/IkJ8RXG3NKCcoFK7v5tgajuxUZOxxl45bQkw=; h=Date:To:From:Cc:Subject:Message-ID:In-Reply-To:References: Feedback-ID:From:To:Cc:Date:Subject:Reply-To:Feedback-ID: Message-ID:BIMI-Selector; b=VyICU1GJvjK/5vXjR/YBEZDqfpfOpG4BBXTAD9X6a7UdyoXGwmqi26e45zuxngyd7 oksq9WfdOl/gKg+EhmcCKNilCTrMBFsQdpggmk288VdAnYEz6nAZX7SN/8reNrZ+BO CTnyZ5Mbg8py+06oZ+P22BWRgqBYa8gRDAa7Zidrojtoxn6nYXu3nLYe/QICKm1EVQ Rsr4IBNusLiVdR4Wx8uUjsFRQ+8UNZmA2pp1gdJMUad/JZD8gLRzvdWzWPDQLbWXbp knwXbLcCS/i1fwVJF6WQgJFJ7ORsq0zbaQWkVFf/H95Ow3Pbk/MczGyZhLrqkeYy9O PnhXRB4/eT/FQ== Date: Mon, 20 Apr 2026 14:28:04 +0000 To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Abel Vesa From: Alexander Koskovich Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Alexander Koskovich Subject: [PATCH v2 2/2] pinctrl: qcom: eliza: Split up some QUP pin groups Message-ID: <20260420-fix-eliza-pinctrl-v2-2-b68329fd6701@pm.me> In-Reply-To: <20260420-fix-eliza-pinctrl-v2-0-b68329fd6701@pm.me> References: <20260420-fix-eliza-pinctrl-v2-0-b68329fd6701@pm.me> Feedback-ID: 37836894:user:proton X-Pm-Message-ID: 0b36d055a9c635361ef9d952bdef044d3e7cad8a Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Multiple QUPs have lanes that can be routed to one of two GPIOs and collapsing them prevents devicetrees from requesting specific routing. For example, a board that wires an I2C SCL line to one of two GPIOs cannot request that specific pin with the groups collapsed. This change splits them up so devicetrees can request the configuration they need. Signed-off-by: Alexander Koskovich --- drivers/pinctrl/qcom/pinctrl-eliza.c | 200 +++++++++++++++++++++++++++++--= ---- 1 file changed, 169 insertions(+), 31 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pi= nctrl-eliza.c index c1f756cbcdeb..a1365bcd3bf6 100644 --- a/drivers/pinctrl/qcom/pinctrl-eliza.c +++ b/drivers/pinctrl/qcom/pinctrl-eliza.c @@ -562,16 +562,39 @@ enum eliza_functions { msm_mux_qspi_cs, msm_mux_qup1_se0, msm_mux_qup1_se1, - msm_mux_qup1_se2, + msm_mux_qup1_se2_l0, + msm_mux_qup1_se2_l1, + msm_mux_qup1_se2_l2_mira, + msm_mux_qup1_se2_l2_mirb, + msm_mux_qup1_se2_l3_mira, + msm_mux_qup1_se2_l3_mirb, + msm_mux_qup1_se2_l4, + msm_mux_qup1_se2_l5, + msm_mux_qup1_se2_l6, msm_mux_qup1_se3, msm_mux_qup1_se4, msm_mux_qup1_se5, - msm_mux_qup1_se6, - msm_mux_qup1_se7, + msm_mux_qup1_se6_l0, + msm_mux_qup1_se6_l1_mira, + msm_mux_qup1_se6_l1_mirb, + msm_mux_qup1_se6_l2, + msm_mux_qup1_se6_l3_mira, + msm_mux_qup1_se6_l3_mirb, + msm_mux_qup1_se7_l0_mira, + msm_mux_qup1_se7_l0_mirb, + msm_mux_qup1_se7_l1_mira, + msm_mux_qup1_se7_l1_mirb, + msm_mux_qup1_se7_l2, + msm_mux_qup1_se7_l3, msm_mux_qup2_se0, msm_mux_qup2_se1, msm_mux_qup2_se2, - msm_mux_qup2_se3, + msm_mux_qup2_se3_l0_mira, + msm_mux_qup2_se3_l0_mirb, + msm_mux_qup2_se3_l1_mira, + msm_mux_qup2_se3_l1_mirb, + msm_mux_qup2_se3_l2, + msm_mux_qup2_se3_l3, msm_mux_qup2_se4, msm_mux_qup2_se5, msm_mux_qup2_se6, @@ -977,8 +1000,40 @@ static const char *const qup1_se1_groups[] =3D { "gpio32", "gpio33", "gpio34", "gpio35", }; =20 -static const char *const qup1_se2_groups[] =3D { - "gpio52", "gpio53", "gpio54", "gpio52", "gpio55", "gpio53", "gpio40", "gp= io42", "gpio30", +static const char *const qup1_se2_l0_groups[] =3D { + "gpio52", +}; + +static const char *const qup1_se2_l1_groups[] =3D { + "gpio53", +}; + +static const char *const qup1_se2_l2_mira_groups[] =3D { + "gpio54", +}; + +static const char *const qup1_se2_l2_mirb_groups[] =3D { + "gpio52", +}; + +static const char *const qup1_se2_l3_mira_groups[] =3D { + "gpio55", +}; + +static const char *const qup1_se2_l3_mirb_groups[] =3D { + "gpio53", +}; + +static const char *const qup1_se2_l4_groups[] =3D { + "gpio40", +}; + +static const char *const qup1_se2_l5_groups[] =3D { + "gpio42", +}; + +static const char *const qup1_se2_l6_groups[] =3D { + "gpio30", }; =20 static const char *const qup1_se3_groups[] =3D { @@ -993,12 +1048,52 @@ static const char *const qup1_se5_groups[] =3D { "gpio132", "gpio133", "gpio134", "gpio135", "gpio34", "gpio35", }; =20 -static const char *const qup1_se6_groups[] =3D { - "gpio40", "gpio42", "gpio54", "gpio42", "gpio40", "gpio55", +static const char *const qup1_se6_l0_groups[] =3D { + "gpio40", +}; + +static const char *const qup1_se6_l1_mira_groups[] =3D { + "gpio42", +}; + +static const char *const qup1_se6_l1_mirb_groups[] =3D { + "gpio54", +}; + +static const char *const qup1_se6_l2_groups[] =3D { + "gpio42", +}; + +static const char *const qup1_se6_l3_mira_groups[] =3D { + "gpio40", }; =20 -static const char *const qup1_se7_groups[] =3D { - "gpio81", "gpio78", "gpio80", "gpio114", "gpio114", "gpio78", +static const char *const qup1_se6_l3_mirb_groups[] =3D { + "gpio55", +}; + +static const char *const qup1_se7_l0_mira_groups[] =3D { + "gpio81", +}; + +static const char *const qup1_se7_l0_mirb_groups[] =3D { + "gpio78", +}; + +static const char *const qup1_se7_l1_mira_groups[] =3D { + "gpio80", +}; + +static const char *const qup1_se7_l1_mirb_groups[] =3D { + "gpio114", +}; + +static const char *const qup1_se7_l2_groups[] =3D { + "gpio114", +}; + +static const char *const qup1_se7_l3_groups[] =3D { + "gpio78", }; =20 static const char *const qup2_se0_groups[] =3D { @@ -1013,8 +1108,28 @@ static const char *const qup2_se2_groups[] =3D { "gpio8", "gpio9", "gpio10", "gpio11", "gpio16", "gpio17", "gpio18", }; =20 -static const char *const qup2_se3_groups[] =3D { - "gpio79", "gpio116", "gpio97", "gpio100", "gpio100", "gpio116", +static const char *const qup2_se3_l0_mira_groups[] =3D { + "gpio79", +}; + +static const char *const qup2_se3_l0_mirb_groups[] =3D { + "gpio116", +}; + +static const char *const qup2_se3_l1_mira_groups[] =3D { + "gpio97", +}; + +static const char *const qup2_se3_l1_mirb_groups[] =3D { + "gpio100", +}; + +static const char *const qup2_se3_l2_groups[] =3D { + "gpio100", +}; + +static const char *const qup2_se3_l3_groups[] =3D { + "gpio116", }; =20 static const char *const qup2_se4_groups[] =3D { @@ -1235,16 +1350,39 @@ static const struct pinfunction eliza_functions[] = =3D { MSM_PIN_FUNCTION(qspi_cs), MSM_PIN_FUNCTION(qup1_se0), MSM_PIN_FUNCTION(qup1_se1), - MSM_PIN_FUNCTION(qup1_se2), + MSM_PIN_FUNCTION(qup1_se2_l0), + MSM_PIN_FUNCTION(qup1_se2_l1), + MSM_PIN_FUNCTION(qup1_se2_l2_mira), + MSM_PIN_FUNCTION(qup1_se2_l2_mirb), + MSM_PIN_FUNCTION(qup1_se2_l3_mira), + MSM_PIN_FUNCTION(qup1_se2_l3_mirb), + MSM_PIN_FUNCTION(qup1_se2_l4), + MSM_PIN_FUNCTION(qup1_se2_l5), + MSM_PIN_FUNCTION(qup1_se2_l6), MSM_PIN_FUNCTION(qup1_se3), MSM_PIN_FUNCTION(qup1_se4), MSM_PIN_FUNCTION(qup1_se5), - MSM_PIN_FUNCTION(qup1_se6), - MSM_PIN_FUNCTION(qup1_se7), + MSM_PIN_FUNCTION(qup1_se6_l0), + MSM_PIN_FUNCTION(qup1_se6_l1_mira), + MSM_PIN_FUNCTION(qup1_se6_l1_mirb), + MSM_PIN_FUNCTION(qup1_se6_l2), + MSM_PIN_FUNCTION(qup1_se6_l3_mira), + MSM_PIN_FUNCTION(qup1_se6_l3_mirb), + MSM_PIN_FUNCTION(qup1_se7_l0_mira), + MSM_PIN_FUNCTION(qup1_se7_l0_mirb), + MSM_PIN_FUNCTION(qup1_se7_l1_mira), + MSM_PIN_FUNCTION(qup1_se7_l1_mirb), + MSM_PIN_FUNCTION(qup1_se7_l2), + MSM_PIN_FUNCTION(qup1_se7_l3), MSM_PIN_FUNCTION(qup2_se0), MSM_PIN_FUNCTION(qup2_se1), MSM_PIN_FUNCTION(qup2_se2), - MSM_PIN_FUNCTION(qup2_se3), + MSM_PIN_FUNCTION(qup2_se3_l0_mira), + MSM_PIN_FUNCTION(qup2_se3_l0_mirb), + MSM_PIN_FUNCTION(qup2_se3_l1_mira), + MSM_PIN_FUNCTION(qup2_se3_l1_mirb), + MSM_PIN_FUNCTION(qup2_se3_l2), + MSM_PIN_FUNCTION(qup2_se3_l3), MSM_PIN_FUNCTION(qup2_se4), MSM_PIN_FUNCTION(qup2_se5), MSM_PIN_FUNCTION(qup2_se6), @@ -1316,7 +1454,7 @@ static const struct msm_pingroup eliza_groups[] =3D { [27] =3D PINGROUP(27, qup2_se4, aoss_cti, mdp_vsync11_out, qup2_se7, gcc_= gp1, _, _, _, _, _, _), [28] =3D PINGROUP(28, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), [29] =3D PINGROUP(29, qup1_se0, ibi_i3c, _, _, _, _, _, _, _, _, egpio), - [30] =3D PINGROUP(30, qup1_se0, qup1_se2, cci_async_in, gcc_gp3, qdss_gpi= o_tracedata, _, _, _, _, _, egpio), + [30] =3D PINGROUP(30, qup1_se0, qup1_se2_l6, cci_async_in, gcc_gp3, qdss_= gpio_tracedata, _, _, _, _, _, egpio), [31] =3D PINGROUP(31, qup1_se0, cci_async_in, qdss_gpio_tracedata, _, _, = _, _, _, _, _, egpio), [32] =3D PINGROUP(32, qup1_se1, ibi_i3c, audio_ref_clk, gcc_gp2, qdss_cti= , _, _, _, _, _, _), [33] =3D PINGROUP(33, qup1_se1, ibi_i3c, host2wlan_sol, gcc_gp3, _, _, _,= _, _, _, _), @@ -1326,9 +1464,9 @@ static const struct msm_pingroup eliza_groups[] =3D { [37] =3D PINGROUP(37, qup1_se4, qup1_se4, ibi_i3c, _, _, _, _, _, _, _, _= ), [38] =3D PINGROUP(38, _, _, _, _, _, _, _, _, _, _, _), [39] =3D PINGROUP(39, _, _, _, _, _, _, _, _, _, _, _), - [40] =3D PINGROUP(40, qup1_se6, qup1_se2, qup1_se6, _, qdss_gpio_tracedat= a, gnss_adc1, ddr_pxi1, _, _, _, _), + [40] =3D PINGROUP(40, qup1_se6_l0, qup1_se2_l4, qup1_se6_l3_mira, _, qdss= _gpio_tracedata, gnss_adc1, ddr_pxi1, _, _, _, _), [41] =3D PINGROUP(41, _, _, _, _, _, _, _, _, _, _, _), - [42] =3D PINGROUP(42, qup1_se6, qup1_se2, qup1_se6, qdss_gpio_tracedata, = gnss_adc0, ddr_pxi1, _, _, _, _, _), + [42] =3D PINGROUP(42, qup1_se6_l2, qup1_se2_l5, qup1_se6_l1_mira, qdss_gp= io_tracedata, gnss_adc0, ddr_pxi1, _, _, _, _, _), [43] =3D PINGROUP(43, _, _, _, _, _, _, _, _, _, _, _), [44] =3D PINGROUP(44, qup1_se3, _, _, _, _, _, _, _, _, _, _), [45] =3D PINGROUP(45, qup1_se3, _, _, _, _, _, _, _, _, _, _), @@ -1338,10 +1476,10 @@ static const struct msm_pingroup eliza_groups[] =3D= { [49] =3D PINGROUP(49, _, _, _, _, _, _, _, _, _, _, _), [50] =3D PINGROUP(50, sdc2_fb_clk, _, _, _, _, _, _, _, _, _, _), [51] =3D PINGROUP(51, _, _, _, _, _, _, _, _, _, _, _), - [52] =3D PINGROUP(52, qup1_se2, pcie1_clk_req_n, qup1_se2, ddr_bist_compl= ete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _), - [53] =3D PINGROUP(53, qup1_se2, qup1_se2, gcc_gp1, ddr_bist_stop, _, qdss= _gpio_tracedata, _, _, _, _, _), - [54] =3D PINGROUP(54, qup1_se2, qup1_se6, qdss_gpio_tracedata, gnss_adc1,= atest_usb, ddr_pxi0, _, _, _, _, _), - [55] =3D PINGROUP(55, qup1_se2, dp0_hot, qup1_se6, _, gnss_adc0, atest_us= b, ddr_pxi0, _, _, _, _), + [52] =3D PINGROUP(52, qup1_se2_l0, pcie1_clk_req_n, qup1_se2_l2_mirb, ddr= _bist_complete, qdss_gpio_tracedata, _, vsense_trigger_mirnat, _, _, _, _), + [53] =3D PINGROUP(53, qup1_se2_l1, qup1_se2_l3_mirb, gcc_gp1, ddr_bist_st= op, _, qdss_gpio_tracedata, _, _, _, _, _), + [54] =3D PINGROUP(54, qup1_se2_l2_mira, qup1_se6_l1_mirb, qdss_gpio_trace= data, gnss_adc1, atest_usb, ddr_pxi0, _, _, _, _, _), + [55] =3D PINGROUP(55, qup1_se2_l3_mira, dp0_hot, qup1_se6_l3_mirb, _, gns= s_adc0, atest_usb, ddr_pxi0, _, _, _, _), [56] =3D PINGROUP(56, usb0_hs, tsense_pwm1, tsense_pwm2, tsense_pwm3, tse= nse_pwm4, _, _, _, _, _, _), [57] =3D PINGROUP(57, sd_write_protect, _, _, _, _, _, _, _, _, _, _), [58] =3D PINGROUP(58, _, _, _, _, _, _, _, _, _, _, _), @@ -1364,10 +1502,10 @@ static const struct msm_pingroup eliza_groups[] =3D= { [75] =3D PINGROUP(75, cci_i2c_scl, _, phase_flag, _, _, _, _, _, _, _, _), [76] =3D PINGROUP(76, cci_i2c_sda, cci_timer, prng_rosc2, _, phase_flag, = _, _, _, _, _, _), [77] =3D PINGROUP(77, cci_i2c_scl, jitter_bist, _, _, _, _, _, _, _, _, _= ), - [78] =3D PINGROUP(78, qup1_se7, qup1_se7, _, phase_flag, _, _, _, _, _, _= , _), - [79] =3D PINGROUP(79, qspi0, mdp_vsync, qup2_se3, _, _, _, _, _, _, _, _), - [80] =3D PINGROUP(80, pcie0_clk_req_n, qup1_se7, _, phase_flag, _, _, _, = _, _, _, _), - [81] =3D PINGROUP(81, wcn_sw_ctrl, qup1_se7, dbg_out_clk, _, _, _, _, _, = _, _, _), + [78] =3D PINGROUP(78, qup1_se7_l3, qup1_se7_l0_mirb, _, phase_flag, _, _,= _, _, _, _, _), + [79] =3D PINGROUP(79, qspi0, mdp_vsync, qup2_se3_l0_mira, _, _, _, _, _, = _, _, _), + [80] =3D PINGROUP(80, pcie0_clk_req_n, qup1_se7_l1_mira, _, phase_flag, _= , _, _, _, _, _, _), + [81] =3D PINGROUP(81, wcn_sw_ctrl, qup1_se7_l0_mira, dbg_out_clk, _, _, _= , _, _, _, _, _), [82] =3D PINGROUP(82, _, _, _, _, _, _, _, _, _, _, _), [83] =3D PINGROUP(83, _, _, _, _, _, _, _, _, _, _, _), [84] =3D PINGROUP(84, uim0_data, _, _, _, _, _, _, _, _, _, _), @@ -1383,10 +1521,10 @@ static const struct msm_pingroup eliza_groups[] =3D= { [94] =3D PINGROUP(94, qlink_wmss, _, _, _, _, _, _, _, _, _, _), [95] =3D PINGROUP(95, qlink_big_request, _, _, _, _, _, _, _, _, _, _), [96] =3D PINGROUP(96, qlink_big_enable, _, _, _, _, _, _, _, _, _, _), - [97] =3D PINGROUP(97, uim1_data, qspi0, qup2_se3, _, _, _, _, _, _, _, _), + [97] =3D PINGROUP(97, uim1_data, qspi0, qup2_se3_l1_mira, _, _, _, _, _, = _, _, _), [98] =3D PINGROUP(98, uim1_clk, qspi0, _, _, _, _, _, _, _, _, _), [99] =3D PINGROUP(99, uim1_reset, qspi0, _, _, _, _, _, _, _, _, _), - [100] =3D PINGROUP(100, uim1_present, qspi0, qup2_se3, coex_uart2_tx, qup= 2_se3, mdp_vsync, _, _, _, _, _), + [100] =3D PINGROUP(100, uim1_present, qspi0, qup2_se3_l2, coex_uart2_tx, = qup2_se3_l1_mirb, mdp_vsync, _, _, _, _, _), [101] =3D PINGROUP(101, _, _, _, _, _, _, _, _, _, _, _), [102] =3D PINGROUP(102, _, _, _, _, _, _, _, _, _, _, _), [103] =3D PINGROUP(103, _, _, _, _, _, _, _, _, _, _, _), @@ -1400,9 +1538,9 @@ static const struct msm_pingroup eliza_groups[] =3D { [111] =3D PINGROUP(111, coex_uart1_tx, _, _, _, _, _, _, _, _, _, _), [112] =3D PINGROUP(112, coex_uart1_rx, _, _, _, _, _, _, _, _, _, _), [113] =3D PINGROUP(113, _, nav_gpio3, _, _, _, _, _, _, _, _, _), - [114] =3D PINGROUP(114, qup1_se7, qup1_se7, _, qdss_gpio_tracedata, _, _,= _, _, _, _, _), + [114] =3D PINGROUP(114, qup1_se7_l2, qup1_se7_l1_mirb, _, qdss_gpio_trace= data, _, _, _, _, _, _, _), [115] =3D PINGROUP(115, _, qspi0, cci_async_in, _, _, _, _, _, _, _, _), - [116] =3D PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3, qup2_se3, _, _, _= , _, _, _, _), + [116] =3D PINGROUP(116, qspi0, coex_uart2_rx, qup2_se3_l3, qup2_se3_l0_mi= rb, _, _, _, _, _, _, _), [117] =3D PINGROUP(117, nav_gpio1, _, vfr_1, _, _, _, _, _, _, _, _), [118] =3D PINGROUP(118, nav_gpio2, _, _, _, _, _, _, _, _, _, _), [119] =3D PINGROUP(119, nav_gpio0, _, _, _, _, _, _, _, _, _, _), --=20 2.53.0