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Sat, 18 Apr 2026 01:44:02 -0700 (PDT) From: Weimin Wu To: takahiro.kuwano@infineon.com Cc: tudor.ambarus@linaro.org, pratyush@kernel.org, mwalle@kernel.org, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, Weimin Wu Subject: [PATCH] [v3] mtd: spi-nor: gigadevice: Add support for GD25LQ255E Date: Sat, 18 Apr 2026 16:42:53 +0800 Message-ID: <20260418084253.792395-1-wuweimin@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the GigaDevice GD25LQ255E (JEDEC ID c8 60 19), a 256Mbit (32MB) SPI NOR flash chip which supports SFDP. The chip supports 4K sector erase, dual read, and quad read modes. Link: https://download.gigadevice.com/Datasheet/DS-00562-GD25LQ255E-Rev1.2.= pdf Without this patch, The WP status cannot be obtained using flashrom: device:/ # flashrom --wp-status ... linux_mtd_wp_read_cfg: ioctl: Operation not supported on transport endpoint Failed to get WP status: failed to read the current WP configuration and with this patch: device:/ # flashrom --wp-status ... Protection range: start=3D0x00000000 length=3D0x00000000 (none) Protection mode: disabled SUCCESS Signed-off-by: Weimin Wu Reviewed-by: Michael Walle --- Changes in v3: - Add SPI_NOR_4BIT_BP and SPI_NOR_TB_SR_BIT6 flag bits. - Add /* gd25lb256 */ comment. - Link to v2: https://patchwork.ozlabs.org/project/linux-mtd/patch/20260313= 133806.2390946-1-wuweimin@huaqin.corp-partner.google.com/ - Link to v1: https://patchwork.ozlabs.org/project/linux-mtd/patch/20260213= 144133.1778932-1-wuweimin@huaqin.corp-partner.google.com/ Refer to the following documents: https://docs.kernel.org/driver-api/mtd/spi-nor.html#minimum-testing-require= ments 1. Specify the controller that you used to test the flash and specify the f= requency at which the flash was operated: This flash memory has been successfully tested at 100Mhz frequency on a Chr= omebook device running the Intel Patherlake platform, which is currently un= der development. 2. Dump the sysfs entries and print the md5/sha1/sha256 SFDP checksum: root:/ # cat /sys/bus/spi/devices/spi0.0/spi-nor/partname cat: /sys/bus/spi/devices/spi0.0/spi-nor/partname: No such file or directory root:/ # cat /sys/bus/spi/devices/spi0.0/spi-nor/jedec_id c86019 root:/ # cat /sys/bus/spi/devices/spi0.0/spi-nor/manufacturer gigadevice root:/ # xxd -p /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 53464450070102ff00070114300000ffc8000103900000ff84010102c000 00ffffffffffffffffffffffffffffffffffe520fbffffffff0f44eb086b 083b80bbfeffffffffff00ffffff42eb0c200f5210d800ffd4299dfe84d2 14c7ec6316337a757a7507b3d55c190614ff885018010000000000008800 00000000f6f5ffffffffffffffffffffffffffffffffffff002050169ff9 7764fc8bffffffffffffffffffffffffffffffffffffffffffffffffffff ffffffffffffffffffffffffff8e00fe215cdcff root:/ # sha256sum /sys/bus/spi/devices/spi0.0/spi-nor/sfdp 09f61fe623df200d86b4ab47c48e3a13718fadbb450fcd430b3cdc49a902b1f6 /sys/bus/= spi/devices/spi0.0/spi-nor/sfdp 3. Dump debugfs data: root:/ # cat /sys/kernel/debug/spi-nor/spi0.0/capabilities Supported read modes by the flash 1S-1S-1S opcode 0x13 mode cycles 0 dummy cycles 0 1S-1S-1S (fast read) opcode 0x0c mode cycles 0 dummy cycles 8 1S-1S-2S opcode 0x3c mode cycles 0 dummy cycles 8 1S-2S-2S opcode 0xbc mode cycles 4 dummy cycles 0 1S-1S-4S opcode 0x6c mode cycles 0 dummy cycles 8 1S-4S-4S opcode 0xec mode cycles 2 dummy cycles 4 4S-4S-4S opcode 0xec mode cycles 2 dummy cycles 2 Supported page program modes by the flash 1S-1S-1S opcode 0x12 1S-1S-4S opcode 0x34 root:/ # cat /sys/kernel/debug/spi-nor/spi0.0/params name (null) id c8 60 19 c8 60 19 size 32.0 MiB write size 1 page size 256 address nbytes 4 flags HAS_SR_TB | 4B_OPCODES | HAS_4BAIT | HAS_LOCK | HAS_16BIT_SR | NO_RE= AD_CR | HAS_SR_TB_BIT6 | HAS_4BIT_BP | SOFT_RESET opcodes read 0x0c dummy cycles 8 erase 0xdc program 0x12 8D extension repeat protocols read 1S-1S-1S write 1S-1S-1S register 1S-1S-1S erase commands 21 (4.00 KiB) [1] 5c (32.0 KiB) [2] dc (64.0 KiB) [3] c7 (32.0 MiB) sector map region (in hex) | erase mask | overlaid ------------------+------------+---------- 00000000-01ffffff | [ 3] | no root:/ # cat /sys/bus/spi/devices/spi0.0/ driver/ mtd/ statistic= s/ uevent driver_override power/ subsystem/ modalias spi-nor/ supplier:= regulator:regulator.0/ root:/ # cat /sys/bus/spi/devices/spi0.0/s spi-nor/ statistics/ subsystem= / supplier:regulator:regulator.0/ root:/ # cat /sys/bus/spi/devices/spi0.0/spi-nor/ jedec_id manufacturer sfdp root:/ # cat /sys/bus/spi/devices/spi0.0/spi-nor/ 4. Use mtd-utils and verify that erase, read and page program operations wo= rk fine: Because Chromebooks lack the necessary mtd-utils directives, the correspond= ing data cannot be provided. --- --- drivers/mtd/spi-nor/gigadevice.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mtd/spi-nor/gigadevice.c b/drivers/mtd/spi-nor/gigadev= ice.c index ef1edd0ad..22a430798 100644 --- a/drivers/mtd/spi-nor/gigadevice.c +++ b/drivers/mtd/spi-nor/gigadevice.c @@ -82,6 +82,10 @@ static const struct flash_info gigadevice_nor_parts[] = =3D { .size =3D SZ_16M, .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB, .no_sfdp_flags =3D SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ, + }, { + /* gd25lb256 */ + .id =3D SNOR_ID(0xc8, 0x60, 0x19), + .flags =3D SPI_NOR_HAS_LOCK | SPI_NOR_4BIT_BP | SPI_NOR_HAS_TB | SPI_NOR= _TB_SR_BIT6, }, }; =20 --=20 2.43.0