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Fri, 17 Apr 2026 10:52:37 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH 1/3] dt-bindings: mfd: syscon: Document the LVDS_CMN syscon for the RZ/G3L Date: Fri, 17 Apr 2026 18:52:28 +0100 Message-ID: <20260417175235.224809-2-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417175235.224809-1-biju.das.jz@bp.renesas.com> References: <20260417175235.224809-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The RZ/G3{E,L} SoCs have an LVDS Common (LVDS_CMN) region which is common to all LVDS channels. The RZ/G3L has single-link, but the RZ/G3E has both single and dual-link. Use the syscon interface to access these registers for scalability. Signed-off-by: Tommaso Merciai Signed-off-by: Biju Das Acked-by: Conor Dooley --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentat= ion/devicetree/bindings/mfd/syscon.yaml index e22867088063..9c81010d5a74 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -221,6 +221,7 @@ properties: - nxp,s32g3-gpr - qcom,apq8064-mmss-sfpb - qcom,apq8064-sps-sic + - renesas,r9a08g046-lvds-cmn - rockchip,px30-qos - rockchip,rk3036-qos - rockchip,rk3066-qos --=20 2.43.0 From nobody Sat Jun 20 08:26:33 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB9BF32548B for ; Fri, 17 Apr 2026 17:52:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 17 Apr 2026 10:52:38 -0700 (PDT) Received: from biju.lan ([2a00:23c4:a758:8a01:528c:590:5bef:9bc8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488fc1c773fsm56166535e9.12.2026.04.17.10.52.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 10:52:38 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Andrzej Hajda , Neil Armstrong , Robert Foss , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Tommaso Merciai , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH 2/3] dt-bindings: display: bridge: Document Renesas RZ/G3L LVDS encoder Date: Fri, 17 Apr 2026 18:52:29 +0100 Message-ID: <20260417175235.224809-3-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417175235.224809-1-biju.das.jz@bp.renesas.com> References: <20260417175235.224809-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Document the LVDS encoder IP found on the RZ/G3L SoC. It supports single-link mode. LVDS and the DSI interface share a peripheral clock and the MIPI_DSI_PRESET_N reset signal. However, the LVDS module cannot be used at the same time as MIPI-DSI. Signed-off-by: Tommaso Merciai Signed-off-by: Biju Das Acked-by: Conor Dooley --- .../bridge/renesas,r9a08g046-lvds.yaml | 128 ++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/renesa= s,r9a08g046-lvds.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,r9a08= g046-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,r= 9a08g046-lvds.yaml new file mode 100644 index 000000000000..b1f6d020ae7b --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/renesas,r9a08g046-lv= ds.yaml @@ -0,0 +1,128 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/renesas,r9a08g046-lvds.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3L LVDS Encoder + +maintainers: + - Biju Das + - Tommaso Merciai + +description: | + This binding describe the LVDS encoder embedded in the Renesas RZ/G3L + SoC. The encoder can operate in LVDS Single-link mode with 4 lanes + (Data) + 1 lane (Clock). + +properties: + compatible: + const: renesas,r9a08g046-lvds + + reg: + maxItems: 1 + + clocks: + items: + - description: Peripheral clock + - description: PHY clock + - description: Dot clock + + clock-names: + items: + - const: pclk + - const: phyclk + - const: dotclk + + resets: + items: + - description: LVDS_RESET_N + - description: MIPI_DSI_PRESET_N + - description: MIPI_DSI_CMN_RSTB + - description: MIPI_DSI_ARESET_N + + reset-names: + items: + - const: lvdrst + - const: prst + - const: rst + - const: arst + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input channel, directly connected to the Display Unit. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: | + Output channel, directly connected to the LVDS panel or bridge. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - power-domains + - ports + +additionalProperties: false + +examples: + - | + #include + + lvds-cmn@108a0000 { + compatible =3D "renesas,r9a08g046-lvds-cmn", + "simple-mfd", "syscon"; + reg =3D <0x108a0000 0x10000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + lvds0: lvds@10 { + compatible =3D "renesas,r9a08g046-lvds"; + reg =3D <0x10 0x8>; + clocks =3D <&cpg CPG_MOD R9A08G046_MIPI_DSI_PCLK>, + <&cpg CPG_MOD R9A08G046_LVDS_PLLCLK>, + <&cpg CPG_MOD R9A08G046_LVDS_CLK_DOT0>; + clock-names =3D "pclk", "phyclk", "dotclk"; + resets =3D <&cpg R9A08G046_LVDS_RESET_N>, + <&cpg R9A08G046_MIPI_DSI_PRESET_N>, + <&cpg R9A08G046_MIPI_DSI_CMN_RSTB>, + <&cpg R9A08G046_MIPI_DSI_ARESET_N>; + reset-names =3D "lvdrst", "prst", "rst", "arst"; + power-domains =3D <&cpg>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + lvds0_in: endpoint { + remote-endpoint =3D <&du_out_lvds0>; + }; + }; + + port@1 { + reg =3D <1>; + lvds0_out: endpoint { + remote-endpoint =3D <&panel_in>; + }; + }; + }; + }; + }; +... --=20 2.43.0 From nobody Sat Jun 20 08:26:33 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BD46366557 for ; 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Fri, 17 Apr 2026 10:52:39 -0700 (PDT) Received: from biju.lan ([2a00:23c4:a758:8a01:528c:590:5bef:9bc8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-488fc1c773fsm56166535e9.12.2026.04.17.10.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 10:52:39 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Biju Das , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH 3/3] drm: renesas: rz-du: Add support for RZ/G3L LVDS encoder Date: Fri, 17 Apr 2026 18:52:30 +0100 Message-ID: <20260417175235.224809-4-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260417175235.224809-1-biju.das.jz@bp.renesas.com> References: <20260417175235.224809-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das Add support for the RZ/G3L LVDS encoder driver. It operates in single-link mode with 4 lanes (Data) + 1 lane (Clock) and supports pixel clock rates from 25 to 87 MHz. The LVDS module cannot be used at the same time as MIPI-DSI. However, LVDS and the DSI interface share a peripheral clock and the MIPI_DSI_PRESET_N reset signal. Also, the MIPI_DSI_CMN_RSTB and MIPI_DSI_ARESET_N reset signals must be asserted before using the LVDS module. Signed-off-by: Tommaso Merciai Signed-off-by: Biju Das --- drivers/gpu/drm/renesas/rz-du/Kconfig | 13 + drivers/gpu/drm/renesas/rz-du/Makefile | 1 + drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c | 333 ++++++++++++++++++ drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.h | 22 ++ .../gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h | 26 ++ 5 files changed, 395 insertions(+) create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.h create mode 100644 drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h diff --git a/drivers/gpu/drm/renesas/rz-du/Kconfig b/drivers/gpu/drm/renesa= s/rz-du/Kconfig index 7f2ef7137ae5..cbfc7b6bccb8 100644 --- a/drivers/gpu/drm/renesas/rz-du/Kconfig +++ b/drivers/gpu/drm/renesas/rz-du/Kconfig @@ -26,3 +26,16 @@ config DRM_RZG2L_MIPI_DSI def_tristate DRM_RZG2L_DU depends on DRM_RZG2L_USE_MIPI_DSI select DRM_MIPI_DSI + +config DRM_RZG3L_USE_LVDS + bool "RZ/G3L DU LVDS Encoder Support" + depends on DRM_BRIDGE && OF + default DRM_RZG2L_DU + help + Enable support for the RZ/G3L Display Unit embedded LVDS encoders. + +config DRM_RZG3L_LVDS + def_tristate DRM_RZG2L_DU + depends on DRM_RZG3L_USE_LVDS + select DRM_KMS_HELPER + select DRM_PANEL diff --git a/drivers/gpu/drm/renesas/rz-du/Makefile b/drivers/gpu/drm/renes= as/rz-du/Makefile index 2987900ea6b6..46decb7ac4f1 100644 --- a/drivers/gpu/drm/renesas/rz-du/Makefile +++ b/drivers/gpu/drm/renesas/rz-du/Makefile @@ -8,3 +8,4 @@ rzg2l-du-drm-$(CONFIG_VIDEO_RENESAS_VSP1) +=3D rzg2l_du_vsp= .o obj-$(CONFIG_DRM_RZG2L_DU) +=3D rzg2l-du-drm.o =20 obj-$(CONFIG_DRM_RZG2L_MIPI_DSI) +=3D rzg2l_mipi_dsi.o +obj-$(CONFIG_DRM_RZG3L_LVDS) +=3D rzg3l_lvds.o diff --git a/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c b/drivers/gpu/drm/r= enesas/rz-du/rzg3l_lvds.c new file mode 100644 index 000000000000..bedeedbdfada --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.c @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * RZ/G3L LVDS Encoder Driver + * + * Copyright (C) 2026 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "rzg3l_lvds.h" +#include "rzg3l_lvds_regs.h" + +enum rzg3l_lvds_mode { + RZG3L_LVDS_MODE_JEIDA =3D 0, + RZG3L_LVDS_MODE_JEIDA_MIRROR =3D 1, + RZG3L_LVDS_MODE_MODE2 =3D 2, + RZG3L_LVDS_MODE_MODE2_MIRROR =3D 3, + RZG3L_LVDS_MODE_VESA =3D 4, + RZG3L_LVDS_MODE_VESA_MIRROR =3D 5, + RZG3L_LVDS_MODE_MODE6 =3D 6, + RZG3L_LVDS_MODE_MODE6_MIRROR =3D 7, +}; + +struct rzg3l_lvds { + struct device *dev; + struct reset_control *prstc; + struct reset_control *lvd_rstc; + struct regmap *regmap; + + struct drm_bridge bridge; + struct drm_bridge *next_bridge; +}; + +#define bridge_to_rzg3l_lvds(b) \ + container_of(b, struct rzg3l_lvds, bridge) + +/* -----------------------------------------------------------------------= ------ + * Bridge + */ +static void rzg3l_lvds_atomic_enable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct rzg3l_lvds *lvds =3D bridge_to_rzg3l_lvds(bridge); + const struct drm_bridge_state *bridge_state; + int ret; + u32 fmt; + + /* Get the LVDS format from the bridge state. */ + bridge_state =3D drm_atomic_get_new_bridge_state(state, bridge); + if (!bridge_state) { + dev_err(lvds->dev, "failed to get bridge state\n"); + return; + } + + switch (bridge_state->output_bus_cfg.format) { + case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: + fmt =3D RZG3L_LVDS_MODE_JEIDA; + break; + case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: + fmt =3D RZG3L_LVDS_MODE_VESA; + break; + default: + fmt =3D RZG3L_LVDS_MODE_VESA; + dev_warn(lvds->dev, "Unsupported bus fmt 0x%04x\n", + bridge_state->output_bus_cfg.format); + break; + } + + ret =3D pm_runtime_resume_and_get(lvds->dev); + if (ret < 0) { + dev_err(lvds->dev, "pm_runtime_resume_and_get error\n"); + return; + } + + regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET, + LVDS_0_PHY_CH_EN_BGR, LVDS_0_PHY_CH_EN_BGR); + usleep_range(20, 25); + + regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET, + LVDS_0_PHY_CH_EN_LDO, LVDS_0_PHY_CH_EN_LDO); + usleep_range(10, 15); + + regmap_write(lvds->regmap, LVDS_CMN, LVDS_CMN_RST_PHY0_SEL); + regmap_update_bits(lvds->regmap, LVDS_0_CTL_OFFSET, + LVDS_0_CTL_FMT_SEL_MSK, + FIELD_PREP(LVDS_0_CTL_FMT_SEL_MSK, fmt)); + regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET, + LVDS_0_PHY_CH_IO_EN_MSK, LVDS_0_PHY_CH_IO_EN); + regmap_write(lvds->regmap, LVDS_CMN, + LVDS_CMN_RST_PHY0_SEL | LVDS_CMN_PHY_RESET); + usleep_range(100, 150); +} + +static void rzg3l_lvds_atomic_disable(struct drm_bridge *bridge, + struct drm_atomic_state *state) +{ + struct rzg3l_lvds *lvds =3D bridge_to_rzg3l_lvds(bridge); + + regmap_update_bits(lvds->regmap, LVDS_CMN, LVDS_CMN_PHY_RESET, 0); + regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET, + LVDS_0_PHY_CH_IO_EN_MSK, 0); + regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET, + LVDS_0_PHY_CH_EN_LDO, 0); + regmap_update_bits(lvds->regmap, LVDS_0_PHY_OFFSET, + LVDS_0_PHY_CH_EN_BGR, 0); + + pm_runtime_put(lvds->dev); +} + +static int rzg3l_lvds_attach(struct drm_bridge *bridge, + struct drm_encoder *encoder, + enum drm_bridge_attach_flags flags) +{ + struct rzg3l_lvds *lvds =3D bridge_to_rzg3l_lvds(bridge); + + if (!lvds->next_bridge) + return 0; + + return drm_bridge_attach(encoder, lvds->next_bridge, bridge, flags); +} + +static enum drm_mode_status +rzg3l_lvds_bridge_mode_valid(struct drm_bridge *bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + if (mode->clock > 87000) + return MODE_CLOCK_HIGH; + + if (mode->clock < 25000) + return MODE_CLOCK_LOW; + + return MODE_OK; +} + +bool rzg3l_lvds_is_connected(struct drm_bridge *bridge) +{ + struct rzg3l_lvds *lvds =3D bridge_to_rzg3l_lvds(bridge); + + return !!lvds->next_bridge; +} +EXPORT_SYMBOL_GPL(rzg3l_lvds_is_connected); + +static const struct drm_bridge_funcs rzg3l_lvds_bridge_ops =3D { + .attach =3D rzg3l_lvds_attach, + .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, + .atomic_reset =3D drm_atomic_helper_bridge_reset, + .atomic_enable =3D rzg3l_lvds_atomic_enable, + .atomic_disable =3D rzg3l_lvds_atomic_disable, + .mode_valid =3D rzg3l_lvds_bridge_mode_valid, +}; + +/* -----------------------------------------------------------------------= ------ + * Power Management + */ + +static int rzg3l_lvds_pm_runtime_suspend(struct device *dev) +{ + struct rzg3l_lvds *lvds =3D dev_get_drvdata(dev); + int ret; + + ret =3D reset_control_assert(lvds->lvd_rstc); + if (ret) + return ret; + + ret =3D reset_control_assert(lvds->prstc); + if (ret) + goto err_deassert_lvd_rstc; + + return 0; + +err_deassert_lvd_rstc: + reset_control_deassert(lvds->lvd_rstc); + return ret; +} + +static int rzg3l_lvds_pm_runtime_resume(struct device *dev) +{ + struct rzg3l_lvds *lvds =3D dev_get_drvdata(dev); + int ret; + + ret =3D reset_control_deassert(lvds->prstc); + if (ret) + return ret; + + return reset_control_deassert(lvds->lvd_rstc); + if (ret) + goto err_assert_prstc; + + return 0; + +err_assert_prstc: + reset_control_assert(lvds->prstc); + return ret; +} + +static const struct dev_pm_ops rzg3l_lvds_pm_ops =3D { + RUNTIME_PM_OPS(rzg3l_lvds_pm_runtime_suspend, + rzg3l_lvds_pm_runtime_resume, NULL) + SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) +}; + +/* -----------------------------------------------------------------------= ------ + * Probe & Remove + */ + +static int rzg3l_lvds_parse_dt(struct rzg3l_lvds *lvds) +{ + struct device *dev =3D lvds->dev; + struct drm_panel *panel; + int ret; + + ret =3D drm_of_find_panel_or_bridge(dev->of_node, 1, 0, + &panel, &lvds->next_bridge); + if (ret) + return ret; + + if (panel) { + lvds->next_bridge =3D devm_drm_panel_bridge_add(dev, panel); + if (IS_ERR_OR_NULL(lvds->next_bridge)) + return -EINVAL; + } + + return 0; +} + +static int rzg3l_lvds_probe(struct platform_device *pdev) +{ + struct reset_control *rstc, *arstc; + struct device *dev =3D &pdev->dev; + struct rzg3l_lvds *lvds; + int ret; + + lvds =3D devm_drm_bridge_alloc(dev, struct rzg3l_lvds, bridge, + &rzg3l_lvds_bridge_ops); + if (IS_ERR(lvds)) + return PTR_ERR(lvds); + + lvds->dev =3D dev; + lvds->bridge.of_node =3D pdev->dev.of_node; + + lvds->regmap =3D syscon_node_to_regmap(dev->of_node->parent); + if (IS_ERR(lvds->regmap)) + return PTR_ERR(lvds->regmap); + + rstc =3D devm_reset_control_get_optional_exclusive(dev, "rst"); + if (IS_ERR(rstc)) + return dev_err_probe(dev, PTR_ERR(rstc), "failed to get rst\n"); + + arstc =3D devm_reset_control_get_optional_exclusive(dev, "arst"); + if (IS_ERR(arstc)) + return dev_err_probe(dev, PTR_ERR(arstc), + "failed to get arst\n"); + + lvds->prstc =3D devm_reset_control_get_shared(dev, "prst"); + if (IS_ERR(lvds->prstc)) + return dev_err_probe(dev, PTR_ERR(lvds->prstc), + "failed to get prst\n"); + + lvds->lvd_rstc =3D devm_reset_control_get_shared(dev, "lvdrst"); + if (IS_ERR(lvds->lvd_rstc)) + return dev_err_probe(dev, PTR_ERR(lvds->lvd_rstc), + "failed to get core reset\n"); + + platform_set_drvdata(pdev, lvds); + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return dev_err_probe(dev, ret, "Failed to enable Runtime PM\n"); + + ret =3D rzg3l_lvds_parse_dt(lvds); + if (ret < 0) + return ret; + + ret =3D reset_control_assert(rstc); + if (ret < 0) + return ret; + + ret =3D reset_control_assert(arstc); + if (ret < 0) + return ret; + + ret =3D devm_drm_bridge_add(dev, &lvds->bridge); + if (ret) + return dev_err_probe(dev, ret, + "Failed to register drm bridge\n"); + + return ret; +} + +static const struct of_device_id rzg3l_lvds_of_table[] =3D { + { .compatible =3D "renesas,r9a08g046-lvds" }, + { /* sentinel */ } +}; + +MODULE_DEVICE_TABLE(of, rzg3l_lvds_of_table); + +static struct platform_driver rzg3l_lvds_platform_driver =3D { + .probe =3D rzg3l_lvds_probe, + .driver =3D { + .name =3D "rzg3l-lvds", + .pm =3D pm_ptr(&rzg3l_lvds_pm_ops), + .of_match_table =3D rzg3l_lvds_of_table, + }, +}; + +module_platform_driver(rzg3l_lvds_platform_driver); + +MODULE_AUTHOR("Biju Das "); +MODULE_AUTHOR("Tommaso Merciai "); +MODULE_DESCRIPTION("Renesas RZ/G3L LVDS Encoder Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.h b/drivers/gpu/drm/r= enesas/rz-du/rzg3l_lvds.h new file mode 100644 index 000000000000..2ea3cf4e1cae --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * RZ/G3L LVDS Encoder + * + * Copyright (C) 2026 Renesas Electronics Corporation + * + */ + +#ifndef __RZG3L_LVDS_H__ +#define __RZG3L_LVDS_H__ + +struct drm_bridge; + +#if IS_ENABLED(CONFIG_DRM_RZG3L_LVDS) +bool rzg3l_lvds_is_connected(struct drm_bridge *bridge); +#else +static inline bool rzg3l_lvds_is_connected(struct drm_bridge *bridge) +{ + return false; +} +#endif /* CONFIG_DRM_RZG3L_LVDS */ +#endif /* __RZG3L_LVDS_H__ */ diff --git a/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h b/drivers/gpu/= drm/renesas/rz-du/rzg3l_lvds_regs.h new file mode 100644 index 000000000000..281b7648f168 --- /dev/null +++ b/drivers/gpu/drm/renesas/rz-du/rzg3l_lvds_regs.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * RZ/G3L LVDS Interface Registers Definitions + * + * Copyright (C) 2026 Renesas Electronics Corporation + * + */ + +#ifndef __RZG3L_LVDS_REGS_H__ +#define __RZG3L_LVDS_REGS_H__ + +#define LVDS_CMN 0x00 +#define LVDS_CMN_RST_PHY0_SEL (1 << 24) +#define LVDS_CMN_RST_PHY0_SEL_CH0 (1 << 24) +#define LVDS_CMN_PHY_RESET (1 << 0) + +#define LVDS_0_PHY_OFFSET 0x10 +#define LVDS_0_PHY_CH_IO_EN_MSK (0x1f) +#define LVDS_0_PHY_CH_IO_EN (LVDS_0_PHY_CH_IO_EN_MSK << 0) +#define LVDS_0_PHY_CH_EN_BGR BIT(8) +#define LVDS_0_PHY_CH_EN_LDO BIT(9) + +#define LVDS_0_CTL_OFFSET 0x14 +#define LVDS_0_CTL_FMT_SEL_MSK GENMASK(23, 20) + +#endif /* __RZG3L_LVDS_REGS_H__ */ --=20 2.43.0