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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ba451cdfd27sm26448466b.26.2026.04.17.00.07.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 00:07:50 -0700 (PDT) From: Luca Weiss Date: Fri, 17 Apr 2026 09:07:44 +0200 Subject: [PATCH v3 1/3] dt-bindings: clock: qcom: document the Milos GX clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260417-milos-gxclkctl-v3-1-08f5988c43a2@fairphone.com> References: <20260417-milos-gxclkctl-v3-0-08f5988c43a2@fairphone.com> In-Reply-To: <20260417-milos-gxclkctl-v3-0-08f5988c43a2@fairphone.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Krzysztof Kozlowski X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776409667; l=2723; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=AMCItOgDdHgKRdx1GXTFHeaC4r97dyq4obHVbtp3GHw=; b=hUIxkwNCfgNBT48GTiRI3BvsQ5rtFklAYZzv51cQl26o2DQEuT+YGDpXuqxrSQEZS2UEtKPQ+ DXfgdvp/FGZBzOFwEIAp8Nhu5X+KFyue9GP1EMWKw+uLxVinjHuHvWV X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and Power domains (GDSC), but the requirement from the SW driver is to use the GDSC power domain from the clock controller to recover the GPU firmware in case of any failure/hangs. The rest of the resources of the clock controller are being used by the firmware of GPU. This module exposes the GDSC power domains which helps the recovery of Graphics subsystem. Milos can reuse the qcom,kaanapali-gxclkctl.h header due to similarity of the hardware block, and also reuse of the Linux driver. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss --- .../bindings/clock/qcom,milos-gxclkctl.yaml | 61 ++++++++++++++++++= ++++ 1 file changed, 61 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-gxclkctl.ya= ml b/Documentation/devicetree/bindings/clock/qcom,milos-gxclkctl.yaml new file mode 100644 index 000000000000..fbcb5d3f3e3d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,milos-gxclkctl.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,milos-gxclkctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Power Domain Controller on Milos + +maintainers: + - Luca Weiss + +description: | + Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and + Power domains (GDSC). This module provides the power domains control + of gxclkctl on Qualcomm SoCs which helps the recovery of Graphics subsys= tem. + + See also: + include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h + +properties: + compatible: + enum: + - qcom,milos-gxclkctl + + reg: + maxItems: 1 + + power-domains: + description: + Power domains required for the clock controller to operate + items: + - description: GFX power domain + - description: GPUCC(CX) power domain + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - power-domains + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + clock-controller@3d64000 { + compatible =3D "qcom,milos-gxclkctl"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&gpucc 0>; + #power-domain-cells =3D <1>; + }; + }; +... --=20 2.53.0 From nobody Wed Jun 10 08:05:57 2026 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D8A633ADB5 for ; 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ba451cdfd27sm26448466b.26.2026.04.17.00.07.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 00:07:51 -0700 (PDT) From: Luca Weiss Date: Fri, 17 Apr 2026 09:07:45 +0200 Subject: [PATCH v3 2/3] clk: qcom: Add support for GXCLK for Milos Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260417-milos-gxclkctl-v3-2-08f5988c43a2@fairphone.com> References: <20260417-milos-gxclkctl-v3-0-08f5988c43a2@fairphone.com> In-Reply-To: <20260417-milos-gxclkctl-v3-0-08f5988c43a2@fairphone.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Jagadeesh Kona , Taniya Das , Dmitry Baryshkov X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776409667; l=2067; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=CxKlaHXcmKClm+BXYNnlDwRO4wTrssG9zSsFyKBZQhI=; b=D1Q+NSNmBB5WEGCN3xpZmWLXLC0ji06xpDbVD0s5K0mlHcPmHDp0OIJIvcmuHELDdefVf2PIA BpHzZnehC+uCT/qY2Kt9FKSzS8FAQoPtZmCSxNVaig4NgT41gr0UF+Z X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= GXCLKCTL (Graphics GX Clock Controller) is a block dedicated to managing clocks for the GPU subsystem on GX power domain. The GX clock controller driver manages only the GX GDSC and the rest of the resources of the controller are managed by the firmware. We can use the existing kaanapali driver for Milos as well since the GX_CLKCTL_GX_GDSC supported by the Linux driver requires the same configuration. Reviewed-by: Jagadeesh Kona Reviewed-by: Taniya Das Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss --- drivers/clk/qcom/Makefile | 2 +- drivers/clk/qcom/gxclkctl-kaanapali.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 89d07c35e4d9..462c7615a6d7 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -189,7 +189,7 @@ obj-$(CONFIG_SM_GPUCC_8450) +=3D gpucc-sm8450.o obj-$(CONFIG_SM_GPUCC_8550) +=3D gpucc-sm8550.o obj-$(CONFIG_SM_GPUCC_8650) +=3D gpucc-sm8650.o obj-$(CONFIG_SM_GPUCC_8750) +=3D gpucc-sm8750.o gxclkctl-kaanapali.o -obj-$(CONFIG_SM_GPUCC_MILOS) +=3D gpucc-milos.o +obj-$(CONFIG_SM_GPUCC_MILOS) +=3D gpucc-milos.o gxclkctl-kaanapali.o obj-$(CONFIG_SM_LPASSCC_6115) +=3D lpasscc-sm6115.o obj-$(CONFIG_SM_TCSRCC_8550) +=3D tcsrcc-sm8550.o obj-$(CONFIG_SM_TCSRCC_8650) +=3D tcsrcc-sm8650.o diff --git a/drivers/clk/qcom/gxclkctl-kaanapali.c b/drivers/clk/qcom/gxclk= ctl-kaanapali.c index 40d856378a74..7b0af0ba1e68 100644 --- a/drivers/clk/qcom/gxclkctl-kaanapali.c +++ b/drivers/clk/qcom/gxclkctl-kaanapali.c @@ -53,6 +53,7 @@ static const struct qcom_cc_desc gx_clkctl_kaanapali_desc= =3D { static const struct of_device_id gx_clkctl_kaanapali_match_table[] =3D { { .compatible =3D "qcom,glymur-gxclkctl" }, { .compatible =3D "qcom,kaanapali-gxclkctl" }, + { .compatible =3D "qcom,milos-gxclkctl" }, { .compatible =3D "qcom,sm8750-gxclkctl" }, { } }; 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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ba451cdfd27sm26448466b.26.2026.04.17.00.07.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 17 Apr 2026 00:07:52 -0700 (PDT) From: Luca Weiss Date: Fri, 17 Apr 2026 09:07:46 +0200 Subject: [PATCH v3 3/3] arm64: dts: qcom: milos: Add GX clock controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260417-milos-gxclkctl-v3-3-08f5988c43a2@fairphone.com> References: <20260417-milos-gxclkctl-v3-0-08f5988c43a2@fairphone.com> In-Reply-To: <20260417-milos-gxclkctl-v3-0-08f5988c43a2@fairphone.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , Alexander Koskovich Cc: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Konrad Dybcio , Jagadeesh Kona X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776409667; l=1066; i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id; bh=++e5FZB0tsvADRX7W3I2ua7//VvtHVnA0IB0LJVNzdk=; b=8898ctpJBm3z6J1Uj5QTf6yngGfQCbUWxKiZsXVNy4Ta5P8d/CK0C0G4aB6tnCpRQPEcfJeNB L8jWLKqiTU4Av8SW1RkWv8ZYRUHrsnE6+elqbkdzzz/fze4rBXJsT2v X-Developer-Key: i=luca.weiss@fairphone.com; a=ed25519; pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8= Add a node for the GX clock controller, which provides a power domain to consumers. Reviewed-by: Konrad Dybcio Reviewed-by: Jagadeesh Kona Signed-off-by: Luca Weiss --- arch/arm64/boot/dts/qcom/milos.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom= /milos.dtsi index 4a64a98a434b..4bd9181ca03e 100644 --- a/arch/arm64/boot/dts/qcom/milos.dtsi +++ b/arch/arm64/boot/dts/qcom/milos.dtsi @@ -1542,6 +1542,16 @@ lpass_ag_noc: interconnect@3c40000 { qcom,bcm-voters =3D <&apps_bcm_voter>; }; =20 + gxclkctl: clock-controller@3d64000 { + compatible =3D "qcom,milos-gxclkctl"; + reg =3D <0x0 0x03d64000 0x0 0x6000>; + + power-domains =3D <&rpmhpd RPMHPD_GFX>, + <&gpucc GPU_CC_CX_GDSC>; + + #power-domain-cells =3D <1>; + }; + gpucc: clock-controller@3d90000 { compatible =3D "qcom,milos-gpucc"; reg =3D <0x0 0x03d90000 0x0 0x9800>; --=20 2.53.0