From nobody Tue Jun 16 06:03:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D467C29C33F for ; Thu, 16 Apr 2026 17:57:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776362239; cv=none; b=aFaTT52ymPj1Bfd1/6vlsNzHobuVbpGkj7FsXUSuHUj1QzrUV2N7Rymrv58h1r3d7OUcW1uNv+6EiAa82BatV/nL2abb/mFDAA1f+B3BTHQkxOsDbNNqXafTM1/72qD0N+HcFlxU9Z2hXM0yHbLlFVmcljlUlvJyiZGBvrIjSa4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776362239; c=relaxed/simple; bh=Z4Qbr2ArJ5Ivc+8c4wPA6/J5rPKAKUL1RthHGDqpNIQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WzNVrx6RQn5kp8t1hECUvyyMJxeh/k+6WM87XzhjpKQOxD098vHudirX3+fukNzt/usHcPlssPA9NuQt8oyqYk5EDdhxGtt713sjLaEGxISpL8FU/97Kew6J3gqkRWQRTVBmq32nZ636rgz7wteH2eCW4CGGMz9u3YRQXjmdR4I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FQIjg3Kz; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FQIjg3Kz" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776362237; x=1807898237; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z4Qbr2ArJ5Ivc+8c4wPA6/J5rPKAKUL1RthHGDqpNIQ=; b=FQIjg3Kzx2T7KV8sISN9l2lWlrJ/G0UchKSl4jXYNzdomCdSZuZCF+J2 EVZCpYgNojffNxL2jdgXw7R2LSoUqvVeSheQ9QTKCagLNR2qbEbpUVUts Xk6aaX5BPLocPu+jFvJLCF18il9x4eG0Spm4fASFAVMfS8rXaOMGtEqwr GqwzAGZnT2JoorWghkUXeKmC+boBcLDJwHRiMw8ITCKlLl0QvgVC2VHDn 9a5JdfIMcDStKsAiG9UsZc24WGNxwWwkX/nC+01QdYSaRrP8r8uzDaNuA R0o7aA7+t0MTnvOmdVY6yZd5Po+6wv9boa9aFqMU1eJjvPbLIZaUp9ES8 Q==; X-CSE-ConnectionGUID: +MblaMFWQIOJR7syvYfsAQ== X-CSE-MsgGUID: g4+wqSUQRHagdhHdF5RYjQ== X-IronPort-AV: E=McAfee;i="6800,10657,11761"; a="94778347" X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="94778347" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:17 -0700 X-CSE-ConnectionGUID: 9mVuN3hpS9OFxzYFtDpqgA== X-CSE-MsgGUID: Eu0n5YNyT4SQgPVxvuhnUg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="235784476" Received: from abityuts-desk.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.222]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:16 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/16] i3c: mipi-i3c-hci: Fix suspend behavior when bus disable falls back to software reset Date: Thu, 16 Apr 2026 20:56:49 +0300 Message-ID: <20260416175704.41217-2-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260416175704.41217-1-adrian.hunter@intel.com> References: <20260416175704.41217-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Software reset was introduced as a fallback if bus disable failed. The change was made in 2 places: the cleanup path and the suspend path. For the cleanup path, after software reset the function continues to do cleanup for the current I/O mode. For the suspend path, after software reset the function returns early. However software reset does not reset any Ring Headers in the Host Controller, so returning early is not the right thing to do. Instead, continue to call suspend for the current I/O mode, which for DMA mode will reset any Ring Headers. Note, although Ring Headers should not be active at this stage, performing this reset follows the procedure defined by the specification and keeps the suspend path consistent with the cleanup path. Fixes: 9a258d1336f7 ("i3c: mipi-i3c-hci: Fallback to software reset when bu= s disable fails") Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/core.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index b781dbed2165..bb8f2d830b0d 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -765,16 +765,14 @@ int i3c_hci_rpm_suspend(struct device *dev) int ret; =20 ret =3D i3c_hci_bus_disable(hci); - if (ret) { - /* Fall back to software reset to disable the bus */ + + /* Fall back to software reset to disable the bus */ + if (ret) ret =3D i3c_hci_software_reset(hci); - i3c_hci_sync_irq_inactive(hci); - return ret; - } =20 hci->io->suspend(hci); =20 - return 0; + return ret; } EXPORT_SYMBOL_GPL(i3c_hci_rpm_suspend); =20 --=20 2.51.0 From nobody Tue Jun 16 06:03:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A535A3264CE for ; Thu, 16 Apr 2026 17:57:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776362241; cv=none; b=FKJxhdE/YE2FOxzhvgNTE7cK1LW9jYRKBg0OrDBzl8H+cWMgXzQwbF4ruUJg9t4h/nLrHi5MNM6YfDkfxEUAZpAFp38Rfn7pg9P9NX9gl/Azj/Nmo/pb4s4dBrI63xsBpnbgnTydzpYrHBRhrcYBR3cULyAhpt5lZiUX/fcM7b4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776362241; c=relaxed/simple; bh=l9/XGCFmUNwQod5vP59DMBBLRtrS7gHKb+3bXhugszg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FE53YqUDNgTvt4kkuXywjP8MNHXmz1T9SkgXS5SlUpAQWKZFimlmxzY1uMdCmS4Td2nOJwtXQ0t9d7uBgL/hToagXcuJggPkUfSQbos2ywG+UA/8+s7aCKCds9bzjICduj/zWnBGdBl5PwG+lneG1sT6IdyHQ1Sd3My3u2v04zE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=l84hoXEm; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="l84hoXEm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776362239; x=1807898239; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=l9/XGCFmUNwQod5vP59DMBBLRtrS7gHKb+3bXhugszg=; b=l84hoXEmGCkJQ7+93aBBo+QSmn9ednXx7WVdnQPcZiodWW/39KuTWIzn gyrC6qP7dCx6Q6jqkPIRPz6L4F8TKznMcqGuSark87yzXiGfyjP6hL8d3 76KEjRDbMCccjiBCFBl9blhSzRuNF1bkpOJftROzHnJXBH4d6uUHq3wrY JMLGtWgpqCcfvKCJ5zsZJ+tN+gkLzpjJ25uyjUwhuYsX/bfTjAhv9jaC5 f5khEWs562TKC5Aa1owh0lhBhoQHi3cRQjNddf+xI0b4oeLZKtNwiJSO3 npn3UWYD7WtzjWn/vertRRR9cwsmLrw5cvireP+oIkzNioAUlCtfmNuka g==; X-CSE-ConnectionGUID: XdgzRZrLTUepPaHgnTc+nw== X-CSE-MsgGUID: 2tAOEFi7Rw6LX/xiE386aQ== X-IronPort-AV: E=McAfee;i="6800,10657,11761"; a="94778352" X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="94778352" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:19 -0700 X-CSE-ConnectionGUID: kIiwc/EaSDmzZmXvO31fow== X-CSE-MsgGUID: QFePmp03S+iUz8tJOhaYog== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="235784490" Received: from abityuts-desk.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.222]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:18 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/16] i3c: mipi-i3c-hci: Preserve RUN bit when aborting DMA ring Date: Thu, 16 Apr 2026 20:56:50 +0300 Message-ID: <20260416175704.41217-3-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260416175704.41217-1-adrian.hunter@intel.com> References: <20260416175704.41217-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The MIPI I3C HCI specification does not require the DMA ring RUN bit (RUN_STOP) to be cleared when issuing an ABORT. Adjust the RING_CONTROL handling to set ABORT without clearing RUN_STOP, bringing the driver into alignment with the specification. According to the specification, that allows the DMA ring to continue to receive IBIs, although currently ABORT is only used in an error path so the change has very little effect in practice. Fixes: b795e68bf3073 ("i3c: mipi-i3c-hci: Correct RING_CTRL_ABORT handling = in DMA dequeue") Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index e487ef52f6b4..4cd32e3afa7b 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -554,7 +554,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, if (ring_status & RING_STATUS_RUNNING) { /* stop the ring */ reinit_completion(&rh->op_done); - rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_ABORT); + rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); wait_for_completion_timeout(&rh->op_done, HZ); ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { --=20 2.51.0 From nobody Tue Jun 16 06:03:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ABEA3033E3 for ; Thu, 16 Apr 2026 17:57:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776362242; cv=none; b=T4YIwksgZdVW2GpyI83wbd2jHrTVXWUMJxrTyntNyMVMSj8opILBqYev+FTf6CNqFyN5AKsJ5L8/sVZo//m/gcych8WHvWw3DUBGBz6VQ96/H65iLHYdj2kgOF5vt9CRHPQBP3vm8ApeVqTiJUSDCSKTKDukKiEdwvv7k+X8VK4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776362242; c=relaxed/simple; bh=wfG7OXmk6jxD8gytR4muq6DVuXJrOsNEGNsRvQWdBrw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VLTwQWFSA2BgdCY2gr5g/mNxv3uBnkuJCWTiVGrqSfx1X/mXIS/dobBxHCQK6F8eLfK06t8TpU38cvysJDUgDiHaLeLvmwlCtVp2U41zi2kZ/pClB/hloivY8aGwp9UnaDjcmcg+hLYNw1iEa9OiQAcusHM8yK39XnCwOcmht1s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=VlW+Ju7H; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="VlW+Ju7H" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776362241; x=1807898241; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wfG7OXmk6jxD8gytR4muq6DVuXJrOsNEGNsRvQWdBrw=; b=VlW+Ju7Hf4lrhC/s9Q0PkUscvChzwPYlzclAsTUMbiuc6F5w/T8A6ZLF 7RlVTCVZG5HBc6JVqFcCyImDQcOHeDrol6bcc62iFmaWcZs1IStcJxK+u dui0R0E1uMIlzttCiKkQqN1JYLR5VdE8s4yFQN3JLWWTTpRZ74BWUAy8x nA1yRcsg1lHlv3fdXqpu3Gykn9ySrYATSS1OfCNIQ/U4PU2w6nKVDa61+ mgq29FfKHr8AUcQV/8WE8MkflAm/KjcI8Uxxm99KtIi8sq0U8cblzq59C wppE6+tU6wStUSfxTR37yD7zlQ+xGDwaqBHBYYayJpIm4UqiLa4OCBZvt w==; X-CSE-ConnectionGUID: yMgJmBejQf6S+YJKZvaEHQ== X-CSE-MsgGUID: U0X7ISihReeUqY/q2CkLHg== X-IronPort-AV: E=McAfee;i="6800,10657,11761"; a="94778356" X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="94778356" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:21 -0700 X-CSE-ConnectionGUID: GxLc2QaFToGsAxCIxgGlBg== X-CSE-MsgGUID: VOi+i/kKQXWLGBoEX0v+1Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="235784504" Received: from abityuts-desk.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.222]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:20 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/16] i3c: mipi-i3c-hci: Prevent DMA enqueue while ring is aborting or in error Date: Thu, 16 Apr 2026 20:56:51 +0300 Message-ID: <20260416175704.41217-4-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260416175704.41217-1-adrian.hunter@intel.com> References: <20260416175704.41217-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Block the DMA enqueue path while a Ring abort is in progress or after an error condition has been detected. Previously, new transfers could be enqueued while the DMA Ring was being aborted or while error handling was underway. This allowed enqueue and error-recovery paths to run concurrently, potentially interfering with each other and corrupting Ring state. Introduce explicit enqueue blocking and a wait queue to serialize access: enqueue operations now wait until abort or error handling has completed before proceeding. Enqueue is unblocked once the Ring is safely restarted. Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/core.c | 1 + drivers/i3c/master/mipi-i3c-hci/dma.c | 25 +++++++++++++++++++++++-- drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ 3 files changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index bb8f2d830b0d..5e1bc6d819cf 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -976,6 +976,7 @@ static int i3c_hci_probe(struct platform_device *pdev) =20 spin_lock_init(&hci->lock); mutex_init(&hci->control_mutex); + init_waitqueue_head(&hci->enqueue_wait_queue); =20 /* * Multi-bus instances share the same MMIO address range, but not diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 4cd32e3afa7b..314635e6e190 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -484,6 +484,12 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, =20 spin_lock_irq(&hci->lock); =20 + while (unlikely(hci->enqueue_blocked)) { + spin_unlock_irq(&hci->lock); + wait_event(hci->enqueue_wait_queue, !READ_ONCE(hci->enqueue_blocked)); + spin_lock_irq(&hci->lock); + } + if (n > rh->xfer_space) { spin_unlock_irq(&hci->lock); hci_dma_unmap_xfer(hci, xfer_list, n); @@ -539,6 +545,14 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, return 0; } =20 +static void hci_dma_unblock_enqueue(struct i3c_hci *hci) +{ + if (hci->enqueue_blocked) { + hci->enqueue_blocked =3D false; + wake_up_all(&hci->enqueue_wait_queue); + } +} + static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, struct hci_xfer *xfer_list, int n) { @@ -550,12 +564,17 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 guard(mutex)(&hci->control_mutex); =20 + spin_lock_irq(&hci->lock); + ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { + hci->enqueue_blocked =3D true; + spin_unlock_irq(&hci->lock); /* stop the ring */ reinit_completion(&rh->op_done); rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); wait_for_completion_timeout(&rh->op_done, HZ); + spin_lock_irq(&hci->lock); ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { /* @@ -567,8 +586,6 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } } =20 - spin_lock_irq(&hci->lock); - for (i =3D 0; i < n; i++) { struct hci_xfer *xfer =3D xfer_list + i; int idx =3D xfer->ring_entry; @@ -604,6 +621,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP); =20 + hci_dma_unblock_enqueue(hci); + spin_unlock_irq(&hci->lock); =20 return did_unqueue; @@ -647,6 +666,8 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, stru= ct hci_rh_data *rh) } if (xfer->completion) complete(xfer->completion); + if (RESP_STATUS(resp)) + hci->enqueue_blocked =3D true; } =20 done_ptr =3D (done_ptr + 1) % rh->xfer_entries; diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index f17f43494c1b..d630400ec945 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -54,6 +54,8 @@ struct i3c_hci { struct mutex control_mutex; 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16 Apr 2026 10:57:22 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/16] i3c: mipi-i3c-hci: Wait for DMA ring restart to complete Date: Thu, 16 Apr 2026 20:56:52 +0300 Message-ID: <20260416175704.41217-5-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260416175704.41217-1-adrian.hunter@intel.com> References: <20260416175704.41217-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Although hci_dma_dequeue_xfer() is serialized against itself via control_mutex, this does not guarantee that a DMA ring restart triggered by a previous invocation has fully completed. When the function is called again in rapid succession, the DMA ring may still be transitioning back to the running state, which may confound or disrupt further state changes. Address this by waiting for the DMA ring restart to complete before continuing. Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/dma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 314635e6e190..28614fdbf558 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -617,6 +617,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } =20 /* restart the ring */ + reinit_completion(&rh->op_done); mipi_i3c_hci_resume(hci); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP); @@ -625,6 +626,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 spin_unlock_irq(&hci->lock); =20 + wait_for_completion_timeout(&rh->op_done, HZ); + return did_unqueue; } =20 --=20 2.51.0 From nobody Tue Jun 16 06:03:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71C4C332EA2 for ; Thu, 16 Apr 2026 17:57:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776362246; cv=none; b=aBg7uRpuDgZbhw+sjgi2UgverWXOsrMyqrAzQD1WzlKkTbvq31KFmbbM23zgz/VaknHT3c1yKsDrgxdJu8dgf2SahvKch6OoZ8TUY428Q4GSllNtbZycBm3JHSUrNAps0x1Ary7nGUZg6LM5z8AxHucNYVUQmHqEaRwMxAZ73TE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776362246; c=relaxed/simple; bh=dgjsmQh9bebq8fR+LNNb1CpwZCNgA6sbRNg+TBYN02g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RE9WVi3zB85l+bY85yIUk9DcT5PO2lY/J+BZ9EZXGhoOkoStj5l8yceK90NKvpBt97AY+jklEZRye3YW6xutScEEYF58s9xJ5VRmDG0JvAtBAsYIq4x+mwCHvdoHZzT0XHjplKNF5+vkRRtCVeZtGYMKVOiTX79/dZ7ylLPaiac= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=G5yYrgH7; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="G5yYrgH7" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776362245; x=1807898245; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dgjsmQh9bebq8fR+LNNb1CpwZCNgA6sbRNg+TBYN02g=; b=G5yYrgH7kXUi71g9NCt3i+R3by/nTLk3PDqbBpgmcwtbK0YNmlwUCHr7 vH8S2OMRWEs1jcmWlx0iJqRiCC53X9OvhLVBClFEC4s4jQkeNpc8xOjRc G8kSgf9JElSSOojp0jVW8rGOiZnilRWPnECRiVFfkSGWgW3BO8d7WYmR4 Qozhy4YElr4dVmzYx2ODdeTcDv1yQTlpiWdsJq9EyYtn8eepqCBAytjzc Nx0VePGmgpG6+hjjR3WHUclLCkpzRhYB9I7jIrOwa27FUzTvZicCSIQv3 i7loaPlpQdGXWoO1VcfkR0bJikRqQmhgDhmbuXNzix9c5T1O7NjNDtusm Q==; X-CSE-ConnectionGUID: XKiKqezyQkyPRUxuP0gWBg== X-CSE-MsgGUID: xpPI/PKuTMaolHsr8G4GWw== X-IronPort-AV: E=McAfee;i="6800,10657,11761"; a="94778374" X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="94778374" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:25 -0700 X-CSE-ConnectionGUID: 7kI3+rS3Q/mxHLw6JfBXyQ== X-CSE-MsgGUID: STmQie51SA21wanEcZGexQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="235784534" Received: from abityuts-desk.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.222]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:24 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/16] i3c: mipi-i3c-hci: Move hci_dma_xfer_done() definition Date: Thu, 16 Apr 2026 20:56:53 +0300 Message-ID: <20260416175704.41217-6-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260416175704.41217-1-adrian.hunter@intel.com> References: <20260416175704.41217-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move hci_dma_xfer_done() earlier in the file to avoid a forward declaration needed by a subsequent change. No functional change. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- drivers/i3c/master/mipi-i3c-hci/dma.c | 98 +++++++++++++-------------- 1 file changed, 49 insertions(+), 49 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 28614fdbf558..c9852b85d6b0 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -545,6 +545,55 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, return 0; } =20 +static void hci_dma_xfer_done(struct i3c_hci *hci, struct hci_rh_data *rh) +{ + u32 op1_val, op2_val, resp, *ring_resp; + unsigned int tid, done_ptr =3D rh->done_ptr; + unsigned int done_cnt =3D 0; + struct hci_xfer *xfer; + + for (;;) { + op2_val =3D rh_reg_read(RING_OPERATION2); + if (done_ptr =3D=3D FIELD_GET(RING_OP2_CR_DEQ_PTR, op2_val)) + break; + + ring_resp =3D rh->resp + rh->resp_struct_sz * done_ptr; + resp =3D *ring_resp; + tid =3D RESP_TID(resp); + dev_dbg(&hci->master.dev, "resp =3D 0x%08x", resp); + + xfer =3D rh->src_xfers[done_ptr]; + if (!xfer) { + dev_dbg(&hci->master.dev, "orphaned ring entry"); + } else { + hci_dma_unmap_xfer(hci, xfer, 1); + rh->src_xfers[done_ptr] =3D NULL; + xfer->ring_entry =3D -1; + xfer->response =3D resp; + if (tid !=3D xfer->cmd_tid) { + dev_err(&hci->master.dev, + "response tid=3D%d when expecting %d\n", + tid, xfer->cmd_tid); + /* TODO: do something about it? */ + } + if (xfer->completion) + complete(xfer->completion); + if (RESP_STATUS(resp)) + hci->enqueue_blocked =3D true; + } + + done_ptr =3D (done_ptr + 1) % rh->xfer_entries; + rh->done_ptr =3D done_ptr; + done_cnt +=3D 1; + } + + rh->xfer_space +=3D done_cnt; + op1_val =3D rh_reg_read(RING_OPERATION1); + op1_val &=3D ~RING_OP1_CR_SW_DEQ_PTR; + op1_val |=3D FIELD_PREP(RING_OP1_CR_SW_DEQ_PTR, done_ptr); + rh_reg_write(RING_OPERATION1, op1_val); +} + static void hci_dma_unblock_enqueue(struct i3c_hci *hci) { if (hci->enqueue_blocked) { @@ -636,55 +685,6 @@ static int hci_dma_handle_error(struct i3c_hci *hci, s= truct hci_xfer *xfer_list, return hci_dma_dequeue_xfer(hci, xfer_list, n) ? -EIO : 0; } =20 -static void hci_dma_xfer_done(struct i3c_hci *hci, struct hci_rh_data *rh) -{ - u32 op1_val, op2_val, resp, *ring_resp; - unsigned int tid, done_ptr =3D rh->done_ptr; - unsigned int done_cnt =3D 0; - struct hci_xfer *xfer; - - for (;;) { - op2_val =3D rh_reg_read(RING_OPERATION2); - if (done_ptr =3D=3D FIELD_GET(RING_OP2_CR_DEQ_PTR, op2_val)) - break; - - ring_resp =3D rh->resp + rh->resp_struct_sz * done_ptr; - resp =3D *ring_resp; - tid =3D RESP_TID(resp); - dev_dbg(&hci->master.dev, "resp =3D 0x%08x", resp); - - xfer =3D rh->src_xfers[done_ptr]; - if (!xfer) { - dev_dbg(&hci->master.dev, "orphaned ring entry"); - } else { - hci_dma_unmap_xfer(hci, xfer, 1); - rh->src_xfers[done_ptr] =3D NULL; - xfer->ring_entry =3D -1; - xfer->response =3D resp; - if (tid !=3D xfer->cmd_tid) { - dev_err(&hci->master.dev, - "response tid=3D%d when expecting %d\n", - tid, xfer->cmd_tid); - /* TODO: do something about it? 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Ensure that state is current by explicitly invoking hci_dma_xfer_done() from the dequeue path. This handles cases where the interrupt handler has not (yet) run. Signed-off-by: Adrian Hunter Reviewed-by: Frank Li --- drivers/i3c/master/mipi-i3c-hci/dma.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index c9852b85d6b0..28e4d38f55d3 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -635,6 +635,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } } =20 + hci_dma_xfer_done(hci, rh); + for (i =3D 0; i < n; i++) { struct hci_xfer *xfer =3D xfer_list + i; int idx =3D xfer->ring_entry; --=20 2.51.0 From nobody Tue Jun 16 06:03:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E6EA93368BB for ; Thu, 16 Apr 2026 17:57:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776362252; cv=none; b=mkrZV74Lje8P7VHRKqsok0Yc3AYLjaGD2teRHfQ89mlt4meeoxVjW1WeSbdlVJXTQsdqoqCE2CrHQ7uw9Hv9opGTO+h5DwMiWeo/39RgpVteY23HozLe1a6ZhCtTb/3ye84/t7vqXsha+Oc0fHjikzowc/YQKFs+F8ifX4lXYhU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776362252; c=relaxed/simple; bh=sftKnuMKbgr2LYtEm+2TjhHATg50Nz6kkphzeIBb1pg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=hhQXbAfzMJ4GcsYwfULI3YdkVRFRfUvgPAZ9y5pYrxmxFM5PNCDf0nuaMDukCvz4lHEWi0CRknBkwYHNzNgkYtvWS48CZIottIJLUbk2SrEXl2QmvUUbdv5tpUOc4fcq5LfQVwThGN5XD7ke17KpDYEZzefaoH7GZXUSwh85XMk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=dytrw+zp; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="dytrw+zp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776362251; x=1807898251; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sftKnuMKbgr2LYtEm+2TjhHATg50Nz6kkphzeIBb1pg=; b=dytrw+zpwnCXQCI6bmp/aGrGr8IcY5RcBAErpLroEbzgnCEqHLlKlvVG Jq5tXUGG/5RW24yHYYn6wjhE98Tn9/hELmjMNvhUFfTg7bhHMmbGILnB1 gAQhV7n6zKMVzu8fqamQYBXHRL32BRQiQUjsP5JuMxzZItCTSujj+B8WG gbwK6P5opCdQGJfOgunwGFDfysyn5vJub114kVy0pdIqxjGYf7LJkK/9G iUompk3J+yKqIwHETrX9JfTWbeWqxEZl1M6vHfryRyroxGSHRfuLchmcb mfNchxqCi5nb2xI4D1BmRhIdz37//Ogx1COWMNBoLlZzoq5lZAjFkdorb A==; X-CSE-ConnectionGUID: ZuYYXa43QDezs2vW6HkwtA== X-CSE-MsgGUID: bbJDvl4mSGOhjHTuT5fKYA== X-IronPort-AV: E=McAfee;i="6800,10657,11761"; a="94778385" X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="94778385" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:30 -0700 X-CSE-ConnectionGUID: t6yEQZbgR+O9DWEwRUK2Ug== X-CSE-MsgGUID: abSEi+MFT5+G4Rq2KJ/R3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="235784564" Received: from abityuts-desk.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.222]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:28 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/16] i3c: mipi-i3c-hci: Complete transfer lists immediately on error Date: Thu, 16 Apr 2026 20:56:55 +0300 Message-ID: <20260416175704.41217-8-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260416175704.41217-1-adrian.hunter@intel.com> References: <20260416175704.41217-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In DMA mode, transfer lists are currently completed only when the final transfer in the list completes. If an earlier transfer fails, the list is left incomplete and callers wait until timeout. There is no need to wait for a timeout, as the completion path in i3c_hci_process_xfer() already checks for error status. Complete the transfer list as soon as any transfer in the list reports an error. This avoids unnecessary delays and spurious timeouts on error. Complete a transfer list completion immediately there is an error. Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/dma.c | 6 ++++-- drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 28e4d38f55d3..5eea4fe6ebb3 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -502,6 +502,8 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, struct hci_xfer *xfer =3D xfer_list + i; u32 *ring_data =3D rh->xfer + rh->xfer_struct_sz * enqueue_ptr; =20 + xfer->completing_xfer =3D xfer_list + n - 1; + /* store cmd descriptor */ *ring_data++ =3D xfer->cmd_desc[0]; *ring_data++ =3D xfer->cmd_desc[1]; @@ -576,8 +578,8 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, stru= ct hci_rh_data *rh) tid, xfer->cmd_tid); /* TODO: do something about it? */ } - if (xfer->completion) - complete(xfer->completion); + if (xfer =3D=3D xfer->completing_xfer || RESP_STATUS(resp)) + complete(xfer->completing_xfer->completion); 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d="scan'208";a="235784586" Received: from abityuts-desk.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.222]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:30 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/16] i3c: mipi-i3c-hci: Avoid restarting DMA ring after aborting wrong transfer Date: Thu, 16 Apr 2026 20:56:56 +0300 Message-ID: <20260416175704.41217-9-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260416175704.41217-1-adrian.hunter@intel.com> References: <20260416175704.41217-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Software ABORT of the DMA ring is used to recover from transfer list timeouts, but it is inherently racy. The intended transfer list may complete just before the ABORT takes effect, causing the subsequent transfer list to be aborted instead. In this case, an incomplete transfer list may remain in the ring and has not yet been processed by hci_dma_dequeue_xfer(). Restarting the DMA ring at that point can lead to unpredictable results. Detect when the next queued transfer is not the first entry of a transfer list and does not belong to the list currently being dequeued. In that case, skip restarting the DMA ring and defer recovery until a subsequent call to hci_dma_dequeue_xfer(), which will safely restart the ring once the incomplete list is handled. Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/dma.c | 16 ++++++++++++++++ drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + 2 files changed, 17 insertions(+) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 5eea4fe6ebb3..5b394220a509 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -503,6 +503,7 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, u32 *ring_data =3D rh->xfer + rh->xfer_struct_sz * enqueue_ptr; =20 xfer->completing_xfer =3D xfer_list + n - 1; + xfer->xfer_list_pos =3D i; =20 /* store cmd descriptor */ *ring_data++ =3D xfer->cmd_desc[0]; @@ -669,6 +670,21 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } } =20 + /* + * A software ABORT may race with transfer completion and abort the next + * transfer list instead. Detect that case, and do not restart the ring. + * It will be handled by a subsequent dequeue. + */ + if (!did_unqueue) { + struct hci_xfer *xfer =3D rh->src_xfers[rh->done_ptr]; + + if (xfer && xfer->xfer_list_pos && + xfer->completing_xfer !=3D xfer_list->completing_xfer) { + spin_unlock_irq(&hci->lock); + return false; + } + } + /* restart the ring */ reinit_completion(&rh->op_done); mipi_i3c_hci_resume(hci); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index eee3e11810dd..527345a995ad 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -107,6 +107,7 @@ struct hci_xfer { struct hci_xfer *completing_xfer; int ring_number; int ring_entry; + int xfer_list_pos; }; }; }; --=20 2.51.0 From nobody Tue Jun 16 06:03:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4ED58330644 for ; Thu, 16 Apr 2026 17:57:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776362256; cv=none; b=t4eteqVfAYVwdmTG4h/dSESKoNctOGm0OjWldduF2nOSiKzBamABrLnv9aow8Ei+pxdb6/l56QKhybBh/mRlREQUqa2j/RSfKtwYkPy6LK8DIoIuj4o4V/gciXI/9oq6ZpqlepSUQrzqMB4g6yj9QfOF79hHwvVx0JmAEpcOjVM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776362256; c=relaxed/simple; bh=77W6GA+stdUcVskIr+bUAiS4B7iVgT27x26wIyOlJOA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Cwto9MRpaGM9rifcL9CEelbBOduxuXLrybG0ocGtToeO3NV33C/LEyA3/FwmR5remdSkl60dtEEWf4dw58SigDJ148QEYZ6aC+plSrjqTryeSH3G4jwwIZJ97D+gbRjwwTTWZxe1HHY98LXbxhVqx1q3lZ9loaXVNStdEDKvxdI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=NFPD53Um; arc=none smtp.client-ip=198.175.65.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="NFPD53Um" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1776362254; x=1807898254; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=77W6GA+stdUcVskIr+bUAiS4B7iVgT27x26wIyOlJOA=; b=NFPD53UmGOb3w0Z0MI3NkLj1SBEcJ/v+u/Ion0NE5BnXGjrS7UvNI1jt bFge+8rTHuIqCRW6Z9wl6OlTFDKn85BuCqhlHqhBBGnSlOiwECXp5Ys+m aRtYD0fncft5RzGwQ9IXvr2jeAWgc+HFAhutlHfUWT2p9H+ZJAWgeJwWR k/2dMqERUzc5IE3z1b9UPy0Ko+3K4QXTTOge4qEimBe7b69wldfm1eHyd 3ZLT6VK7MZm5bpgW/+1iqL6gG17b8fyEJ+uDma92QNIxiKZ34qnK6Nu5B BPdTAwIhdywGx0poW6APjXkYtcnzoDmRJVzrscD4So3Sds5ISevofp5PX Q==; X-CSE-ConnectionGUID: muZZwkz9SeWcT1df2VephQ== X-CSE-MsgGUID: yZ1+IfwWRMCQ2oWWvN86qQ== X-IronPort-AV: E=McAfee;i="6800,10657,11761"; a="94778395" X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="94778395" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:33 -0700 X-CSE-ConnectionGUID: hMpLphOhSRa9BsKs6eRD2A== X-CSE-MsgGUID: LW5nAciqTGGEuS4nylNihg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="235784598" Received: from abityuts-desk.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.222]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:32 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/16] i3c: mipi-i3c-hci: Add DMA ring abort/reset quirk for Intel controllers Date: Thu, 16 Apr 2026 20:56:57 +0300 Message-ID: <20260416175704.41217-10-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260416175704.41217-1-adrian.hunter@intel.com> References: <20260416175704.41217-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some Intel I3C HCI controllers cannot reliably restart a DMA ring after an ABORT. Additional queue resets are required to recover, and must be performed using PIO reset bits even while operating in DMA mode. This behavior is non-standard. Introduce a controller quirk to opt into the required PIO queue resets after a DMA ring abort, and enable it for Intel LPSS I3C controllers. Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/core.c | 15 ++++++++++++++- drivers/i3c/master/mipi-i3c-hci/dma.c | 9 +++++++++ drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 5e1bc6d819cf..84fb03e918b0 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -240,6 +240,18 @@ void mipi_i3c_hci_pio_reset(struct i3c_hci *hci) reg_write(RESET_CONTROL, RX_FIFO_RST | TX_FIFO_RST | RESP_QUEUE_RST); } =20 +#define ALL_QUEUES_RST (CMD_QUEUE_RST | RESP_QUEUE_RST | RX_FIFO_RST | TX_= FIFO_RST | IBI_QUEUE_RST) + +void mipi_i3c_hci_pio_reset_all_queues(struct i3c_hci *hci) +{ + u32 regval; + + reg_write(RESET_CONTROL, ALL_QUEUES_RST); + if (readx_poll_timeout_atomic(reg_read, RESET_CONTROL, regval, + !(regval & ALL_QUEUES_RST), 0, 20)) + dev_err(&hci->master.dev, "%s: Reset queues failed\n", __func__); +} + /* located here rather than dct.c because needed bits are in core reg spac= e */ void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci) { @@ -1043,7 +1055,8 @@ MODULE_DEVICE_TABLE(acpi, i3c_hci_acpi_match); static const struct platform_device_id i3c_hci_driver_ids[] =3D { { .name =3D "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED | HCI_QUIRK_RPM_IBI_ALLOWED | - HCI_QUIRK_RPM_PARENT_MANAGED }, + HCI_QUIRK_RPM_PARENT_MANAGED | + HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids); diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 5b394220a509..26533d3cc8bf 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -597,6 +597,13 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, str= uct hci_rh_data *rh) rh_reg_write(RING_OPERATION1, op1_val); } =20 +static void hci_dma_abort_requires_pio_reset_quirk(struct i3c_hci *hci, st= ruct hci_rh_data *rh) +{ + if ((hci->quirks & HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET) && + (rh_reg_read(RING_STATUS) & RING_STATUS_ABORTED)) + mipi_i3c_hci_pio_reset_all_queues(hci); +} + static void hci_dma_unblock_enqueue(struct i3c_hci *hci) { if (hci->enqueue_blocked) { @@ -638,6 +645,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, } } =20 + hci_dma_abort_requires_pio_reset_quirk(hci, rh); + hci_dma_xfer_done(hci, rh); =20 for (i =3D 0; i < n; i++) { diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 527345a995ad..352effc468d9 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -156,10 +156,12 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_RPM_ALLOWED BIT(5) /* Runtime PM allowed */ #define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed whil= e runtime suspended */ #define HCI_QUIRK_RPM_PARENT_MANAGED BIT(7) /* Runtime PM managed by pare= nt device */ +#define HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET BIT(8) /* Do PIO queue SW = resets after DMA abort */ =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); 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d="scan'208";a="235784612" Received: from abityuts-desk.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.222]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:34 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/16] i3c: mipi-i3c-hci: Add DMA ring abort quirk for Intel controllers Date: Thu, 16 Apr 2026 20:56:58 +0300 Message-ID: <20260416175704.41217-11-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260416175704.41217-1-adrian.hunter@intel.com> References: <20260416175704.41217-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" DMA rings can be aborted either per-ring via RING_CONTROL or globally via HC_CONTROL_ABORT. The driver currently relies on the per-ring mechanism. Some Intel I3C HCI controllers require HC_CONTROL_ABORT to be asserted before a DMA ring abort is effective. This behavior is non-standard. Introduce a controller quirk to select the required abort method and enable it for Intel LPSS I3C controllers. Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/core.c | 18 +++++++++++++++-- drivers/i3c/master/mipi-i3c-hci/dma.c | 27 +++++++++++++++++++++++--- drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ 3 files changed, 42 insertions(+), 5 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 84fb03e918b0..4c4e87a9b352 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -231,7 +231,20 @@ static void i3c_hci_bus_cleanup(struct i3c_master_cont= roller *m) =20 void mipi_i3c_hci_resume(struct i3c_hci *hci) { - reg_set(HC_CONTROL, HC_CONTROL_RESUME); + u32 reg =3D reg_read(HC_CONTROL); + + reg |=3D HC_CONTROL_RESUME; + reg &=3D ~HC_CONTROL_ABORT; + reg_write(HC_CONTROL, reg); +} + +void mipi_i3c_hci_abort(struct i3c_hci *hci) +{ + u32 reg =3D reg_read(HC_CONTROL); + + reg &=3D ~HC_CONTROL_RESUME; /* Do not set resume */ + reg |=3D HC_CONTROL_ABORT; + reg_write(HC_CONTROL, reg); } =20 /* located here rather than pio.c because needed bits are in core reg spac= e */ @@ -1056,7 +1069,8 @@ static const struct platform_device_id i3c_hci_driver= _ids[] =3D { { .name =3D "intel-lpss-i3c", HCI_QUIRK_RPM_ALLOWED | HCI_QUIRK_RPM_IBI_ALLOWED | HCI_QUIRK_RPM_PARENT_MANAGED | - HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET }, + HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET | + HCI_QUIRK_DMA_REQUIRES_HC_ABORT }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(platform, i3c_hci_driver_ids); diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 26533d3cc8bf..c2f48024f175 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -597,6 +597,29 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, str= uct hci_rh_data *rh) rh_reg_write(RING_OPERATION1, op1_val); } =20 +static bool hci_dma_requires_hc_abort_quirk(struct i3c_hci *hci, struct hc= i_rh_data *rh) +{ + if (!(hci->quirks & HCI_QUIRK_DMA_REQUIRES_HC_ABORT)) + return false; + + reinit_completion(&rh->op_done); + mipi_i3c_hci_abort(hci); + wait_for_completion_timeout(&rh->op_done, HZ); + rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); + + return true; +} + +static void hci_dma_abort(struct i3c_hci *hci, struct hci_rh_data *rh) +{ + if (hci_dma_requires_hc_abort_quirk(hci, rh)) + return; + + reinit_completion(&rh->op_done); + rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); + wait_for_completion_timeout(&rh->op_done, HZ); +} + static void hci_dma_abort_requires_pio_reset_quirk(struct i3c_hci *hci, st= ruct hci_rh_data *rh) { if ((hci->quirks & HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET) && @@ -630,9 +653,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, hci->enqueue_blocked =3D true; spin_unlock_irq(&hci->lock); /* stop the ring */ - reinit_completion(&rh->op_done); - rh_reg_write(RING_CONTROL, rh_reg_read(RING_CONTROL) | RING_CTRL_ABORT); - wait_for_completion_timeout(&rh->op_done, HZ); + hci_dma_abort(hci, rh); spin_lock_irq(&hci->lock); ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 352effc468d9..d542d03dc629 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -157,9 +157,11 @@ struct i3c_hci_dev_data { #define HCI_QUIRK_RPM_IBI_ALLOWED BIT(6) /* IBI and Hot-Join allowed whil= e runtime suspended */ #define HCI_QUIRK_RPM_PARENT_MANAGED BIT(7) /* Runtime PM managed by pare= nt device */ #define HCI_QUIRK_DMA_ABORT_REQUIRES_PIO_RESET BIT(8) /* Do PIO queue SW = resets after DMA abort */ +#define HCI_QUIRK_DMA_REQUIRES_HC_ABORT BIT(9) /* Use HC_CONTROL ABORT t= o abort DMA */ =20 /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); +void mipi_i3c_hci_abort(struct i3c_hci *hci); void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); void mipi_i3c_hci_pio_reset_all_queues(struct i3c_hci *hci); void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); 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charset="utf-8" Factor the reset-and-restore sequence out of i3c_hci_rpm_resume() into a separate helper. This allows the same logic to be reused for recovery paths in subsequent changes without duplicating suspend/resume handling. No functional change. Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/core.c | 21 +++++++++++++++++++-- drivers/i3c/master/mipi-i3c-hci/hci.h | 2 ++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 4c4e87a9b352..f745805d3c99 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -801,9 +801,8 @@ int i3c_hci_rpm_suspend(struct device *dev) } EXPORT_SYMBOL_GPL(i3c_hci_rpm_suspend); =20 -int i3c_hci_rpm_resume(struct device *dev) +static int i3c_hci_do_reset_and_restore(struct i3c_hci *hci) { - struct i3c_hci *hci =3D dev_get_drvdata(dev); int ret; =20 ret =3D i3c_hci_reset_and_init(hci); @@ -824,6 +823,24 @@ int i3c_hci_rpm_resume(struct device *dev) =20 return 0; } + +int i3c_hci_reset_and_restore(struct i3c_hci *hci) +{ + i3c_hci_bus_disable(hci); + + hci->io->suspend(hci); + + i3c_hci_sync_irq_inactive(hci); + + return i3c_hci_do_reset_and_restore(hci); +} + +int i3c_hci_rpm_resume(struct device *dev) +{ + struct i3c_hci *hci =3D dev_get_drvdata(dev); + + return i3c_hci_do_reset_and_restore(hci); +} EXPORT_SYMBOL_GPL(i3c_hci_rpm_resume); =20 static int i3c_hci_runtime_suspend(struct device *dev) diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index d542d03dc629..9b46453d6d4b 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -175,4 +175,6 @@ int i3c_hci_process_xfer(struct i3c_hci *hci, struct hc= i_xfer *xfer, int n); int i3c_hci_rpm_suspend(struct device *dev); int i3c_hci_rpm_resume(struct device *dev); =20 +int i3c_hci_reset_and_restore(struct i3c_hci *hci); + #endif --=20 2.51.0 From nobody Tue Jun 16 06:03:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C046433C19E for ; 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a="94778409" X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="94778409" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:40 -0700 X-CSE-ConnectionGUID: 3cP0svejQkq82VNFs1mslg== X-CSE-MsgGUID: TUV9eHPQR3KZndGOek/2+w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="235784640" Received: from abityuts-desk.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.222]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:38 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/16] i3c: mipi-i3c-hci: Add DMA-mode recovery for internal controller errors Date: Thu, 16 Apr 2026 20:57:00 +0300 Message-ID: <20260416175704.41217-13-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260416175704.41217-1-adrian.hunter@intel.com> References: <20260416175704.41217-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Handle internal I3C HCI errors when operating in DMA mode by adding a simple recovery mechanism. On detection of an internal controller error, mark recovery as needed and attempt to restore operation by performing a software reset followed by state restore. To keep recovery straightforward on this unlikely error path, all currently queued transfers are terminated and completed with an error. This allows the controller to resume operation after internal failures rather than remaining permanently stuck. Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/cmd.h | 6 ++ drivers/i3c/master/mipi-i3c-hci/core.c | 1 + drivers/i3c/master/mipi-i3c-hci/dma.c | 90 +++++++++++++++++++++++--- drivers/i3c/master/mipi-i3c-hci/hci.h | 1 + 4 files changed, 89 insertions(+), 9 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/cmd.h b/drivers/i3c/master/mip= i-i3c-hci/cmd.h index b1bf87daa651..7bada7b4b2de 100644 --- a/drivers/i3c/master/mipi-i3c-hci/cmd.h +++ b/drivers/i3c/master/mipi-i3c-hci/cmd.h @@ -65,4 +65,10 @@ struct hci_cmd_ops { extern const struct hci_cmd_ops mipi_i3c_hci_cmd_v1; extern const struct hci_cmd_ops mipi_i3c_hci_cmd_v2; =20 +static inline void hci_cmd_set_resp_err(u32 *response, int resp_err) +{ + *response &=3D ~RESP_ERR_FIELD; + *response |=3D FIELD_PREP(RESP_ERR_FIELD, resp_err); +} + #endif diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index f745805d3c99..89181a6a972d 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -668,6 +668,7 @@ static irqreturn_t i3c_hci_irq_handler(int irq, void *d= ev_id) if (val & INTR_HC_INTERNAL_ERR) { dev_err(&hci->master.dev, "Host Controller Internal Error\n"); val &=3D ~INTR_HC_INTERNAL_ERR; + hci->recovery_needed =3D true; } =20 if (val) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index c2f48024f175..6811503c869e 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -9,6 +9,7 @@ */ =20 #include +#include #include #include #include @@ -258,6 +259,10 @@ static void hci_dma_init_rh(struct i3c_hci *hci, struc= t hci_rh_data *rh, int i) rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE); rh_reg_write(RING_CONTROL, RING_CTRL_ENABLE | RING_CTRL_RUN_STOP); =20 + /* + * Do not clear the entries of rh->src_xfers because the recovery uses + * them. In other cases they should be NULL anyway. + */ rh->done_ptr =3D 0; rh->ibi_chunk_ptr =3D 0; rh->xfer_space =3D rh->xfer_entries; @@ -362,7 +367,7 @@ static int hci_dma_init(struct i3c_hci *hci) rh->resp =3D dma_alloc_coherent(rings->sysdev, resps_sz, &rh->resp_dma, GFP_KERNEL); rh->src_xfers =3D - kmalloc_objs(*rh->src_xfers, rh->xfer_entries); + kzalloc_objs(*rh->src_xfers, rh->xfer_entries); ret =3D -ENOMEM; if (!rh->xfer || !rh->resp || !rh->src_xfers) goto err_out; @@ -572,13 +577,15 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, st= ruct hci_rh_data *rh) hci_dma_unmap_xfer(hci, xfer, 1); rh->src_xfers[done_ptr] =3D NULL; xfer->ring_entry =3D -1; - xfer->response =3D resp; if (tid !=3D xfer->cmd_tid) { dev_err(&hci->master.dev, "response tid=3D%d when expecting %d\n", tid, xfer->cmd_tid); - /* TODO: do something about it? */ + hci->recovery_needed =3D true; + if (!RESP_STATUS(resp)) + hci_cmd_set_resp_err(&resp, RESP_ERR_HC_TERMINATED); } + xfer->response =3D resp; if (xfer =3D=3D xfer->completing_xfer || RESP_STATUS(resp)) complete(xfer->completing_xfer->completion); if (RESP_STATUS(resp)) @@ -635,6 +642,58 @@ static void hci_dma_unblock_enqueue(struct i3c_hci *hc= i) } } =20 +static void hci_dma_error_out_rh(struct i3c_hci *hci, struct hci_rh_data *= rh) +{ + /* + * The entries of rh->src_xfers are not cleared by + * i3c_hci_reset_and_restore(), so can be used here. + */ + for (int i =3D 0; i < rh->xfer_entries; i++) { + struct hci_xfer *xfer =3D rh->src_xfers[i]; + + if (!xfer) + continue; + hci_dma_unmap_xfer(hci, xfer, 1); + rh->src_xfers[i] =3D NULL; + xfer->ring_entry =3D -1; + hci_cmd_set_resp_err(&xfer->response, RESP_ERR_HC_TERMINATED); + if (xfer =3D=3D xfer->completing_xfer) + complete(xfer->completing_xfer->completion); + } +} + +static void hci_dma_error_out_all(struct i3c_hci *hci) +{ + struct hci_rings_data *rings =3D hci->io_data; + + for (int i =3D 0; i < rings->total; i++) + hci_dma_error_out_rh(hci, &rings->headers[i]); +} + +static void hci_dma_recovery(struct i3c_hci *hci) +{ + int ret; + + dev_err(&hci->master.dev, "Attempting to recover from internal errors\n"); + + for (int i =3D 0; i < 3; i++) { + ret =3D i3c_hci_reset_and_restore(hci); + if (!ret) + break; + dev_err(&hci->master.dev, "Reset and restore failed, error %d\n", ret); + /* Just in case the controller is busy, give it some time */ + msleep(1000); + } + + spin_lock_irq(&hci->lock); + hci_dma_error_out_all(hci); + hci_dma_unblock_enqueue(hci); + hci->recovery_needed =3D false; + spin_unlock_irq(&hci->lock); + + dev_err(&hci->master.dev, "Recovery %s\n", ret ? "failed!" : "done"); +} + static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, struct hci_xfer *xfer_list, int n) { @@ -650,6 +709,16 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { + /* + * The transfer may have already completed, especially + * if recovery has just run. Do nothing in that case. + */ + if (xfer_list->completing_xfer->ring_entry < 0 && + !hci->recovery_needed && !hci->enqueue_blocked && + ring_status =3D=3D (RING_STATUS_ENABLED | RING_STATUS_RUNNING)) { + spin_unlock_irq(&hci->lock); + return false; + } hci->enqueue_blocked =3D true; spin_unlock_irq(&hci->lock); /* stop the ring */ @@ -657,12 +726,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, spin_lock_irq(&hci->lock); ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { - /* - * We're deep in it if ever this condition is ever met. - * Hardware might still be writing to memory, etc. - */ - dev_crit(&hci->master.dev, "unable to abort the ring\n"); - WARN_ON(1); + dev_err(&hci->master.dev, "Unable to abort the DMA ring\n"); + hci->recovery_needed =3D true; } } =20 @@ -670,6 +735,13 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 hci_dma_xfer_done(hci, rh); =20 + if (hci->recovery_needed) { + hci->enqueue_blocked =3D true; + spin_unlock_irq(&hci->lock); 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charset="utf-8" When a transfer list is only partially completed due to an error, hci_dma_dequeue_xfer() overwrites the remaining DMA ring entries with NoOp commands and restarts the ring to flush them out. While NoOp commands are expected to complete successfully, they may still fail to complete if the DMA ring is stuck. Explicitly wait for the NoOp commands to finish, and trigger controller recovery if they do not complete or report an error. This ensures that partially completed transfer lists are reliably resolved and that a stuck ring is recovered promptly. Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/dma.c | 37 ++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 6 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 6811503c869e..053e487b6257 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -694,11 +694,33 @@ static void hci_dma_recovery(struct i3c_hci *hci) dev_err(&hci->master.dev, "Recovery %s\n", ret ? "failed!" : "done"); } =20 +static bool hci_dma_wait_for_noop(struct i3c_hci *hci, struct hci_xfer *xf= er_list, int n, + int noop_pos) +{ + struct completion *done =3D xfer_list->completing_xfer->completion; + bool timeout =3D !wait_for_completion_timeout(done, HZ); + u32 error =3D timeout; + + for (int i =3D noop_pos; i < n && !error; i++) + error =3D RESP_STATUS(xfer_list[i].response); + + if (!error) + return true; + + if (timeout) + dev_err(&hci->master.dev, "NoOp timeout error\n"); + else + dev_err(&hci->master.dev, "NoOp error %u\n", error); + + return false; +} + static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, struct hci_xfer *xfer_list, int n) { struct hci_rings_data *rings =3D hci->io_data; struct hci_rh_data *rh =3D &rings->headers[xfer_list[0].ring_number]; + int noop_pos =3D -1; unsigned int i; bool did_unqueue =3D false; u32 ring_status; @@ -706,7 +728,7 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, guard(mutex)(&hci->control_mutex); =20 spin_lock_irq(&hci->lock); - +restart: ring_status =3D rh_reg_read(RING_STATUS); if (ring_status & RING_STATUS_RUNNING) { /* @@ -762,11 +784,8 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, *ring_data++ =3D 0; } =20 - /* disassociate this xfer struct */ - rh->src_xfers[idx] =3D NULL; - - /* and unmap it */ - hci_dma_unmap_xfer(hci, xfer, 1); + if (noop_pos < 0) + noop_pos =3D i; =20 did_unqueue =3D true; } @@ -799,6 +818,12 @@ static bool hci_dma_dequeue_xfer(struct i3c_hci *hci, =20 wait_for_completion_timeout(&rh->op_done, HZ); =20 + if (did_unqueue && !hci_dma_wait_for_noop(hci, xfer_list, n, noop_pos)) { + spin_lock_irq(&hci->lock); + hci->recovery_needed =3D true; + goto restart; + } + return did_unqueue; } =20 --=20 2.51.0 From nobody Tue Jun 16 06:03:24 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7289333F8B7 for ; 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a="94778421" X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="94778421" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:44 -0700 X-CSE-ConnectionGUID: oWHDSDuVQgClZFERoMv0Vg== X-CSE-MsgGUID: 8JnowKm/R1+X7IoCAhTEDQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,181,1770624000"; d="scan'208";a="235784659" Received: from abityuts-desk.ger.corp.intel.com (HELO ahunter6-desk) ([10.245.244.222]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Apr 2026 10:57:43 -0700 From: Adrian Hunter To: alexandre.belloni@bootlin.com Cc: Frank.Li@nxp.com, linux-i3c@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 14/16] i3c: mipi-i3c-hci: Base timeouts on actual transfer start time Date: Thu, 16 Apr 2026 20:57:02 +0300 Message-ID: <20260416175704.41217-15-adrian.hunter@intel.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260416175704.41217-1-adrian.hunter@intel.com> References: <20260416175704.41217-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Transfer timeouts are currently measured from the point where a transfer list is queued to the controller. This can cause transfers to time out before they have actually started, if earlier queued transfers consume the timeout interval. Fix this by recording when a transfer reaches the head of the queue and adjusting the timeout calculation to start from that point. The existing low-overhead completion-based timeout mechanism is preserved, but care is taken to ensure the transfer start time is consistently recorded for both PIO and DMA paths. This prevents premature timeouts while retaining efficient timeout handling. Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/core.c | 19 ++++++++++++++++++- drivers/i3c/master/mipi-i3c-hci/dma.c | 9 +++++++++ drivers/i3c/master/mipi-i3c-hci/hci.h | 11 +++++++++++ drivers/i3c/master/mipi-i3c-hci/pio.c | 3 +++ 4 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/core.c b/drivers/i3c/master/mi= pi-i3c-hci/core.c index 89181a6a972d..7f3e70bfffc1 100644 --- a/drivers/i3c/master/mipi-i3c-hci/core.c +++ b/drivers/i3c/master/mipi-i3c-hci/core.c @@ -275,13 +275,30 @@ int i3c_hci_process_xfer(struct i3c_hci *hci, struct = hci_xfer *xfer, int n) { struct completion *done =3D xfer[n - 1].completion; unsigned long timeout =3D xfer[n - 1].timeout; + unsigned long remaining_timeout =3D timeout; + long time_taken; + bool started; int ret; =20 + xfer[0].started =3D false; + ret =3D hci->io->queue_xfer(hci, xfer, n); if (ret) return ret; =20 - if (!wait_for_completion_timeout(done, timeout)) { + while (!wait_for_completion_timeout(done, remaining_timeout)) { + scoped_guard(spinlock_irqsave, &hci->lock) { + started =3D xfer[0].started; + time_taken =3D jiffies - xfer[0].start_time; + } + /* Keep waiting if xfer has not started */ + if (!started) + continue; + /* Recalculate timeout based on actual start time */ + if (time_taken < timeout) { + remaining_timeout =3D timeout - time_taken; + continue; + } if (hci->io->dequeue_xfer(hci, xfer, n)) { dev_err(&hci->master.dev, "%s: timeout error\n", __func__); return -ETIMEDOUT; diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 053e487b6257..527c282e0734 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -543,6 +543,9 @@ static int hci_dma_queue_xfer(struct i3c_hci *hci, enqueue_ptr =3D (enqueue_ptr + 1) % rh->xfer_entries; } =20 + if (rh->xfer_space =3D=3D rh->xfer_entries) + hci_start_xfer(xfer_list); + rh->xfer_space -=3D n; =20 op1_val &=3D ~RING_OP1_CR_ENQ_PTR; @@ -588,6 +591,8 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, stru= ct hci_rh_data *rh) xfer->response =3D resp; if (xfer =3D=3D xfer->completing_xfer || RESP_STATUS(resp)) complete(xfer->completing_xfer->completion); + else + hci_start_xfer(xfer); if (RESP_STATUS(resp)) hci->enqueue_blocked =3D true; } @@ -598,6 +603,10 @@ static void hci_dma_xfer_done(struct i3c_hci *hci, str= uct hci_rh_data *rh) } =20 rh->xfer_space +=3D done_cnt; + if (rh->xfer_space < rh->xfer_entries) { + xfer =3D rh->src_xfers[done_ptr]; + hci_start_xfer(xfer); + } op1_val =3D rh_reg_read(RING_OPERATION1); op1_val &=3D ~RING_OP1_CR_SW_DEQ_PTR; op1_val |=3D FIELD_PREP(RING_OP1_CR_SW_DEQ_PTR, done_ptr); diff --git a/drivers/i3c/master/mipi-i3c-hci/hci.h b/drivers/i3c/master/mip= i-i3c-hci/hci.h index 1344c469c2e2..ecf2dcc0b004 100644 --- a/drivers/i3c/master/mipi-i3c-hci/hci.h +++ b/drivers/i3c/master/mipi-i3c-hci/hci.h @@ -11,6 +11,7 @@ #define HCI_H =20 #include +#include =20 /* 32-bit word aware bit and mask macros */ #define W0_MASK(h, l) GENMASK((h) - 0, (l) - 0) @@ -88,11 +89,13 @@ struct hci_xfer { u32 cmd_desc[4]; u32 response; bool rnw; + bool started; void *data; unsigned int data_len; unsigned int cmd_tid; struct completion *completion; unsigned long timeout; + unsigned long start_time; union { struct { /* PIO specific */ @@ -123,6 +126,14 @@ static inline void hci_free_xfer(struct hci_xfer *xfer= , unsigned int n) kfree(xfer); } =20 +static inline void hci_start_xfer(struct hci_xfer *xfer) +{ + if (!xfer->started) { + xfer->started =3D true; + xfer->start_time =3D jiffies; + } +} + /* This abstracts PIO vs DMA operations */ struct hci_io_ops { bool (*irq_handler)(struct i3c_hci *hci); diff --git a/drivers/i3c/master/mipi-i3c-hci/pio.c b/drivers/i3c/master/mip= i-i3c-hci/pio.c index 8f48a81e65ab..d4779c17d433 100644 --- a/drivers/i3c/master/mipi-i3c-hci/pio.c +++ b/drivers/i3c/master/mipi-i3c-hci/pio.c @@ -605,6 +605,9 @@ static bool hci_pio_process_cmd(struct i3c_hci *hci, st= ruct hci_pio_data *pio) * Finally send the command. */ hci_pio_write_cmd(hci, pio->curr_xfer); + + pio->curr_xfer->start_time =3D jiffies; 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charset="utf-8" dma_alloc_coherent() allocates memory in whole pages, which can waste space when command and response queues are allocated separately. Allocate the DMA command and response queues from a single coherent allocation instead, while preserving the required 4-byte alignment. This reduces memory overhead without changing behavior. Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/dma.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index 527c282e0734..b06405a9aa7b 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -186,14 +186,12 @@ static void hci_dma_free(void *data) for (int i =3D 0; i < rings->total; i++) { rh =3D &rings->headers[i]; =20 - if (rh->xfer) - dma_free_coherent(rings->sysdev, - rh->xfer_struct_sz * rh->xfer_entries, - rh->xfer, rh->xfer_dma); - if (rh->resp) - dma_free_coherent(rings->sysdev, - rh->resp_struct_sz * rh->xfer_entries, - rh->resp, rh->resp_dma); + if (rh->xfer) { + size_t sz =3D round_up(rh->xfer_struct_sz * rh->xfer_entries, 4); + + sz +=3D rh->resp_struct_sz * rh->xfer_entries; + dma_free_coherent(rings->sysdev, sz, rh->xfer, rh->xfer_dma); + } kfree(rh->src_xfers); if (rh->ibi_status) dma_free_coherent(rings->sysdev, @@ -359,17 +357,17 @@ static int hci_dma_init(struct i3c_hci *hci) dev_dbg(&hci->master.dev, "xfer_struct_sz =3D %d, resp_struct_sz =3D %d", rh->xfer_struct_sz, rh->resp_struct_sz); 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charset="utf-8" The DMA transfer ring is currently limited to 16 entries, despite the MIPI I3C HCI supporting up to 32 devices. When the ring lacks space for a new transfer list, the driver returns -EBUSY, which can be unexpected for clients. Increase the DMA transfer ring size to the maximum supported value of 255 entries. This effectively eliminates ring-space exhaustion in practice and avoids the complexity of adding secondary queuing mechanisms. Even at the maximum size, the memory overhead remains small (approximately 24 bytes per entry by default). Signed-off-by: Adrian Hunter --- drivers/i3c/master/mipi-i3c-hci/dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/i3c/master/mipi-i3c-hci/dma.c b/drivers/i3c/master/mip= i-i3c-hci/dma.c index b06405a9aa7b..fdab1e2df19c 100644 --- a/drivers/i3c/master/mipi-i3c-hci/dma.c +++ b/drivers/i3c/master/mipi-i3c-hci/dma.c @@ -27,7 +27,7 @@ */ =20 #define XFER_RINGS 1 /* max: 8 */ -#define XFER_RING_ENTRIES 16 /* max: 255 */ +#define XFER_RING_ENTRIES 255 /* max: 255 */ =20 #define IBI_RINGS 1 /* max: 8 */ #define IBI_STATUS_RING_ENTRIES 32 /* max: 255 */ --=20 2.51.0