From nobody Sat Jun 13 07:47:13 2026 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DF5A53E0C44 for ; Thu, 16 Apr 2026 14:42:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776350566; cv=none; b=MofPUc7JNmBY4uut06ZzcsZTtkfEl2mCYgWNMPi1Y1IAf+zawfJsAA8eLT0DZgggOOX4y8PVL/00/b390+7jHIhR26h7nfUS/Bn0Jos3q18prNeFA/8YluYFIBAPbKLLnSXcq8SMihk3S8U1GawiVOxoHUPECcH0PuCAIJOBzUM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776350566; c=relaxed/simple; bh=lNett6iejLsfwaJeQ80UJS5S0wekv6jUzKXG7ijjLbc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=myUtXmTtC7+d4jx05YiYPQrTRb+T4WCqKQIVYXhRXQE2mTvguN4vcC9HvIM+jLNHE6sl2Yna+jXbczCOnA90WUfSiLDX1lgCwcAshzbjEDGFar7FhaIc/OmvGjKbsfDxCIpO7Q5qKdRPXR+0Y92i1a+5Z+6KrEqmmBvkrvjaIDU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ShEDho6o; arc=none smtp.client-ip=209.85.218.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ShEDho6o" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-b9c3e2cf3c0so1263235766b.1 for ; Thu, 16 Apr 2026 07:42:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1776350563; x=1776955363; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0dQoW9IEupnPf0vdvP3gC5QucYExC5rqYZAdJ429kig=; b=ShEDho6olUVEGBGJTjv3+w+BA5wC8srcrSKeNBKhnsFxynGAp6YsmeQI7Bk9O9O0iM 9dYoJLB5Al0zxwad1/Z6FciSpvNcFpdj2FSI/B6H+dlmpP0zGGYdXv1vPKqw+Jiy4+Ti BmEd9/btKmDk2gERdxIKF5YaZsODlQEeZXqlWr9BkQlQtaqhE72SZmblRvDIRhgRVVD8 R2/xav8sAvGhKQ1qbd2IlcNxKpdE4WL48SwEbUO47poXmDeJAtE/UtUPxrA/dAgRGKEQ 4Zw0F9X88R1Vkf3p9lcO45c0pO+KSIL+jVaGDXmWndDu9kVdgEbmFQYFwYOL2o72aWNP CYAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776350563; x=1776955363; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=0dQoW9IEupnPf0vdvP3gC5QucYExC5rqYZAdJ429kig=; b=dU5wH6uYN70LbBfPgYXlLKbaG79LxcHEcCOOu8fhidsZbr1xU8EzoICTnAxUUTYed/ TUeBIuSkQS1YTyGCWfiTa6eYb9Pd1ZBh3qe9REjqsJGy/YR5i/4GJh+gr4G9rdNVIsYh t/myUPxRXDonpvAwj2dn4HxML8GUXMzHjp4NYzoiIYmW+5U6riQBtW/G8Ucs+uZlJ/80 7h8RCwG2ggjTyePmXwrUb1R53pUMQUTtZTDN5GwVj8ccw7kHJbEx9QD7Dsm1yf305OjP bkiWtlKxhbJEfj3kHd0aalm6UYx3pcJ7T5cF/yB8lqJQdLsD6LiisPoRRz2jepn4b4jN UAiw== X-Forwarded-Encrypted: i=1; AFNElJ8tVBrlYu9YrhRLMvP9dheofFayeHz0cDfiD0dl/TycBfgoENMDVD1pkNUn3lEiB2W97Msl6w1R8yhUcvk=@vger.kernel.org X-Gm-Message-State: AOJu0YzwFLOOJNEJCWNXGeOu12kdoWFtJrfEhf6bRQtUD267gJ27idCm CAu573eUM/v/IYJGSJOzOdRN4shbSabqhEt67wLrMrsXmbkQo5lB5PXW X-Gm-Gg: AeBDieupZMdXqPL1YeVFwoEaaOz/b1+0g48JWOiiZYiaZbWVcUKqQSuK6iHTIgYzS+M BfjG1l2ubeDb8HyXBIySiX9HDGoTdlSz4Ciq/PWmAmthTiLvOKjE1u4MjzeaNxeRS71DuFVG/ba 1N/ObbknCCz8/kmgebdSnR0ZW9nvC6yK1fETJNOQPhFF6bPff+5FKEPg5WrMMf18s3aVDwjcPDG pEDL4fQRRPaM8Cvt6v/yHbP4Uk1YCFe/AMD35hAtPiaYJtcZM1+p8/Z2GVFrQ5dPYKZieGiWpGF 57riK3slTKcgVGMqkksfeOCwQhnHMP+7ARalZzhCgQFxEu8tJNf7MfypC8HlSPUHS95gBAf2S1g F/aYShnjAoJq7XaJdbYMm9bq/QzGtn+pFjBHjHlMBdBkDenSP6BIxn4tOTz1w9vx4dkvgaZB3V0 8k3PQZRODK8XHNFBuUO3kIXu32qhdfFvErEoJS X-Received: by 2002:a17:906:99d0:b0:b98:a49:a22e with SMTP id a640c23a62f3a-b9d727fcc57mr1457033066b.36.1776350563046; Thu, 16 Apr 2026 07:42:43 -0700 (PDT) Received: from iris-Ian.. ([2a00:20:636a:3838:3bf9:3a9b:8000:4975]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ba2a112cc9csm90502766b.40.2026.04.16.07.42.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2026 07:42:42 -0700 (PDT) From: iansdannapel@gmail.com To: linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: mdf@kernel.org, yilun.xu@intel.com, trix@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, heiko@sntech.de, marex@nabladev.com, prabhakar.mahadev-lad.rj@bp.renesas.com, dev@kael-k.io, Ian Dannapel , Conor Dooley , Alexander Dahl Subject: [PATCH v7 1/3] dt-bindings: vendor-prefix: Add prefix for Efinix, Inc. Date: Thu, 16 Apr 2026 16:42:34 +0200 Message-ID: <20260416144237.373852-2-iansdannapel@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260416144237.373852-1-iansdannapel@gmail.com> References: <20260416144237.373852-1-iansdannapel@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ian Dannapel Add entry for Efinix, Inc. (https://www.efinixinc.com/) Signed-off-by: Ian Dannapel Acked-by: Conor Dooley Acked-by: Alexander Dahl --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 00bffb9c4469..9e20384ff624 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -485,6 +485,8 @@ patternProperties: description: Emtop Embedded Solutions "^eeti,.*": description: eGalax_eMPIA Technology Inc + "^efinix,.*": + description: Efinix, Inc. "^egnite,.*": description: egnite GmbH "^einfochips,.*": --=20 2.43.0 From nobody Sat Jun 13 07:47:13 2026 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0AB93BD64D for ; Thu, 16 Apr 2026 14:42:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776350572; cv=none; b=lLpnp0BU7gwGoEvWdBJ6Z1v1fyzsdNsNcHoUyRug6SUV6HrPKjirrgw2XbivxpwWL4NKg8oMGJEFEmJqBrFpsvfQmJicHAtDs9TZU3xLbPbsBzfUeqcucGUDWf6W2QuoOaM2petYifuVyxIPOpu+jb69ToGQ11HbMRRpyRfJ2uM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776350572; c=relaxed/simple; bh=xrrPdpYsYhy0eGksuw8CEsG6UEANm6hhyh3Ohzaysz4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iok3pRzpsE2YW106uJBkC5Zyf0xAbFy6Vkkh4dHu42glSi27oiqT4P+u9t1NBQ4R3mJt7tBUxSP7aSPHk9ICXK9bF8y0mzr5XEGGFTGIaBcM8tvgIQlrCv1N4YRJtMA2oz0MGdcU4x2t7fckKtcBTb35X1WzUZ9p8R1c+bt1LOA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=io+yRIDm; arc=none smtp.client-ip=209.85.218.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="io+yRIDm" Received: by mail-ej1-f49.google.com with SMTP id a640c23a62f3a-b8d7f22d405so1323190066b.0 for ; Thu, 16 Apr 2026 07:42:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1776350569; x=1776955369; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wpzCqOy3BCsfajpy7vpm92RCmf0w4xV2D9F85Ngay0g=; b=io+yRIDmtKgQ3maPFTVDH9qg5FC6K0I8jW0mbHGwvPXRTOXpoOB0duG1DmAJtfc8Pz FABa1eU76JOg/VA1a7Bl55LFfvxpBvJmjZ2zL6tuEBAcKkUWljp0XSbYDhqZwENXSk2v ZMydh+JkEVmvXTjmfGCCrNf7E1NoOvwqxoF2x86xcSOHM8x+ao1DMPk8Ca8tsdLmikkd kIQbOUWwklJXaaRyTOTOFH+ggjDvng3D8PrWSQVYdU5kYvj8VJq5e18NBuxNmodrI1pw Jy21Wt3RspcBeKaIqo71IJgmP37zHzcfMzidbQ7JwHSVoABHqtQYf1znn89ctvNufdHg lNEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776350569; x=1776955369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=wpzCqOy3BCsfajpy7vpm92RCmf0w4xV2D9F85Ngay0g=; b=k3YH81jQrqQbPdR8pbcPt8UXYk0Rqbl+i2gaRUGcP3+gA35qdYxd0qhY+FEf5DMD5A U1AJNtVGFcfzgJWYMDVX5CgyfLqcNjhtiXXOdjZQZEMcnPS/AqS8BiiK/YLQSoW6hPWf l2EzqWvP8AVUlZN/38ygKX5WQuow09CgFrbBm9VHrVm4GTz/FYRhy9JUMmgxNlVaEfnr eEIFyJ/9TTJ2OcL66ujWdHpdZTGTx/uNikgpO9Oc8v3mznGbT1oz+nnCijQXVaonMH5X TrsHJWxOtpQrvnKvP/Me9LWADnmFoOfVF9Qk8p0/LG+R6rZXIy+ZWhFLYPUDQWlYeuVX Oytw== X-Forwarded-Encrypted: i=1; AFNElJ9okLpyJm8+WnzwiAVpn733uXXxrx6TmXQZvE84CwiBwvg05IdghzMEA6DkuUm/poQ+UwO0iwMdYXiZhvE=@vger.kernel.org X-Gm-Message-State: AOJu0YzWOlVtXhImCTKg6S/a326LrvqBIzM1IgYbMUv01en5YfWeQJAU BDxa1fURWq/CylYLHAemBGzW/LnKK4cVz6IdrO6iri5iH+VcjtoJcjuU X-Gm-Gg: AeBDietemBUXb0H4NiNBDFsm6fHT715rH3T9t7GubB/QyTEYZcBqvmAh4gN2OJEz5h4 Sw/xwSUY70G6X8abzD9NqbPvkqY8RY03t1Gwc3ahyuygGIooIQhr3hwQZPusfTW6pfQ/h8stfce dCAFYKaLLqS0tpRNzEcd2Z1btbSZA590+xnZMBlSN+Lz8WEoRG/T8/DLW5d4LrT8YzgZSsxGa2d M/jR93tu20QDqkOXCTNeLKX0RxGSlH59ETjx+qOxgJ5GbJcxjL1j6LfRKiKwDZsBmQ+vLL5c5Ht zge4559CA5vfTqaIGYSH2kGP9hlB0gpuT3HYQ93hfZLIaobHzvyWYYtvBklo/BYyIeyBg/rbZTZ YvcVbBbYJoXmTxXarR1Eu6ajZYxhediFwTUaxlofCtUlmsd7dRMRt0Rw5hitSZDK5Xtry6ytH32 urUJwTNsZj9aRPrTTu/scuCDp2fLdBJpptC0exAUrK6mC9Xrw= X-Received: by 2002:a17:907:3e88:b0:b97:c684:57db with SMTP id a640c23a62f3a-b9d72792a5dmr1601267366b.12.1776350568737; Thu, 16 Apr 2026 07:42:48 -0700 (PDT) Received: from iris-Ian.. ([2a00:20:636a:3838:3bf9:3a9b:8000:4975]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ba2a112cc9csm90502766b.40.2026.04.16.07.42.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2026 07:42:48 -0700 (PDT) From: iansdannapel@gmail.com To: linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: mdf@kernel.org, yilun.xu@intel.com, trix@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, heiko@sntech.de, marex@nabladev.com, prabhakar.mahadev-lad.rj@bp.renesas.com, dev@kael-k.io, Ian Dannapel Subject: [PATCH v7 2/3] dt-bindings: fpga: Add Efinix SPI programming bindings Date: Thu, 16 Apr 2026 16:42:35 +0200 Message-ID: <20260416144237.373852-3-iansdannapel@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260416144237.373852-1-iansdannapel@gmail.com> References: <20260416144237.373852-1-iansdannapel@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Ian Dannapel Add device tree bindings documentation for configuring Efinix FPGA using serial SPI passive programming mode. Signed-off-by: Ian Dannapel Acked-by: Conor Dooley --- .../bindings/fpga/efinix,trion-config.yaml | 98 +++++++++++++++++++ 1 file changed, 98 insertions(+) create mode 100644 Documentation/devicetree/bindings/fpga/efinix,trion-con= fig.yaml diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-config.yam= l b/Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml new file mode 100644 index 000000000000..7c7444ff9c3a --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/efinix,trion-config.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Efinix SPI FPGA Manager + +maintainers: + - Ian Dannapel + +description: | + Efinix FPGAs (Trion, Topaz, and Titanium families) support loading bitst= reams + through "SPI Passive Mode". + Additional pin hogs for bus width configuration should be set + elsewhere, if necessary. + + References: + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.3.pdf + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.8.p= df + - https://www.efinixinc.com/docs/an061-configuring-topaz-fpgas-v1.1.pdf + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - efinix,titanium-config + - efinix,topaz-config + - const: efinix,trion-config + - const: efinix,trion-config + + spi-cpha: true + + spi-cpol: true + + spi-max-frequency: + maximum: 25000000 + + reg: + maxItems: 1 + + reset-gpios: + description: + reset and re-configuration trigger pin (low active) + maxItems: 1 + + cdone-gpios: + description: + optional configuration done status pin (high active) + maxItems: 1 + +required: + - compatible + - reg + - reset-gpios + - spi-cpha + - spi-cpol + +unevaluatedProperties: false + +examples: + - | + #include + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + cs-gpios =3D <&gpio5 13 GPIO_ACTIVE_LOW>; + fpga-mgr@0 { + compatible =3D "efinix,trion-config"; + reg =3D <0>; + spi-max-frequency =3D <25000000>; + spi-cpha; + spi-cpol; + reset-gpios =3D <&gpio4 17 GPIO_ACTIVE_LOW>; + cdone-gpios =3D <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; + - | + #include + spi { + #address-cells =3D <1>; + #size-cells =3D <0>; + cs-gpios =3D <&gpio5 13 GPIO_ACTIVE_LOW>; + fpga-mgr@0 { + compatible =3D "efinix,titanium-config", "efinix,trion-config"; + reg =3D <0>; + spi-max-frequency =3D <25000000>; + spi-cpha; + spi-cpol; + reset-gpios =3D <&gpio4 17 GPIO_ACTIVE_LOW>; + cdone-gpios =3D <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; +... --=20 2.43.0 From nobody Sat Jun 13 07:47:13 2026 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0F003E0C66 for ; Thu, 16 Apr 2026 14:42:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776350575; cv=none; b=mw0ZSamka6H5syfHXSvcmbMbOmaX499+JsIj06fjkHsQlStBx5V1jIcs3bL7WAUUp0jNi6a8YODxFJJKwvYl5uH2wQnEjueeOWFtFV0iG2P19V0vBPBV6t/C+lmo2c5dBb19P+2XirQqcif52km3UrSzQ8VP2Gmy8yGAj83yfvA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776350575; c=relaxed/simple; bh=/uDCrP20+RBLonFnmFHSKcrJz/plgbzxI5gtj236sBs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=k2P8otE09QrU7km2dhWOMSMqRoNINiYUEMDzUUo8dqwdpbbdBFr5Z2KRXSxJjP6vluaDttE1hHKxAE/T0WLC5DEUFagYLKjIDgeKmmOV46kOwHR5uCcBtJWl2S+BuzHBtsoVKq5IxOSPBr9HWHLaNtbOYNDbDmpzydyYXLB/e5c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=CS4ONn07; arc=none smtp.client-ip=209.85.208.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="CS4ONn07" Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-671a2f4fd28so6570418a12.3 for ; Thu, 16 Apr 2026 07:42:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1776350572; x=1776955372; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6pcCmYhJDdOosRH1EaiacreI0Vn1NfK5R9o/k5rgKLY=; b=CS4ONn07TcW+Lv3TDZj4fawfxXZrN4v7mDvBgZc+DEZuKZerNcb6EfzepqugOplzxN 5ZBxMzLF3NE7Tz1L/UEIsr/mgkvT5Ph06y7dOvAtahd3JKFArD0SR3vmpFKgHHML1py1 vFfTSZxcT892jBSNaxqPI4APtmhs0kAkeudYnytk6ndy/KI3pbs4XvexA05Aiwz36CK6 tnowmYASz/qn7usBXt80kF9BqgHVr17WnkW8rfnu48rj8MxLzkk1+jIRtEwVeLwMdJwg ykWdrHo7Thbz3trFMq9gJNqJaD8RSga2cfqhZsQ/KS4P9q2ap4W1431nl8AFab4EFXZO M2cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776350572; x=1776955372; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=6pcCmYhJDdOosRH1EaiacreI0Vn1NfK5R9o/k5rgKLY=; b=nX4PqaovviWFvjFVbiKzr70HqYbSQM3T4xTlE/Boh7itMUJ2I37+DhvTwGJLyiulFO ak2S4EdUg7nobpDuM2oH6/8+6tw9QnLbnYz6HDTpWBnaER8NuBomW67qkw6kYXpYHyD0 knGS8sYzQcKW9MhziSpWffOvC6EkXyisZcMBPamc/sMzRJfNDhrVLk/R7BLWruIG9ldC YV7QMRYLjiv8ozHkFm/pkcxs7V03Ot7ITUQs61BIZPKZ8P0/j1LBuEtW/F+fXynlpJZI nS8KQmrtkFjZgIHBA5YlLT5AANDGHAqqMh5f1jpRY23lCfPAqZG3rByyI5jb1EAf9Va7 9VYQ== X-Forwarded-Encrypted: i=1; AFNElJ+pj9ggm/rvwwgdX6oTyAQ35xR68RQIH39Hv4NfqVJdlgixS61rnzoxM0fKt703Wlqcq3k6bQLoN0EzSE8=@vger.kernel.org X-Gm-Message-State: AOJu0YxM8Ue5/lTSoROdo/mRyb23arEKEjIvf2+uKObAGLhLDYGgILOH SOUzpMW9B5b13izNSb+STwFzRQ3iA7zTqmKr//ZL+ZEdGwKFkbRpicoF X-Gm-Gg: AeBDietBq/FXOw0Un7eo+BF9hqzbDcEAUs8ld6FChNEoC+cz/BeblbrzNzgxeur+2Ok X1R77egVtb45K1KllYlgxU2W+/KgHNFYXxm7wFKsPHL4OI7C/mWmeFhcbjULY1RB5f+WmjFLNsv xwgQtwWAZ23ntAp89k7L+xFqVuk9JQXdW9FChOCP1NLETlsrTpT/P8DD+aFFjOku8JFkxybb7+S CL3f5P+/kHRhGybYWXvRFt50rKmbnbAVY3MR98JwcYC3RB4ZaCGtECztj5vc/vTDl6Gavttfrnj vN5aXl6N8Q2RXCCOqYgyP6Yg2TuyPK88FG62MarkjSO5Qlv2jWFka3zIOp312faBQ+Ppu/LPNma kLy8Hr/1uGz+6smqviKrXn8T9I5ftGkO/i3DmQCyTSaOTPp5wBFh4W1zkYVrYgdjYIn+CRBw0QD 94Rj7BTXIvXDPv/KGCBOObc8JxSkbM3NN7C4Nu X-Received: by 2002:a17:907:a604:b0:b9d:1a1c:a664 with SMTP id a640c23a62f3a-b9d72991a2dmr1691584266b.40.1776350571983; Thu, 16 Apr 2026 07:42:51 -0700 (PDT) Received: from iris-Ian.. ([2a00:20:636a:3838:3bf9:3a9b:8000:4975]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ba2a112cc9csm90502766b.40.2026.04.16.07.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2026 07:42:51 -0700 (PDT) From: iansdannapel@gmail.com To: linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: mdf@kernel.org, yilun.xu@intel.com, trix@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, neil.armstrong@linaro.org, heiko@sntech.de, marex@nabladev.com, prabhakar.mahadev-lad.rj@bp.renesas.com, dev@kael-k.io, Ian Dannapel Subject: [PATCH v7 3/3] fpga-mgr: Add Efinix SPI programming driver Date: Thu, 16 Apr 2026 16:42:36 +0200 Message-ID: <20260416144237.373852-4-iansdannapel@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260416144237.373852-1-iansdannapel@gmail.com> References: <20260416144237.373852-1-iansdannapel@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable From: Ian Dannapel Add a new driver for loading binary firmware to configuration RAM using "SPI passive mode" on Efinix FPGAs. Efinix passive SPI configuration requires chip select to remain asserted from reset until the complete bitstream and trailing idle clocks have been transferred, so the driver keeps CS active with cs_change and locks the SPI bus for the duration of configuration. Signed-off-by: Ian Dannapel Reviewed-by: Xu Yilun --- drivers/fpga/Kconfig | 7 + drivers/fpga/Makefile | 1 + drivers/fpga/efinix-spi.c | 260 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 268 insertions(+) create mode 100644 drivers/fpga/efinix-spi.c diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 37b35f58f0df..748fc210c135 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -288,6 +288,13 @@ config FPGA_MGR_LATTICE_SYSCONFIG_SPI FPGA manager driver support for Lattice FPGAs programming over slave SPI sysCONFIG interface. =20 +config FPGA_MGR_EFINIX_SPI + tristate "Efinix FPGA configuration over SPI" + depends on SPI + help + FPGA manager driver support for Efinix FPGAs configuration over SPI + (passive mode only). + source "drivers/fpga/tests/Kconfig" =20 endif # FPGA diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index aeb89bb13517..6f5798b27e0d 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -26,6 +26,7 @@ obj-$(CONFIG_FPGA_MGR_LATTICE_SYSCONFIG) +=3D lattice-sys= config.o obj-$(CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI) +=3D lattice-sysconfig-spi.o obj-$(CONFIG_ALTERA_PR_IP_CORE) +=3D altera-pr-ip-core.o obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) +=3D altera-pr-ip-core-plat.o +obj-$(CONFIG_FPGA_MGR_EFINIX_SPI) +=3D efinix-spi.o =20 # FPGA Secure Update Drivers obj-$(CONFIG_FPGA_M10_BMC_SEC_UPDATE) +=3D intel-m10-bmc-sec-update.o diff --git a/drivers/fpga/efinix-spi.c b/drivers/fpga/efinix-spi.c new file mode 100644 index 000000000000..ed9a41232a32 --- /dev/null +++ b/drivers/fpga/efinix-spi.c @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * FPGA Manager Driver for Efinix + * + * Copyright (C) 2025 iris-GmbH infrared & intelligent sensors + * + * Ian Dannapel + * + * Load Efinix FPGA firmware over SPI using the serial configuration inter= face. + * + * Note: Only passive mode (host initiates transfer) is currently supporte= d. + */ + +#include +#include +#include +#include +#include +#include + +/* + * 13 dummy bytes generate 104 SPI clock cycles (8 bits each). + * Used to meet the requirement for >100 clock cycles idle sequence. + */ +#define EFINIX_SPI_IDLE_CYCLES_BYTES 13 + +/* + * tDMIN: Minimum time between deassertion of CRESET_N to first + * valid configuration data. (32 =C2=B5s) + */ +#define EFINIX_TDMIN_US_MIN 35 +#define EFINIX_TDMIN_US_MAX 40 + +/* + * tCRESET_N: Minimum CRESET_N low pulse width required to + * trigger re-configuration. (320 ns) + */ +#define EFINIX_TCRESETN_DELAY_MIN_US 1 +#define EFINIX_TCRESETN_DELAY_MAX_US 2 + +/* + * tUSER: Minimum configuration duration after CDONE goes high + * before entering user mode. (25 =C2=B5s) + */ +#define EFINIX_TUSER_US_MIN 30 +#define EFINIX_TUSER_US_MAX 35 + +struct efinix_spi_conf { + struct spi_device *spi; + struct gpio_desc *cdone; + struct gpio_desc *reset; +}; + +static void efinix_spi_reset(struct efinix_spi_conf *conf) +{ + gpiod_set_value(conf->reset, 1); + usleep_range(EFINIX_TCRESETN_DELAY_MIN_US, EFINIX_TCRESETN_DELAY_MAX_US); + gpiod_set_value(conf->reset, 0); + usleep_range(EFINIX_TDMIN_US_MIN, EFINIX_TDMIN_US_MAX); +} + +static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr) +{ + struct efinix_spi_conf *conf =3D mgr->priv; + + if (conf->cdone && gpiod_get_value(conf->cdone) =3D=3D 1) + return FPGA_MGR_STATE_OPERATING; + + return FPGA_MGR_STATE_UNKNOWN; +} + +static int efinix_spi_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + struct efinix_spi_conf *conf =3D mgr->priv; + struct spi_transfer assert_cs =3D { + /* Keep CS asserted across configuration. */ + .cs_change =3D 1, + }; + struct spi_message message; + int ret; + + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { + dev_err(&mgr->dev, "Partial reconfiguration not supported\n"); + return -EOPNOTSUPP; + } + + /* + * Efinix passive SPI configuration requires chip select to stay + * asserted from reset until the bitstream is fully clocked in. + * Lock the SPI bus so no other device can toggle CS between the + * reset pulse and the write/complete transfers. + */ + spi_bus_lock(conf->spi->controller); + spi_message_init_with_transfers(&message, &assert_cs, 1); + ret =3D spi_sync_locked(conf->spi, &message); + if (ret) { + spi_bus_unlock(conf->spi->controller); + return ret; + } + + /* Reset with CS asserted */ + efinix_spi_reset(conf); + + return 0; +} + +static int efinix_spi_write(struct fpga_manager *mgr, const char *buf, + size_t count) +{ + struct spi_transfer write_xfer =3D { + .tx_buf =3D buf, + .len =3D count, + .cs_change =3D 1, + }; + struct efinix_spi_conf *conf =3D mgr->priv; + struct spi_message message; + int ret; + + spi_message_init_with_transfers(&message, &write_xfer, 1); + ret =3D spi_sync_locked(conf->spi, &message); + if (ret) { + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", ret); + spi_bus_unlock(conf->spi->controller); + } + + return ret; +} + +static int efinix_spi_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + unsigned long timeout =3D + jiffies + usecs_to_jiffies(info->config_complete_timeout_us); + struct spi_transfer clk_cycles =3D { + .len =3D EFINIX_SPI_IDLE_CYCLES_BYTES, + /* Release CS after the trailing idle clocks are sent. */ + .cs_change =3D 0, + }; + struct efinix_spi_conf *conf =3D mgr->priv; + struct spi_message message; + int done, ret; + bool expired =3D false; + u8 *dummy_buf; + + dummy_buf =3D kzalloc(EFINIX_SPI_IDLE_CYCLES_BYTES, GFP_KERNEL); + if (!dummy_buf) { + ret =3D -ENOMEM; + goto unlock_spi; + } + + /* + * Keep the bus locked while sending the trailing idle clocks, then + * let this final transfer deassert CS to terminate configuration. + */ + clk_cycles.tx_buf =3D dummy_buf; + spi_message_init_with_transfers(&message, &clk_cycles, 1); + ret =3D spi_sync_locked(conf->spi, &message); + if (ret) { + dev_err(&mgr->dev, "SPI error in write complete: %d\n", ret); + goto free_buf; + } + + if (conf->cdone) { + while (!expired) { + done =3D gpiod_get_value(conf->cdone); + if (done < 0) { + ret =3D done; + goto free_buf; + } + if (done) + break; + + usleep_range(10, 20); + expired =3D time_after(jiffies, timeout); + } + + if (expired) { + dev_err(&mgr->dev, "Timeout waiting for CDONE\n"); + ret =3D -ETIMEDOUT; + goto free_buf; + } + } + + usleep_range(EFINIX_TUSER_US_MIN, EFINIX_TUSER_US_MAX); + +free_buf: + kfree(dummy_buf); +unlock_spi: + spi_bus_unlock(conf->spi->controller); + + return ret; +} + +static const struct fpga_manager_ops efinix_spi_ops =3D { + .state =3D efinix_spi_state, + .write_init =3D efinix_spi_write_init, + .write =3D efinix_spi_write, + .write_complete =3D efinix_spi_write_complete, +}; + +static int efinix_spi_probe(struct spi_device *spi) +{ + struct efinix_spi_conf *conf; + struct fpga_manager *mgr; + + if (!(spi->mode & SPI_CPHA) || !(spi->mode & SPI_CPOL)) + return dev_err_probe(&spi->dev, -EINVAL, + "Unsupported SPI mode, set CPHA and CPOL\n"); + + conf =3D devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL); + if (!conf) + return -ENOMEM; + + conf->reset =3D devm_gpiod_get(&spi->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(conf->reset)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->reset), + "Failed to get RESET gpio\n"); + + conf->cdone =3D devm_gpiod_get_optional(&spi->dev, "cdone", GPIOD_IN); + if (IS_ERR(conf->cdone)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->cdone), + "Failed to get CDONE gpio\n"); + + conf->spi =3D spi; + + mgr =3D devm_fpga_mgr_register(&spi->dev, + "Efinix FPGA Manager", + &efinix_spi_ops, conf); + + return PTR_ERR_OR_ZERO(mgr); +} + +static const struct of_device_id efinix_spi_of_match[] =3D { + { .compatible =3D "efinix,trion-config", }, + {} +}; +MODULE_DEVICE_TABLE(of, efinix_spi_of_match); + +static const struct spi_device_id efinix_ids[] =3D { + { "trion-config", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(spi, efinix_ids); + +static struct spi_driver efinix_spi_driver =3D { + .driver =3D { + .name =3D "efinix-spi", + .of_match_table =3D efinix_spi_of_match, + }, + .probe =3D efinix_spi_probe, + .id_table =3D efinix_ids, +}; + +module_spi_driver(efinix_spi_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Ian Dannapel "); +MODULE_DESCRIPTION("Efinix FPGA SPI Programming Driver"); --=20 2.43.0