From nobody Tue Jun 16 04:07:23 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C2FC19CD03; Thu, 16 Apr 2026 03:13:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776309184; cv=none; b=kj/nRLBZ+7VyHD3yHv2F4TLveAFiAGJly/7095UNHKYsxNrDf9whXTKBoBedj3fyVrLhbvXPt9v46SCuGNi1WkQYwarudF5Y3Zh0KY/VEb8jOecPPctsSfGJ8EiIejiEa1TTZnIkQ2QiGFaPCL0oRYR9EIbu6WuJnHJRaNL+BX4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776309184; c=relaxed/simple; bh=JWhB/mUsitTZ+rEusPMKJr4sDRE9SYuurfB+xzE3YOQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=jYk0LVEQCQGP+AEn7bth+y9aA0wX7N9O8holZFn8zyiHVgJjyFFIanc0z2oiEf9jGlTjnJXZTzkqr4pse2F4PHKw6GnMcrRHdRj/r8vGxjs275oKQbcwIxwu+Q34GvvIgNXCQMz0c6CO89Y7ez6ZUF45CHCdoo99hiRbWSxTL6c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=iZDTkBws; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="iZDTkBws" X-UUID: 2b29e3b8394211f1ae70033691e9ac7d-20260416 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=TxCeoHdWzESDHn8WGwcrtcx5Txqt/2sN3lNUQ8ms0l0=; b=iZDTkBwsZ8M1Pf3pM9Eb3kfNcLOLPHt0ijNa+to94J5hy7LpLcF/YcbBxuIwQ0i1uJPxxknVK6e/hgSe0rEWbsYJ7M4eE9Yf+fWRmWJFA+GQBNF1rKwlh5VVSPhTUQOh1wOKPfTU30RScPLdYMhY2bs9OhFw0tG60mBKNmxsBhE=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.12,REQID:9c02df0c-6dae-49fe-8aba-7746a0160133,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:e7bac3a,CLOUDID:ef95eb24-cb5c-4236-a89a-9a7fb20c9bc4,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|865|888|898,TC:-5,Cont ent:0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0 ,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 2b29e3b8394211f1ae70033691e9ac7d-20260416 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 322830716; Thu, 16 Apr 2026 11:12:57 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Thu, 16 Apr 2026 11:12:55 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Thu, 16 Apr 2026 11:12:55 +0800 From: Xiaoshun Xu To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Xiaoshun Xu CC: , , , , Sirius Wang , Vince-wl Liu , Subject: [PATCH v3 1/6] soc: mediatek: mtk-devapc: refine devapc interrupt handler Date: Thu, 16 Apr 2026 11:12:04 +0800 Message-ID: <20260416031231.2932493-2-xiaoshun.xu@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260416031231.2932493-1-xiaoshun.xu@mediatek.com> References: <20260416031231.2932493-1-xiaoshun.xu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Because the violation IRQ uses a while loop, it might cause the system to remain in the interrupt handler indefinitely. We are currently optimizing this part of the process to handle only 20 violations for debug violation issues, and then exit the loop Signed-off-by: Xiaoshun Xu --- drivers/soc/mediatek/mtk-devapc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-d= evapc.c index f54c966138b5..c9e1401315ad 100644 --- a/drivers/soc/mediatek/mtk-devapc.c +++ b/drivers/soc/mediatek/mtk-devapc.c @@ -12,6 +12,7 @@ #include #include =20 +#define MAX_VIO_NUM 20 #define VIO_MOD_TO_REG_IND(m) ((m) / 32) #define VIO_MOD_TO_REG_OFF(m) ((m) % 32) =20 @@ -188,13 +189,18 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_= context *ctx) */ static irqreturn_t devapc_violation_irq(int irq_number, void *data) { + u32 vio_num =3D 0; struct mtk_devapc_context *ctx =3D data; =20 - while (devapc_sync_vio_dbg(ctx)) + mask_module_irq(ctx, true); + + for (vio_num =3D 0; (vio_num < MAX_VIO_NUM) && (devapc_sync_vio_dbg(ctx))= ; ++vio_num) devapc_extract_vio_dbg(ctx); =20 clear_vio_status(ctx); =20 + mask_module_irq(ctx, false); + return IRQ_HANDLED; } =20 --=20 2.45.2 From nobody Tue Jun 16 04:07:23 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA0E6287254; Thu, 16 Apr 2026 03:13:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776309187; cv=none; b=Vz2jHPCj8qU7zSHU29SQC66Otf/yjsZ+apHNInOFVvloUq7mQOy8sQO07/GDPZ6S1ljKL26LBKSjyJjNf/005lKMLIP0+veFLIAEk1rByXCRER1lTUgcM1hAbFJZKVaddQooRF8WcPwSvfKdb/nDaPlkzY0AXMEz37w2LLF3tuc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776309187; c=relaxed/simple; bh=NEyyAjmQwAYq5Vb7crtqYMbhTIlVRROQUfhYYQLL3HU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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charset="utf-8" Because the new DEVAPC design, DEVAPC clock is controlled by HW power domains, the control flow of DEVAPC clock is not necessary, but to maintain compatibility with legacy ICs, keep this part of code. Signed-off-by: Xiaoshun Xu --- drivers/soc/mediatek/mtk-devapc.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-d= evapc.c index c9e1401315ad..f54e310791e5 100644 --- a/drivers/soc/mediatek/mtk-devapc.c +++ b/drivers/soc/mediatek/mtk-devapc.c @@ -284,16 +284,28 @@ static int mtk_devapc_probe(struct platform_device *p= dev) goto err; } =20 - ctx->infra_clk =3D devm_clk_get_enabled(&pdev->dev, "devapc-infra-clock"); + /* + * The new design of DAPC clock is controlled by HW power domains, + * making it unnecessary to provide the clock control driver. + */ + ctx->infra_clk =3D devm_clk_get_optional(&pdev->dev, "devapc-infra-clock"= ); if (IS_ERR(ctx->infra_clk)) { - ret =3D -EINVAL; - goto err; + dev_err(ctx->dev, "Cannot get devapc clock from CCF\n"); + ctx->infra_clk =3D NULL; + } else { + if (clk_prepare_enable(ctx->infra_clk)) { + ret =3D -EINVAL; + goto err; + } } =20 ret =3D devm_request_irq(&pdev->dev, devapc_irq, devapc_violation_irq, - IRQF_TRIGGER_NONE, "devapc", ctx); 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charset="utf-8" Add support for MT8189 DEVAPC, DEVAPC debug registers have new version, so refine the structure of devapc_regs_ofs_xxxx to devapc_regs_ofs_verX, and rename the infra_base to base in mtk_devapc_context because devapc not only access the infra_base to dump debug information when violation happens Signed-off-by: Xiaoshun Xu --- drivers/soc/mediatek/mtk-devapc.c | 171 +++++++++++++++++++++++------- 1 file changed, 134 insertions(+), 37 deletions(-) diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-d= evapc.c index f54e310791e5..824b49613c5a 100644 --- a/drivers/soc/mediatek/mtk-devapc.c +++ b/drivers/soc/mediatek/mtk-devapc.c @@ -27,9 +27,19 @@ struct mtk_devapc_vio_dbgs { u32 addr_h:4; u32 resv:4; } dbg0_bits; + + struct { + u32 dmnid:6; + u32 vio_w:1; + u32 vio_r:1; + u32 addr_h:4; + u32 resv:20; + } dbg0_bits_ver2; }; =20 u32 vio_dbg1; + u32 vio_dbg2; + u32 vio_dbg3; }; =20 struct mtk_devapc_regs_ofs { @@ -38,6 +48,8 @@ struct mtk_devapc_regs_ofs { u32 vio_sta_offset; u32 vio_dbg0_offset; u32 vio_dbg1_offset; + u32 vio_dbg2_offset; + u32 vio_dbg3_offset; u32 apc_con_offset; u32 vio_shift_sta_offset; u32 vio_shift_sel_offset; @@ -45,16 +57,20 @@ struct mtk_devapc_regs_ofs { }; =20 struct mtk_devapc_data { - /* numbers of violation index */ - u32 vio_idx_num; + u32 version; + /* Default numbers of violation index */ + u32 default_vio_idx_num; const struct mtk_devapc_regs_ofs *regs_ofs; }; =20 struct mtk_devapc_context { struct device *dev; - void __iomem *infra_base; + void __iomem *base; struct clk *infra_clk; const struct mtk_devapc_data *data; + + /* numbers of violation index */ + u32 vio_idx_num; }; =20 static void clear_vio_status(struct mtk_devapc_context *ctx) @@ -62,12 +78,12 @@ static void clear_vio_status(struct mtk_devapc_context = *ctx) void __iomem *reg; int i; =20 - reg =3D ctx->infra_base + ctx->data->regs_ofs->vio_sta_offset; + reg =3D ctx->base + ctx->data->regs_ofs->vio_sta_offset; =20 - for (i =3D 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++) + for (i =3D 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++) writel(GENMASK(31, 0), reg + 4 * i); =20 - writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, 0), + writel(GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1), 0), reg + 4 * i); } =20 @@ -77,22 +93,22 @@ static void mask_module_irq(struct mtk_devapc_context *= ctx, bool mask) u32 val; int i; =20 - reg =3D ctx->infra_base + ctx->data->regs_ofs->vio_mask_offset; + reg =3D ctx->base + ctx->data->regs_ofs->vio_mask_offset; =20 if (mask) val =3D GENMASK(31, 0); else val =3D 0; =20 - for (i =3D 0; i < VIO_MOD_TO_REG_IND(ctx->data->vio_idx_num) - 1; i++) + for (i =3D 0; i < VIO_MOD_TO_REG_IND(ctx->vio_idx_num - 1); i++) writel(val, reg + 4 * i); =20 val =3D readl(reg + 4 * i); if (mask) - val |=3D GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, + val |=3D GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1), 0); else - val &=3D ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->data->vio_idx_num) - 1, + val &=3D ~GENMASK(VIO_MOD_TO_REG_OFF(ctx->vio_idx_num - 1), 0); =20 writel(val, reg + 4 * i); @@ -119,11 +135,11 @@ static int devapc_sync_vio_dbg(struct mtk_devapc_cont= ext *ctx) int ret; u32 val; =20 - pd_vio_shift_sta_reg =3D ctx->infra_base + + pd_vio_shift_sta_reg =3D ctx->base + ctx->data->regs_ofs->vio_shift_sta_offset; - pd_vio_shift_sel_reg =3D ctx->infra_base + + pd_vio_shift_sel_reg =3D ctx->base + ctx->data->regs_ofs->vio_shift_sel_offset; - pd_vio_shift_con_reg =3D ctx->infra_base + + pd_vio_shift_con_reg =3D ctx->base + ctx->data->regs_ofs->vio_shift_con_offset; =20 /* Find the minimum shift group which has violation */ @@ -134,7 +150,7 @@ static int devapc_sync_vio_dbg(struct mtk_devapc_contex= t *ctx) min_shift_group =3D __ffs(val); =20 /* Assign the group to sync */ - writel(0x1 << min_shift_group, pd_vio_shift_sel_reg); + writel(BIT(min_shift_group), pd_vio_shift_sel_reg); =20 /* Start syncing */ writel(0x1, pd_vio_shift_con_reg); @@ -150,7 +166,7 @@ static int devapc_sync_vio_dbg(struct mtk_devapc_contex= t *ctx) writel(0x0, pd_vio_shift_con_reg); =20 /* Write clear */ - writel(0x1 << min_shift_group, pd_vio_shift_sta_reg); + writel(BIT(min_shift_group), pd_vio_shift_sta_reg); =20 return true; } @@ -164,22 +180,52 @@ static void devapc_extract_vio_dbg(struct mtk_devapc_= context *ctx) struct mtk_devapc_vio_dbgs vio_dbgs; void __iomem *vio_dbg0_reg; void __iomem *vio_dbg1_reg; + void __iomem *vio_dbg2_reg; + void __iomem *vio_dbg3_reg; + u32 vio_addr_l, vio_addr_h, bus_id, domain_id; + u32 vio_w, vio_r; + u64 vio_addr; =20 - vio_dbg0_reg =3D ctx->infra_base + ctx->data->regs_ofs->vio_dbg0_offset; - vio_dbg1_reg =3D ctx->infra_base + ctx->data->regs_ofs->vio_dbg1_offset; + vio_dbg0_reg =3D ctx->base + ctx->data->regs_ofs->vio_dbg0_offset; + vio_dbg1_reg =3D ctx->base + ctx->data->regs_ofs->vio_dbg1_offset; + vio_dbg2_reg =3D ctx->base + ctx->data->regs_ofs->vio_dbg2_offset; + vio_dbg3_reg =3D ctx->base + ctx->data->regs_ofs->vio_dbg3_offset; =20 vio_dbgs.vio_dbg0 =3D readl(vio_dbg0_reg); vio_dbgs.vio_dbg1 =3D readl(vio_dbg1_reg); + if (ctx->data->version >=3D 2U) + vio_dbgs.vio_dbg2 =3D readl(vio_dbg2_reg); + if (ctx->data->version =3D=3D 3U) + vio_dbgs.vio_dbg3 =3D readl(vio_dbg3_reg); + + if (ctx->data->version =3D=3D 1U) { + /* arch version 1 */ + bus_id =3D vio_dbgs.dbg0_bits.mstid; + vio_addr =3D vio_dbgs.vio_dbg1; + domain_id =3D vio_dbgs.dbg0_bits.dmnid; + vio_w =3D vio_dbgs.dbg0_bits.vio_w; + vio_r =3D vio_dbgs.dbg0_bits.vio_r; + } else { + /* arch version 2 & 3 */ + bus_id =3D vio_dbgs.vio_dbg1; + + vio_addr_l =3D vio_dbgs.vio_dbg2; + vio_addr_h =3D ctx->data->version =3D=3D 2U ? vio_dbgs.dbg0_bits_ver2.ad= dr_h : + vio_dbgs.vio_dbg3; + vio_addr =3D ((u64)vio_addr_h << 32) + vio_addr_l; + domain_id =3D vio_dbgs.dbg0_bits_ver2.dmnid; + vio_w =3D vio_dbgs.dbg0_bits_ver2.vio_w; + vio_r =3D vio_dbgs.dbg0_bits_ver2.vio_r; + } =20 /* Print violation information */ - if (vio_dbgs.dbg0_bits.vio_w) + if (vio_w) dev_info(ctx->dev, "Write Violation\n"); - else if (vio_dbgs.dbg0_bits.vio_r) + else if (vio_r) dev_info(ctx->dev, "Read Violation\n"); =20 - dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%x\n", - vio_dbgs.dbg0_bits.mstid, vio_dbgs.dbg0_bits.dmnid, - vio_dbgs.vio_dbg1); + dev_info(ctx->dev, "Bus ID:0x%x, Dom ID:0x%x, Vio Addr:0x%llx\n", + bus_id, domain_id, vio_addr); } =20 /* @@ -209,7 +255,8 @@ static irqreturn_t devapc_violation_irq(int irq_number,= void *data) */ static void start_devapc(struct mtk_devapc_context *ctx) { - writel(BIT(31), ctx->infra_base + ctx->data->regs_ofs->apc_con_offset); + + writel(BIT(31), ctx->base + ctx->data->regs_ofs->apc_con_offset); =20 mask_module_irq(ctx, false); } @@ -221,28 +268,60 @@ static void stop_devapc(struct mtk_devapc_context *ct= x) { mask_module_irq(ctx, true); =20 - writel(BIT(2), ctx->infra_base + ctx->data->regs_ofs->apc_con_offset); + writel(BIT(2), ctx->base + ctx->data->regs_ofs->apc_con_offset); } =20 -static const struct mtk_devapc_regs_ofs devapc_regs_ofs_mt6779 =3D { +static const struct mtk_devapc_regs_ofs devapc_regs_ofs_ver1 =3D { + .vio_mask_offset =3D 0x0, + .vio_sta_offset =3D 0x400, + .vio_dbg0_offset =3D 0x900, + .vio_dbg1_offset =3D 0x904, + .apc_con_offset =3D 0xf00, + .vio_shift_sta_offset =3D 0xf10, + .vio_shift_sel_offset =3D 0xf14, + .vio_shift_con_offset =3D 0xf20, +}; + +static const struct mtk_devapc_regs_ofs devapc_regs_ofs_ver2 =3D { .vio_mask_offset =3D 0x0, .vio_sta_offset =3D 0x400, .vio_dbg0_offset =3D 0x900, .vio_dbg1_offset =3D 0x904, - .apc_con_offset =3D 0xF00, - .vio_shift_sta_offset =3D 0xF10, - .vio_shift_sel_offset =3D 0xF14, - .vio_shift_con_offset =3D 0xF20, + .vio_dbg2_offset =3D 0x908, + .apc_con_offset =3D 0xf00, + .vio_shift_sta_offset =3D 0xf20, + .vio_shift_sel_offset =3D 0xf30, + .vio_shift_con_offset =3D 0xf10, +}; + +static const struct mtk_devapc_regs_ofs devapc_regs_ofs_ver3 =3D { + .vio_mask_offset =3D 0x0, + .vio_sta_offset =3D 0x400, + .vio_dbg0_offset =3D 0x900, + .vio_dbg1_offset =3D 0x904, + .vio_dbg2_offset =3D 0x908, + .vio_dbg3_offset =3D 0x90c, + .apc_con_offset =3D 0xf00, + .vio_shift_sta_offset =3D 0xf20, + .vio_shift_sel_offset =3D 0xf30, + .vio_shift_con_offset =3D 0xf10, }; =20 static const struct mtk_devapc_data devapc_mt6779 =3D { - .vio_idx_num =3D 511, - .regs_ofs =3D &devapc_regs_ofs_mt6779, + .version =3D 1, + .default_vio_idx_num =3D 511, + .regs_ofs =3D &devapc_regs_ofs_ver1, }; =20 static const struct mtk_devapc_data devapc_mt8186 =3D { - .vio_idx_num =3D 519, - .regs_ofs =3D &devapc_regs_ofs_mt6779, + .version =3D 1, + .default_vio_idx_num =3D 519, + .regs_ofs =3D &devapc_regs_ofs_ver1, +}; + +static const struct mtk_devapc_data devapc_mt8189 =3D { + .version =3D 3, + .regs_ofs =3D &devapc_regs_ofs_ver3, }; =20 static const struct of_device_id mtk_devapc_dt_match[] =3D { @@ -252,6 +331,9 @@ static const struct of_device_id mtk_devapc_dt_match[] = =3D { }, { .compatible =3D "mediatek,mt8186-devapc", .data =3D &devapc_mt8186, + }, { + .compatible =3D "mediatek,mt8189-devapc", + .data =3D &devapc_mt8189, }, { }, }; @@ -274,9 +356,24 @@ static int mtk_devapc_probe(struct platform_device *pd= ev) ctx->data =3D of_device_get_match_data(&pdev->dev); ctx->dev =3D &pdev->dev; =20 - ctx->infra_base =3D of_iomap(node, 0); - if (!ctx->infra_base) + ctx->base =3D of_iomap(node, 0); + if (!ctx->base) { + dev_err(ctx->dev, "Failed to map devapc registers\n"); return -EINVAL; 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charset="utf-8" Extend the devapc device tree bindings to support the MediaTek MT8189 SoC. This includes: - Adding "mediatek,mt8189-devapc" to the list of compatible strings. - Introducing the "vio-idx-num" property to specify the number of bus slaves managed by devapc. These changes enable proper configuration and integration of devapc on MT8189 platforms, ensuring accurate device matching and resource allocation in the device tree. Signed-off-by: Xiaoshun Xu --- .../devicetree/bindings/soc/mediatek/devapc.yaml | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml b/D= ocumentation/devicetree/bindings/soc/mediatek/devapc.yaml index 99e2caafeadf..06a096440331 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml @@ -14,13 +14,14 @@ description: | analysis and countermeasures. =20 maintainers: - - Neal Liu + - Xiaoshun Xu =20 properties: compatible: enum: - mediatek,mt6779-devapc - mediatek,mt8186-devapc + - mediatek,mt8189-devapc =20 reg: description: The base address of devapc register bank @@ -30,6 +31,10 @@ properties: description: A single interrupt specifier maxItems: 1 =20 + vio-idx-num: + description: Describe the number of bus slaves controlled by devapc + $ref: /schemas/types.yaml#/definitions/uint32 + clocks: description: Contains module clock source and clock names maxItems: 1 @@ -42,8 +47,6 @@ required: - compatible - reg - interrupts - - clocks - - clock-names =20 additionalProperties: false =20 @@ -55,6 +58,7 @@ examples: devapc: devapc@10207000 { compatible =3D "mediatek,mt6779-devapc"; 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Thu, 16 Apr 2026 11:13:03 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Thu, 16 Apr 2026 11:13:02 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Thu, 16 Apr 2026 11:13:02 +0800 From: Xiaoshun Xu To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Xiaoshun Xu CC: , , , , Sirius Wang , Vince-wl Liu , Subject: [PATCH v3 5/6] soc: mediatek: mtk-devapc: Add support for MT8196 DEVAPC Date: Thu, 16 Apr 2026 11:12:08 +0800 Message-ID: <20260416031231.2932493-6-xiaoshun.xu@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260416031231.2932493-1-xiaoshun.xu@mediatek.com> References: <20260416031231.2932493-1-xiaoshun.xu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for MT8196 DEVAPC, MT8196 DEVAPC debug registers are version 3 and add compatible for MT8196 Signed-off-by: Xiaoshun Xu --- drivers/soc/mediatek/mtk-devapc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/soc/mediatek/mtk-devapc.c b/drivers/soc/mediatek/mtk-d= evapc.c index 824b49613c5a..0f828028bdb4 100644 --- a/drivers/soc/mediatek/mtk-devapc.c +++ b/drivers/soc/mediatek/mtk-devapc.c @@ -324,6 +324,11 @@ static const struct mtk_devapc_data devapc_mt8189 =3D { .regs_ofs =3D &devapc_regs_ofs_ver3, }; =20 +static const struct mtk_devapc_data devapc_mt8196 =3D { + .version =3D 3, + .regs_ofs =3D &devapc_regs_ofs_ver3, +}; + static const struct of_device_id mtk_devapc_dt_match[] =3D { { .compatible =3D "mediatek,mt6779-devapc", @@ -334,6 +339,9 @@ static const struct of_device_id mtk_devapc_dt_match[] = =3D { }, { .compatible =3D "mediatek,mt8189-devapc", .data =3D &devapc_mt8189, + }, { + .compatible =3D "mediatek,mt8196-devapc", + .data =3D &devapc_mt8196, }, { }, }; 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Thu, 16 Apr 2026 11:13:04 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Thu, 16 Apr 2026 11:13:04 +0800 From: Xiaoshun Xu To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Xiaoshun Xu CC: , , , , Sirius Wang , Vince-wl Liu , Subject: [PATCH v3 6/6] dt-bindings: soc: mediatek: devapc: Add bindings for MT8196 Date: Thu, 16 Apr 2026 11:12:09 +0800 Message-ID: <20260416031231.2932493-7-xiaoshun.xu@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260416031231.2932493-1-xiaoshun.xu@mediatek.com> References: <20260416031231.2932493-1-xiaoshun.xu@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the devapc device tree bindings to support the MediaTek MT8196 SoC. This includes: - Adding "mediatek,mt8196-devapc" to the list of compatible strings. These changes enable proper configuration and integration of devapc on MT8196 platforms, ensuring accurate device matching and resource allocation in the device tree. Signed-off-by: Xiaoshun Xu --- Documentation/devicetree/bindings/soc/mediatek/devapc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml b/D= ocumentation/devicetree/bindings/soc/mediatek/devapc.yaml index 06a096440331..5eb260bf3dde 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/devapc.yaml @@ -22,6 +22,7 @@ properties: - mediatek,mt6779-devapc - mediatek,mt8186-devapc - mediatek,mt8189-devapc + - mediatek,mt8196-devapc =20 reg: description: The base address of devapc register bank --=20 2.45.2