From nobody Wed Jun 10 16:29:41 2026 Received: from smtpout-02.galae.net (smtpout-02.galae.net [185.246.84.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 404CC3D6477 for ; Thu, 16 Apr 2026 14:00:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.246.84.56 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776348012; cv=none; b=oaahKe2THmOkfnz4VNbl4r7vCI0vhwxMsvD7okYSn2plBuyfXi5gALbkosi9zQKuzJgeImYMgmG2faaxUA/6cOWXU83afgu7QIFB/tjNXDFX9NBDC+f+bcU3BvxLRHeIrCrS8p9zUdPZ0SPAqpFosXFn4xviLz/X0yxSjKVHugg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776348012; c=relaxed/simple; bh=iA8u0XEYSSlqLZ9mUJGIbic9pBtHUNyXfgToRRoJQhc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mpOsXvJP/sJfOs3YQg2FVcn4umdGtC+vKe+Id7qdm0/GJs8JcY4hw9aflZ2kfCOlTHF/OItNSFKcvqbOKlFGilm8DakUHV4BveKGHrG2EIWGlgm7VIDpoXstoZ++iCZaeVyp8x5zdrIqik5gGJ+SkFnMt/o8MZjgVTqg3K6rF0I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=Kwryl1gl; arc=none smtp.client-ip=185.246.84.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="Kwryl1gl" Received: from smtpout-01.galae.net (smtpout-01.galae.net [212.83.139.233]) by smtpout-02.galae.net (Postfix) with ESMTPS id AEC8F1A32FF; Thu, 16 Apr 2026 14:00:08 +0000 (UTC) Received: from mail.galae.net (mail.galae.net [212.83.136.155]) by smtpout-01.galae.net (Postfix) with ESMTPS id 8452260495; Thu, 16 Apr 2026 14:00:08 +0000 (UTC) Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id 09551104608A1; Thu, 16 Apr 2026 16:00:04 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim; t=1776348007; h=from:subject:date:message-id:to:cc:mime-version:content-type: content-transfer-encoding:in-reply-to:references; bh=Qtj7KJgMQ3pCG2NniTimE9jRyWQEw4bmxyikGHd7CTo=; b=Kwryl1glF6oFpmKVZK02dQ5mYl0qiNc9pzcKe5wYi4g6j5KPbLzYkmIG029SqWDsBJBNRS 8bSJcQiYN7TuZjC4mQqYI2OwE/UQiEcCail6kEgVgM+qifrxoF4U6z5Ly4Z/6eNGa1FeNi aOY92O3Oz9yY1sUsKASYygGHMtsfe0VjbXl246jS8OSabxCZd75HXS3YnB9wVq1PVmt0g9 2Ai0KMGf/I/UGMGxmRyIXgSc+bUdOPUyN/xU5PADAKSiMA87D9NpG1dcR922gC2Ye4Su3w TKNmwsQOH4/JwMzGBu7KlNYJj0uWwpmwSgdEDiKgtX7OoxMrZM7x/FrmVVNP7A== From: Luca Ceresoli Date: Thu, 16 Apr 2026 15:59:55 +0200 Subject: [PATCH v3] drm/bridge: ti-sn65dsi83: add test pattern generation support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260416-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v3-1-143886aebc6b@bootlin.com> References: <20260416-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v3-0-143886aebc6b@bootlin.com> In-Reply-To: <20260416-ti-sn65dsi83-dual-lvds-fixes-and-test-pattern-v3-0-143886aebc6b@bootlin.com> To: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Frieder Schrempf , Marek Vasut , Linus Walleij Cc: Louis Chauvet , Hui Pu , Ian Ray , Thomas Petazzoni , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Luca Ceresoli X-Mailer: b4 0.15.2 X-Last-TLS-Session-Version: TLSv1.3 Generation of a test pattern output is a useful tool for panel bringup and debugging, and very simple to support with this chip. The value of REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW needs to be divided by two for the test pattern to work in dual LVDS mode. While not clearly stated in the datasheet, this is needed according to the DSI Tuner [0] output. And some dual-LVDS panels refuse to show any picture without this division by two. [0] https://www.ti.com/tool/DSI-TUNER Signed-off-by: Luca Ceresoli Reviewed-by: Louis Chauvet --- Changes in v3: - fixed incorrect halving of hdisplay in single-link mode Changes in v2: - added local variable to avoid potential race condition leading to inconsistent settings --- drivers/gpu/drm/bridge/ti-sn65dsi83.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge= /ti-sn65dsi83.c index 17a885244e1e..2b6f6a54edb7 100644 --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c @@ -114,6 +114,7 @@ #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a #define REG_VID_CHA_TEST_PATTERN 0x3c +#define REG_VID_CHA_TEST_PATTERN_EN BIT(4) /* IRQ registers */ #define REG_IRQ_GLOBAL 0xe0 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0) @@ -134,6 +135,9 @@ #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2) #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0) =20 +static bool sn65dsi83_test_pattern; +module_param_named(test_pattern, sn65dsi83_test_pattern, bool, 0644); + enum sn65dsi83_channel { CHANNEL_A, CHANNEL_B @@ -523,6 +527,7 @@ static void sn65dsi83_atomic_pre_enable(struct drm_brid= ge *bridge, const struct drm_display_mode *mode; struct drm_connector *connector; struct drm_crtc *crtc; + bool test_pattern =3D sn65dsi83_test_pattern; bool lvds_format_24bpp; bool lvds_format_jeida; unsigned int pval; @@ -645,7 +650,11 @@ static void sn65dsi83_atomic_pre_enable(struct drm_bri= dge *bridge, REG_LVDS_LANE_CHB_LVDS_TERM : 0)); regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); =20 - le16val =3D cpu_to_le16(mode->hdisplay); + /* + * Active line length needs to be halved for test pattern + * generation in dual LVDS output. + */ + le16val =3D cpu_to_le16(mode->hdisplay / (test_pattern ? dual_factor : 1)= ); regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, &le16val, 2); le16val =3D cpu_to_le16(mode->vdisplay); @@ -668,7 +677,8 @@ static void sn65dsi83_atomic_pre_enable(struct drm_brid= ge *bridge, (mode->hsync_start - mode->hdisplay) / dual_factor); regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, mode->vsync_start - mode->vdisplay); - regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); + regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, + test_pattern ? REG_VID_CHA_TEST_PATTERN_EN : 0); =20 /* Enable PLL */ regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); --=20 2.53.0