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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2e539fa5c38sm638451eec.5.2026.04.16.21.16.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Apr 2026 21:16:26 -0700 (PDT) From: Qiang Yu Date: Thu, 16 Apr 2026 21:16:25 -0700 Subject: [PATCH] PCI: qcom: Set max OPP before DBI access during resume Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20260416-setmaxopp-v1-1-6a74e2d945a0@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIABi04WkC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDE0Mz3eLUktzEivyCAl3zRJM0E8u0JEuDJFMloPqCotS0zAqwWdGxtbU AQDZ/L1sAAAA= X-Change-ID: 20260416-setmaxopp-7a4f49fb90b5 To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Krishna chaitanya chundru Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Qiang Yu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776399386; l=3294; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=wReg8hifVkzlEEdADzMhijrroaIK/MnJQ3ovMsYvmFo=; b=/SvocC1tbAISboxZNBSseO3EC900RS6124mkUXh1rof+7sbSNZR3DgI4YolUmP8MVCo68k2vX QH/RORxPfmmA5nLQDcKQl/AG3247lgd/Sh6SuX2v/biC/eE1TLYeMs9 X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-GUID: zVxAI_G2YwoTzFJ37_D374vQ0jQS9gP2 X-Authority-Analysis: v=2.4 cv=XNoAjwhE c=1 sm=1 tr=0 ts=69e1b41d cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=_e_GtX_bwWpn_Ay3u5MA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-ORIG-GUID: zVxAI_G2YwoTzFJ37_D374vQ0jQS9gP2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE3MDAzOSBTYWx0ZWRfX1676PZnpxvQF tH3zY8Y2KUDoAgInYWVgQ5nFI7mG+K3QlZNsQlCJRC6wXuzyBX71O1b1Q/C1KbnzPoh9o1htnue yuwRVeCMbRKnKfXEQhwYrHtpW0V3o67YMRLzs6tgfUJDxks8dHUGS4d9zEKvk1k/qHp8LCN91bJ 1WNcpjs1N2YZ9vG/R+JPmGk0cRGCPKa5NJBcZFS5DJCoHGasGsJBA4hAe9dCkbDAtP0/hKMf72L v58QzCjclBsARdJyXADxUx1xVdliNORAhxGL3nqzNC2roKwUbnmCM/q4du6q8N1PD/OeZ/oCS9W bAhNFOXJk235Q5VSwvfvmaDcwQEsgU1xEMKDPcbt2+apJBMIIe76c9VV3g9X1H1Em6jEGG1fbuc 2dxoxjDH4ueurZmcF0DHCIrht+odXGTU5uFh3fJRtwsuWFvo2cmnQxoEV2JXxUUJ8PDlcqif/ac rzKopryz7zbmNZTgrog== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-16_04,2026-04-16_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 impostorscore=0 priorityscore=1501 suspectscore=0 spamscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604170039 During resume, qcom_pcie_icc_opp_update() may access DBI registers before the OPP votes are restored, which can trigger NoC errors. Set the PCIe controller to the maximum OPP first in resume_noirq(), then proceed with link/DBI accesses. The OPP is later updated again based on the actual link bandwidth requirements. Also introduce a small helper to reuse the max-OPP setup path shared with probe. Fixes: 5b6272e0efd5 ("PCI: qcom: Add OPP support to scale performance") Signed-off-by: Qiang Yu --- drivers/pci/controller/dwc/pcie-qcom.c | 42 +++++++++++++++++++++---------= ---- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 9fdfc88ac15120b2b01cad746772ae612a2c9690..c9b201a1c033a9849e97db9ee4d= 07d26655d5a6c 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1613,6 +1613,22 @@ static void qcom_pcie_icc_opp_update(struct qcom_pci= e *pcie) } } =20 +static int qcom_pcie_set_max_opp(struct device *dev) +{ + unsigned long max_freq =3D ULONG_MAX; + struct dev_pm_opp *opp; + int ret; + + opp =3D dev_pm_opp_find_freq_floor(dev, &max_freq); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + ret =3D dev_pm_opp_set_opp(dev, opp); + dev_pm_opp_put(opp); + + return ret; +} + static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) { struct qcom_pcie *pcie =3D (struct qcom_pcie *)dev_get_drvdata(s->private= ); @@ -1845,9 +1861,7 @@ static int qcom_pcie_probe(struct platform_device *pd= ev) struct qcom_pcie_perst *perst, *tmp_perst; struct qcom_pcie_port *port, *tmp_port; const struct qcom_pcie_cfg *pcie_cfg; - unsigned long max_freq =3D ULONG_MAX; struct device *dev =3D &pdev->dev; - struct dev_pm_opp *opp; struct qcom_pcie *pcie; struct dw_pcie_rp *pp; struct resource *res; @@ -1951,21 +1965,9 @@ static int qcom_pcie_probe(struct platform_device *p= dev) * probe(), OPP will be updated using qcom_pcie_icc_opp_update(). */ if (!ret) { - opp =3D dev_pm_opp_find_freq_floor(dev, &max_freq); - if (IS_ERR(opp)) { - ret =3D PTR_ERR(opp); - dev_err_probe(pci->dev, ret, - "Unable to find max freq OPP\n"); - goto err_pm_runtime_put; - } else { - ret =3D dev_pm_opp_set_opp(dev, opp); - } - - dev_pm_opp_put(opp); + ret =3D qcom_pcie_set_max_opp(dev); if (ret) { - dev_err_probe(pci->dev, ret, - "Failed to set OPP for freq %lu\n", - max_freq); + dev_err_probe(dev, ret, "Failed to set max OPP in probe\n"); goto err_pm_runtime_put; } =20 @@ -2100,6 +2102,14 @@ static int qcom_pcie_resume_noirq(struct device *dev) return 0; =20 if (pm_suspend_target_state !=3D PM_SUSPEND_MEM) { + if (pcie->use_pm_opp) { + ret =3D qcom_pcie_set_max_opp(dev); + if (ret) { + dev_err(dev, "Failed to set max OPP in resume: %d\n", ret); + return ret; + } + } + ret =3D icc_enable(pcie->icc_cpu); if (ret) { dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); --- base-commit: 33a76fc3c3e61386524479b99f35423bd3d9a895 change-id: 20260416-setmaxopp-7a4f49fb90b5 Best regards, --=20 Qiang Yu