From nobody Sat Jun 20 11:51:19 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CCBCE3E9F63 for ; Wed, 15 Apr 2026 16:55:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272136; cv=none; b=YJ3/xuor8wHjign3+bG+Qs+n2uBlzCfWvzQl6qlgflWdLTNQe47XlXyf5k5v/zPwc1kQIo8fzQy4pBe0MvVXN5J+UA2/CH/6+iUBPCnGoRl5iX9nitzcF7AJhskTAlvwuVExncrOa+AvGgSAL48XJKKHBrQUQDJroBYJYdvOmnQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272136; c=relaxed/simple; bh=+h8s2k45gr74tkKaNYCUe+TMlKHAxaWDuG4e1iGbico=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=F+lUpi6L0sucGmxqzq0WmXYs7LA3Nf63zkBDckRSmlz1w2M4HFZpa9QANbQWWPLETBtKzM5ntiIGmFerL39kU2pUuYBnwSKdxoVys7LbHqkyvzJVsVr9d9tutZ9oirKGg/LJGWqkF9nLbiXIYqJGJgVVXbY8KX46/e8wXGT3ksQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=IC17eKAD; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="IC17eKAD" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9CE8B32FB; Wed, 15 Apr 2026 09:55:28 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 6950F3F7D8; Wed, 15 Apr 2026 09:55:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776272134; bh=+h8s2k45gr74tkKaNYCUe+TMlKHAxaWDuG4e1iGbico=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IC17eKADy/X1hdMMm6YM6fdGw6N6LrhFg6SD704r7cS5A3uxF1yD4ildGMbcPnbuF FZeO91sbHf2V8DAVeq4xeV1Y9Vt+hMzX+2vYfT3HoI8e1u6F/2yL7jx/t0zyKWc7Hj gjWKdGJ1nYQwdA+PuypqXwG9UqgHR4njT3IPNgCE= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v5 01/12] coresight: etm4x: fix wrong check of etm4x_sspcicrn_present() Date: Wed, 15 Apr 2026 17:55:17 +0100 Message-Id: <20260415165528.3369607-2-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260415165528.3369607-1-yeoreum.yun@arm.com> References: <20260415165528.3369607-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" According to Embedded Trace Macrocell Architecture Specification ETMv4.0 to ETM4.6 [0], TRCSSPCICR is present only if all of the following are true: - TRCIDR4.NUMSSCC > n. - TRCIDR4.NUMPC > 0b0000. - TRCSSCSR.PC =3D=3D 0b1. Comment for etm4x_sspcicrn_present() is align with the specification. However, the check should use drvdata->nr_pe_cmp to check TRCIDR4.NUMPC not nr_pe. Link: https://developer.arm.com/documentation/ihi0064/latest/ [0] Signed-off-by: Yeoreum Yun Reviewed-by: Leo Yan --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index d565a73f0042..74b7063d130e 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -89,7 +89,7 @@ static int etm4_probe_cpu(unsigned int cpu); static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) { return (n < drvdata->nr_ss_cmp) && - drvdata->nr_pe && + drvdata->nr_pe_cmp && (drvdata->config.ss_status[n] & TRCSSCSRn_PC); } =20 --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Jun 20 11:51:19 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EC9AE3EAC71 for ; Wed, 15 Apr 2026 16:55:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272138; cv=none; b=A9ENVp68OjWX4K9j5EsWJiEF15YErNxMEVvlCVqFUOBQ8Q9DI2fYG5YoxM+H/x7moN8hl6i9O3h1Nniii0LgrIvlBLtVDb7aPu6UWQA8l1Pqa6Z2/8DD+vTzJ+KVpRTW7azefCi9wKcqE0gvaVP0s/ibbJFlT1Evdu9hgMfUGMs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272138; c=relaxed/simple; bh=AAkzGqlEubbe7OVQcjjz853wRAcx9P/zHI85x3EhPwA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S6w7S7jZUIv0aTuGYQ0Wy6ef0leP/g7JmMEvwvnSUIlTrMAZBsD/eo05veD2Km2uND+7RuzlCgCK+i/Pj0Ttc298uP/Sk1vtfFrZj37uZWizHMhWODQ3pbT7ouUJ3qqGOTQgpp7Bn2u3Yp+P+FQyjtZcuIRz3xxVHmfuazTWGls= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=LZ/ToS7m; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="LZ/ToS7m" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CD279354D; Wed, 15 Apr 2026 09:55:30 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A1E4B3F7D8; Wed, 15 Apr 2026 09:55:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776272136; bh=AAkzGqlEubbe7OVQcjjz853wRAcx9P/zHI85x3EhPwA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LZ/ToS7mG0bd2r27BKCQpk8PUeTPSVaF1jWabP6VmV3WArSWTn1ae0iOSkJVyDjhs sXgsXq0G5SV/JFtdE4edED+cg6DKxPN4VNkSzOP8gt19cc8guOSZzPDJObv2e+uAn3 jE2wiGDEiflKJKJFSHDqRTLKk5c+vwMJPhLHa8TE= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v5 02/12] coresight: etm4x: fix underflow for nrseqstate Date: Wed, 15 Apr 2026 17:55:18 +0100 Message-Id: <20260415165528.3369607-3-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260415165528.3369607-1-yeoreum.yun@arm.com> References: <20260415165528.3369607-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" TCRSEQEVR is implemented only when TCRIDR5.NUMSEQSTATE is 0b100, in which case n ranges from 0 to 2; otherwise, TCRIDR5.NUMSEQSTATE is 0b000. Therefore, drvdata->nrseqstate should be checked before entering the loop. Link: https://developer.arm.com/documentation/ihi0064/latest/ [0] Signed-off-by: Yeoreum Yun Reviewed-by: Leo Yan --- .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++-------- .../coresight/coresight-etm4x-sysfs.c | 2 ++ 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 74b7063d130e..ba5b8b423bd4 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -544,9 +544,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdat= a) etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR); if (drvdata->nr_pe_cmp) etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); - for (i =3D 0; i < drvdata->nrseqstate - 1; i++) - etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); + if (drvdata->nrseqstate) { + for (i =3D 0; i < drvdata->nrseqstate - 1; i++) + etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); } @@ -1927,10 +1929,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *dr= vdata) if (drvdata->nr_pe_cmp) state->trcvipcssctlr =3D etm4x_read32(csa, TRCVIPCSSCTLR); =20 - for (i =3D 0; i < drvdata->nrseqstate - 1; i++) - state->trcseqevr[i] =3D etm4x_read32(csa, TRCSEQEVRn(i)); - if (drvdata->nrseqstate) { + for (i =3D 0; i < drvdata->nrseqstate - 1; i++) + state->trcseqevr[i] =3D etm4x_read32(csa, TRCSEQEVRn(i)); + state->trcseqrstevr =3D etm4x_read32(csa, TRCSEQRSTEVR); state->trcseqstr =3D etm4x_read32(csa, TRCSEQSTR); } @@ -2058,10 +2060,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata= *drvdata) if (drvdata->nr_pe_cmp) etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR); =20 - for (i =3D 0; i < drvdata->nrseqstate - 1; i++) - etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); - if (drvdata->nrseqstate) { + for (i =3D 0; i < drvdata->nrseqstate - 1; i++) + etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); } diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm4x-sysfs.c index e9eeea6240d5..d866dcfa2a36 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1395,6 +1395,8 @@ static ssize_t seq_idx_store(struct device *dev, struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct etmv4_config *config =3D &drvdata->config; =20 + if (!drvdata->nrseqstate) + return -EINVAL; if (kstrtoul(buf, 16, &val)) return -EINVAL; if (val >=3D drvdata->nrseqstate - 1) --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Jun 20 11:51:19 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8DADC3EB7FC for ; Wed, 15 Apr 2026 16:55:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272142; cv=none; b=oqN4OZam8vej4Hm9nc1yUxQI4sev2sMHrJ7akiBKDQUvlh4eL7PjieJBaqZsWMiMwXTUkr/fNr32+9p0Wn4YM9w+8yiQvQQP4srtI00pIomJkQWCx+eaps4BW7CDMB9j2s/aeXoo+qAIOBO1/Zr3UGshFRI1OK33EHmAjZXyHVs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272142; c=relaxed/simple; bh=iBw2fRBxTWbBanD2uS/V/irTV/7RnVWvYbjyP67G2l4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=prK1qgOCdj7L3z6GhCJvb6QED2TIRlcHnYZVqFOphZ9xVx0ZvQydwETvlWx5IxHFIaNx1eE18d2ZqvaNX2tKjcuiTo+KS/ZoRVzB9xTS8LH59k9QPKiPyAInFtTiSZeBv9vo3xZEmW75ZBwGMLaj8qS1j5LU6Pg0ht3S9BUc+8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=ZK8vBle0; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="ZK8vBle0" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5C80A32D1; Wed, 15 Apr 2026 09:55:33 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D48E13F7D8; Wed, 15 Apr 2026 09:55:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776272139; bh=iBw2fRBxTWbBanD2uS/V/irTV/7RnVWvYbjyP67G2l4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZK8vBle09HjXzXJAbzE37AN8lpfPRIsy2V9PFUdiNWckYfH0ZveZw+1ZpvvhgRgKe hai/TK8WykxKxQb2dHylstVHMyF6VxTmQLdPVbfdA6hja3xDVOiHt75Cr3OGjar2fI 1drv3IVtzX0AuSQOUIPsCxQVn/nur0H+1mjIL9yE= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v5 03/12] coresight: etm4x: introduce struct etm4_caps Date: Wed, 15 Apr 2026 17:55:19 +0100 Message-Id: <20260415165528.3369607-4-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260415165528.3369607-1-yeoreum.yun@arm.com> References: <20260415165528.3369607-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce struct etm4_caps to describe ETMv4 capabilities and move capabilities information into it. Reviewed-by: Leo Yan Signed-off-by: Yeoreum Yun --- .../coresight/coresight-etm4x-core.c | 234 +++++++++--------- .../coresight/coresight-etm4x-sysfs.c | 192 ++++++++------ drivers/hwtracing/coresight/coresight-etm4x.h | 176 ++++++------- 3 files changed, 329 insertions(+), 273 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index ba5b8b423bd4..b2b092a76eb5 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -88,8 +88,9 @@ static int etm4_probe_cpu(unsigned int cpu); */ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) { - return (n < drvdata->nr_ss_cmp) && - drvdata->nr_pe_cmp && + const struct etmv4_caps *caps =3D &drvdata->caps; + + return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp && (drvdata->config.ss_status[n] & TRCSSCSRn_PC); } =20 @@ -160,17 +161,20 @@ static void ete_sysreg_write(u64 val, u32 offset, boo= l _relaxed, bool _64bit) static void etm_detect_os_lock(struct etmv4_drvdata *drvdata, struct csdev_access *csa) { + struct etmv4_caps *caps =3D &drvdata->caps; u32 oslsr =3D etm4x_relaxed_read32(csa, TRCOSLSR); =20 - drvdata->os_lock_model =3D ETM_OSLSR_OSLM(oslsr); + caps->os_lock_model =3D ETM_OSLSR_OSLM(oslsr); } =20 static void etm_write_os_lock(struct etmv4_drvdata *drvdata, struct csdev_access *csa, u32 val) { + const struct etmv4_caps *caps =3D &drvdata->caps; + val =3D !!val; =20 - switch (drvdata->os_lock_model) { + switch (caps->os_lock_model) { case ETM_OSLOCK_PRESENT: etm4x_relaxed_write32(csa, val, TRCOSLAR); break; @@ -179,7 +183,7 @@ static void etm_write_os_lock(struct etmv4_drvdata *drv= data, break; default: pr_warn_once("CPU%d: Unsupported Trace OSLock model: %x\n", - smp_processor_id(), drvdata->os_lock_model); + smp_processor_id(), caps->os_lock_model); fallthrough; case ETM_OSLOCK_NI: return; @@ -494,6 +498,7 @@ static int etm4_enable_trace_unit(struct etmv4_drvdata = *drvdata) static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; struct coresight_device *csdev =3D drvdata->csdev; struct device *etm_dev =3D &csdev->dev; @@ -525,14 +530,14 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvda= ta) if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1)) dev_err(etm_dev, "timeout while waiting for Idle Trace Status\n"); - if (drvdata->nr_pe) + if (caps->nr_pe) etm4x_relaxed_write32(csa, config->pe_sel, TRCPROCSELR); etm4x_relaxed_write32(csa, config->cfg, TRCCONFIGR); /* nothing specific implemented */ etm4x_relaxed_write32(csa, 0x0, TRCAUXCTLR); etm4x_relaxed_write32(csa, config->eventctrl0, TRCEVENTCTL0R); etm4x_relaxed_write32(csa, config->eventctrl1, TRCEVENTCTL1R); - if (drvdata->stallctl) + if (caps->stallctl) etm4x_relaxed_write32(csa, config->stall_ctrl, TRCSTALLCTLR); etm4x_relaxed_write32(csa, config->ts_ctrl, TRCTSCTLR); etm4x_relaxed_write32(csa, config->syncfreq, TRCSYNCPR); @@ -542,19 +547,19 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvda= ta) etm4x_relaxed_write32(csa, config->vinst_ctrl, TRCVICTLR); etm4x_relaxed_write32(csa, config->viiectlr, TRCVIIECTLR); etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR); - if (drvdata->nr_pe_cmp) + if (caps->nr_pe_cmp) etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); =20 - if (drvdata->nrseqstate) { - for (i =3D 0; i < drvdata->nrseqstate - 1; i++) + if (caps->nrseqstate) { + for (i =3D 0; i < caps->nrseqstate - 1; i++) etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); =20 etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); } - if (drvdata->numextinsel) + if (caps->numextinsel) etm4x_relaxed_write32(csa, config->ext_inp, TRCEXTINSELR); - for (i =3D 0; i < drvdata->nr_cntr; i++) { + for (i =3D 0; i < caps->nr_cntr; i++) { etm4x_relaxed_write32(csa, config->cntrldvr[i], TRCCNTRLDVRn(i)); etm4x_relaxed_write32(csa, config->cntr_ctrl[i], TRCCNTCTLRn(i)); etm4x_relaxed_write32(csa, config->cntr_val[i], TRCCNTVRn(i)); @@ -564,10 +569,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvda= ta) * Resource selector pair 0 is always implemented and reserved. As * such start at 2. */ - for (i =3D 2; i < drvdata->nr_resource * 2; i++) + for (i =3D 2; i < caps->nr_resource * 2; i++) etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); =20 - for (i =3D 0; i < drvdata->nr_ss_cmp; i++) { + for (i =3D 0; i < caps->nr_ss_cmp; i++) { /* always clear status bit on restart if using single-shot */ if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) config->ss_status[i] &=3D ~TRCSSCSRn_STATUS; @@ -576,23 +581,23 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvda= ta) if (etm4x_sspcicrn_present(drvdata, i)) etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); } - for (i =3D 0; i < drvdata->nr_addr_cmp * 2; i++) { + for (i =3D 0; i < caps->nr_addr_cmp * 2; i++) { etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i)); etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); } - for (i =3D 0; i < drvdata->numcidc; i++) + for (i =3D 0; i < caps->numcidc; i++) etm4x_relaxed_write64(csa, config->ctxid_pid[i], TRCCIDCVRn(i)); etm4x_relaxed_write32(csa, config->ctxid_mask0, TRCCIDCCTLR0); - if (drvdata->numcidc > 4) + if (caps->numcidc > 4) etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1); =20 - for (i =3D 0; i < drvdata->numvmidc; i++) + for (i =3D 0; i < caps->numvmidc; i++) etm4x_relaxed_write64(csa, config->vmid_val[i], TRCVMIDCVRn(i)); etm4x_relaxed_write32(csa, config->vmid_mask0, TRCVMIDCCTLR0); - if (drvdata->numvmidc > 4) + if (caps->numvmidc > 4) etm4x_relaxed_write32(csa, config->vmid_mask1, TRCVMIDCCTLR1); =20 - if (!drvdata->skip_power_up) { + if (!caps->skip_power_up) { u32 trcpdcr =3D etm4x_relaxed_read32(csa, TRCPDCR); =20 /* @@ -668,19 +673,20 @@ static int etm4_config_timestamp_event(struct etmv4_d= rvdata *drvdata, { int ctridx; int rselector; + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 /* No point in trying if we don't have at least one counter */ - if (!drvdata->nr_cntr) + if (!caps->nr_cntr) return -EINVAL; =20 /* Find a counter that hasn't been initialised */ - for (ctridx =3D 0; ctridx < drvdata->nr_cntr; ctridx++) + for (ctridx =3D 0; ctridx < caps->nr_cntr; ctridx++) if (config->cntr_val[ctridx] =3D=3D 0) break; =20 /* All the counters have been configured already, bail out */ - if (ctridx =3D=3D drvdata->nr_cntr) { + if (ctridx =3D=3D caps->nr_cntr) { pr_debug("%s: no available counter found\n", __func__); return -ENOSPC; } @@ -696,11 +702,11 @@ static int etm4_config_timestamp_event(struct etmv4_d= rvdata *drvdata, * ETMIDR4 gives the number of resource selector _pairs_, hence multiply * by 2. */ - for (rselector =3D 2; rselector < drvdata->nr_resource * 2; rselector++) + for (rselector =3D 2; rselector < caps->nr_resource * 2; rselector++) if (!config->res_ctrl[rselector]) break; =20 - if (rselector =3D=3D drvdata->nr_resource * 2) { + if (rselector =3D=3D caps->nr_resource * 2) { pr_debug("%s: no available resource selector found\n", __func__); return -ENOSPC; @@ -751,6 +757,7 @@ static int etm4_parse_event_config(struct coresight_dev= ice *csdev, { int ret =3D 0; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; struct perf_event_attr max_timestamp =3D { .ATTR_CFG_FLD_timestamp_CFG =3D U64_MAX, @@ -790,8 +797,8 @@ static int etm4_parse_event_config(struct coresight_dev= ice *csdev, cc_threshold =3D ATTR_CFG_GET_FLD(attr, cc_threshold); if (!cc_threshold) cc_threshold =3D ETM_CYC_THRESHOLD_DEFAULT; - if (cc_threshold < drvdata->ccitmin) - cc_threshold =3D drvdata->ccitmin; + if (cc_threshold < caps->ccitmin) + cc_threshold =3D caps->ccitmin; config->ccctlr =3D cc_threshold; } =20 @@ -839,7 +846,7 @@ static int etm4_parse_event_config(struct coresight_dev= ice *csdev, } =20 /* return stack - enable if selected and supported */ - if (ATTR_CFG_GET_FLD(attr, retstack) && drvdata->retstack) + if (ATTR_CFG_GET_FLD(attr, retstack) && caps->retstack) /* bit[12], Return stack enable bit */ config->cfg |=3D TRCCONFIGR_RS; =20 @@ -855,7 +862,7 @@ static int etm4_parse_event_config(struct coresight_dev= ice *csdev, =20 /* branch broadcast - enable if selected and supported */ if (ATTR_CFG_GET_FLD(attr, branch_broadcast)) { - if (!drvdata->trcbb) { + if (!caps->trcbb) { /* * Missing BB support could cause silent decode errors * so fail to open if it's not supported. @@ -1030,6 +1037,7 @@ static void etm4_disable_trace_unit(struct etmv4_drvd= ata *drvdata) static void etm4_disable_hw(struct etmv4_drvdata *drvdata) { u32 control; + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; struct coresight_device *csdev =3D drvdata->csdev; struct csdev_access *csa =3D &csdev->access; @@ -1038,7 +1046,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drv= data) etm4_cs_unlock(drvdata, csa); etm4_disable_arch_specific(drvdata); =20 - if (!drvdata->skip_power_up) { + if (!caps->skip_power_up) { /* power can be removed from the trace unit now */ control =3D etm4x_relaxed_read32(csa, TRCPDCR); control &=3D ~TRCPDCR_PU; @@ -1048,13 +1056,13 @@ static void etm4_disable_hw(struct etmv4_drvdata *d= rvdata) etm4_disable_trace_unit(drvdata); =20 /* read the status of the single shot comparators */ - for (i =3D 0; i < drvdata->nr_ss_cmp; i++) { + for (i =3D 0; i < caps->nr_ss_cmp; i++) { config->ss_status[i] =3D etm4x_relaxed_read32(csa, TRCSSCSRn(i)); } =20 /* read back the current counter values */ - for (i =3D 0; i < drvdata->nr_cntr; i++) { + for (i =3D 0; i < caps->nr_cntr; i++) { config->cntr_val[i] =3D etm4x_relaxed_read32(csa, TRCCNTVRn(i)); } @@ -1352,7 +1360,7 @@ static struct midr_range etm_wrong_ccitmin_cpus[] =3D= { {}, }; =20 -static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata) +static void etm4_fixup_wrong_ccitmin(struct etmv4_caps *caps) { /* * Erratum affected cpus will read 256 as the minimum @@ -1362,8 +1370,8 @@ static void etm4_fixup_wrong_ccitmin(struct etmv4_drv= data *drvdata) * this problem. */ if (is_midr_in_range_list(etm_wrong_ccitmin_cpus)) { - if (drvdata->ccitmin =3D=3D 256) - drvdata->ccitmin =3D 4; + if (caps->ccitmin =3D=3D 256) + caps->ccitmin =3D 4; } } =20 @@ -1376,11 +1384,13 @@ static void etm4_init_arch_data(void *info) u32 etmidr5; struct etm4_init_arg *init_arg =3D info; struct etmv4_drvdata *drvdata; + struct etmv4_caps *caps; struct csdev_access *csa; struct device *dev =3D init_arg->dev; int i; =20 drvdata =3D dev_get_drvdata(init_arg->dev); + caps =3D &drvdata->caps; csa =3D init_arg->csa; =20 /* @@ -1393,7 +1403,7 @@ static void etm4_init_arch_data(void *info) =20 if (!csa->io_mem || fwnode_property_present(dev_fwnode(dev), "qcom,skip-power-up")) - drvdata->skip_power_up =3D true; + caps->skip_power_up =3D true; =20 /* Detect the support for OS Lock before we actually use it */ etm_detect_os_lock(drvdata, csa); @@ -1408,71 +1418,71 @@ static void etm4_init_arch_data(void *info) etmidr0 =3D etm4x_relaxed_read32(csa, TRCIDR0); =20 /* INSTP0, bits[2:1] P0 tracing support field */ - drvdata->instrp0 =3D !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) =3D=3D 0b= 11); + caps->instrp0 =3D !!(FIELD_GET(TRCIDR0_INSTP0_MASK, etmidr0) =3D=3D 0b11); /* TRCBB, bit[5] Branch broadcast tracing support bit */ - drvdata->trcbb =3D !!(etmidr0 & TRCIDR0_TRCBB); + caps->trcbb =3D !!(etmidr0 & TRCIDR0_TRCBB); /* TRCCOND, bit[6] Conditional instruction tracing support bit */ - drvdata->trccond =3D !!(etmidr0 & TRCIDR0_TRCCOND); + caps->trccond =3D !!(etmidr0 & TRCIDR0_TRCCOND); /* TRCCCI, bit[7] Cycle counting instruction bit */ - drvdata->trccci =3D !!(etmidr0 & TRCIDR0_TRCCCI); + caps->trccci =3D !!(etmidr0 & TRCIDR0_TRCCCI); /* RETSTACK, bit[9] Return stack bit */ - drvdata->retstack =3D !!(etmidr0 & TRCIDR0_RETSTACK); + caps->retstack =3D !!(etmidr0 & TRCIDR0_RETSTACK); /* NUMEVENT, bits[11:10] Number of events field */ - drvdata->nr_event =3D FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0); + caps->nr_event =3D FIELD_GET(TRCIDR0_NUMEVENT_MASK, etmidr0); /* QSUPP, bits[16:15] Q element support field */ - drvdata->q_support =3D FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0); - if (drvdata->q_support) - drvdata->q_filt =3D !!(etmidr0 & TRCIDR0_QFILT); + caps->q_support =3D FIELD_GET(TRCIDR0_QSUPP_MASK, etmidr0); + if (caps->q_support) + caps->q_filt =3D !!(etmidr0 & TRCIDR0_QFILT); /* TSSIZE, bits[28:24] Global timestamp size field */ - drvdata->ts_size =3D FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0); + caps->ts_size =3D FIELD_GET(TRCIDR0_TSSIZE_MASK, etmidr0); =20 /* maximum size of resources */ etmidr2 =3D etm4x_relaxed_read32(csa, TRCIDR2); /* CIDSIZE, bits[9:5] Indicates the Context ID size */ - drvdata->ctxid_size =3D FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2); + caps->ctxid_size =3D FIELD_GET(TRCIDR2_CIDSIZE_MASK, etmidr2); /* VMIDSIZE, bits[14:10] Indicates the VMID size */ - drvdata->vmid_size =3D FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2); + caps->vmid_size =3D FIELD_GET(TRCIDR2_VMIDSIZE_MASK, etmidr2); /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */ - drvdata->ccsize =3D FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2); + caps->ccsize =3D FIELD_GET(TRCIDR2_CCSIZE_MASK, etmidr2); =20 etmidr3 =3D etm4x_relaxed_read32(csa, TRCIDR3); /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ - drvdata->ccitmin =3D FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3); - etm4_fixup_wrong_ccitmin(drvdata); + caps->ccitmin =3D FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3); + etm4_fixup_wrong_ccitmin(caps); =20 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ - drvdata->s_ex_level =3D FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3); - drvdata->config.s_ex_level =3D drvdata->s_ex_level; + caps->s_ex_level =3D FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3); + drvdata->config.s_ex_level =3D caps->s_ex_level; /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ - drvdata->ns_ex_level =3D FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3); + caps->ns_ex_level =3D FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3); /* * TRCERR, bit[24] whether a trace unit can trace a * system error exception. */ - drvdata->trc_error =3D !!(etmidr3 & TRCIDR3_TRCERR); + caps->trc_error =3D !!(etmidr3 & TRCIDR3_TRCERR); /* SYNCPR, bit[25] implementation has a fixed synchronization period? */ - drvdata->syncpr =3D !!(etmidr3 & TRCIDR3_SYNCPR); + caps->syncpr =3D !!(etmidr3 & TRCIDR3_SYNCPR); /* STALLCTL, bit[26] is stall control implemented? */ - drvdata->stallctl =3D !!(etmidr3 & TRCIDR3_STALLCTL); + caps->stallctl =3D !!(etmidr3 & TRCIDR3_STALLCTL); /* SYSSTALL, bit[27] implementation can support stall control? */ - drvdata->sysstall =3D !!(etmidr3 & TRCIDR3_SYSSTALL); + caps->sysstall =3D !!(etmidr3 & TRCIDR3_SYSSTALL); /* * NUMPROC - the number of PEs available for tracing, 5bits * =3D TRCIDR3.bits[13:12]bits[30:28] * bits[4:3] =3D TRCIDR3.bits[13:12] (since etm-v4.2, otherwise RES0) * bits[3:0] =3D TRCIDR3.bits[30:28] */ - drvdata->nr_pe =3D (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) | - FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3); + caps->nr_pe =3D (FIELD_GET(TRCIDR3_NUMPROC_HI_MASK, etmidr3) << 3) | + FIELD_GET(TRCIDR3_NUMPROC_LO_MASK, etmidr3); /* NOOVERFLOW, bit[31] is trace overflow prevention supported */ - drvdata->nooverflow =3D !!(etmidr3 & TRCIDR3_NOOVERFLOW); + caps->nooverflow =3D !!(etmidr3 & TRCIDR3_NOOVERFLOW); =20 /* number of resources trace unit supports */ etmidr4 =3D etm4x_relaxed_read32(csa, TRCIDR4); /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */ - drvdata->nr_addr_cmp =3D FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4); + caps->nr_addr_cmp =3D FIELD_GET(TRCIDR4_NUMACPAIRS_MASK, etmidr4); /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */ - drvdata->nr_pe_cmp =3D FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4); + caps->nr_pe_cmp =3D FIELD_GET(TRCIDR4_NUMPC_MASK, etmidr4); /* * NUMRSPAIR, bits[19:16] * The number of resource pairs conveyed by the HW starts at 0, i.e a @@ -1483,41 +1493,41 @@ static void etm4_init_arch_data(void *info) * the default TRUE and FALSE resource selectors are omitted. * Otherwise for values 0x1 and above the number is N + 1 as per v4.2. */ - drvdata->nr_resource =3D FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4); - if ((drvdata->arch < ETM_ARCH_V4_3) || (drvdata->nr_resource > 0)) - drvdata->nr_resource +=3D 1; + caps->nr_resource =3D FIELD_GET(TRCIDR4_NUMRSPAIR_MASK, etmidr4); + if ((drvdata->arch < ETM_ARCH_V4_3) || (caps->nr_resource > 0)) + caps->nr_resource +=3D 1; /* * NUMSSCC, bits[23:20] the number of single-shot * comparator control for tracing. Read any status regs as these * also contain RO capability data. */ - drvdata->nr_ss_cmp =3D FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); - for (i =3D 0; i < drvdata->nr_ss_cmp; i++) { + caps->nr_ss_cmp =3D FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); + for (i =3D 0; i < caps->nr_ss_cmp; i++) { drvdata->config.ss_status[i] =3D etm4x_relaxed_read32(csa, TRCSSCSRn(i)); } /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ - drvdata->numcidc =3D FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4); + caps->numcidc =3D FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4); /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */ - drvdata->numvmidc =3D FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4); + caps->numvmidc =3D FIELD_GET(TRCIDR4_NUMVMIDC_MASK, etmidr4); =20 etmidr5 =3D etm4x_relaxed_read32(csa, TRCIDR5); /* NUMEXTIN, bits[8:0] number of external inputs implemented */ - drvdata->nr_ext_inp =3D FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); - drvdata->numextinsel =3D FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); + caps->nr_ext_inp =3D FIELD_GET(TRCIDR5_NUMEXTIN_MASK, etmidr5); + caps->numextinsel =3D FIELD_GET(TRCIDR5_NUMEXTINSEL_MASK, etmidr5); /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */ - drvdata->trcid_size =3D FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); + caps->trcid_size =3D FIELD_GET(TRCIDR5_TRACEIDSIZE_MASK, etmidr5); /* ATBTRIG, bit[22] implementation can support ATB triggers? */ - drvdata->atbtrig =3D !!(etmidr5 & TRCIDR5_ATBTRIG); + caps->atbtrig =3D !!(etmidr5 & TRCIDR5_ATBTRIG); /* * LPOVERRIDE, bit[23] implementation supports * low-power state override */ - drvdata->lpoverride =3D (etmidr5 & TRCIDR5_LPOVERRIDE) && (!drvdata->skip= _power_up); + caps->lpoverride =3D (etmidr5 & TRCIDR5_LPOVERRIDE) && (!caps->skip_power= _up); /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */ - drvdata->nrseqstate =3D FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5); + caps->nrseqstate =3D FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5); /* NUMCNTR, bits[30:28] number of counters available for tracing */ - drvdata->nr_cntr =3D FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5); + caps->nr_cntr =3D FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5); =20 coresight_clear_self_claim_tag_unlocked(csa); etm4_cs_lock(drvdata, csa); @@ -1693,7 +1703,7 @@ static int etm4_get_next_comparator(struct etmv4_drvd= ata *drvdata, u32 type) * nr_addr_cmp holds the number of comparator _pair_, so time 2 * for the total number of comparators. */ - nr_comparator =3D drvdata->nr_addr_cmp * 2; + nr_comparator =3D drvdata->caps.nr_addr_cmp * 2; =20 /* Go through the tally of comparators looking for a free one. */ while (index < nr_comparator) { @@ -1871,6 +1881,7 @@ static int etm4_dying_cpu(unsigned int cpu) static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) { int i, ret =3D 0; + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_save_state *state; struct coresight_device *csdev =3D drvdata->csdev; struct csdev_access *csa; @@ -1907,57 +1918,57 @@ static int __etm4_cpu_save(struct etmv4_drvdata *dr= vdata) =20 state =3D drvdata->save_state; =20 - if (drvdata->nr_pe) + if (caps->nr_pe) state->trcprocselr =3D etm4x_read32(csa, TRCPROCSELR); state->trcconfigr =3D etm4x_read32(csa, TRCCONFIGR); state->trcauxctlr =3D etm4x_read32(csa, TRCAUXCTLR); state->trceventctl0r =3D etm4x_read32(csa, TRCEVENTCTL0R); state->trceventctl1r =3D etm4x_read32(csa, TRCEVENTCTL1R); - if (drvdata->stallctl) + if (caps->stallctl) state->trcstallctlr =3D etm4x_read32(csa, TRCSTALLCTLR); state->trctsctlr =3D etm4x_read32(csa, TRCTSCTLR); state->trcsyncpr =3D etm4x_read32(csa, TRCSYNCPR); state->trcccctlr =3D etm4x_read32(csa, TRCCCCTLR); state->trcbbctlr =3D etm4x_read32(csa, TRCBBCTLR); state->trctraceidr =3D etm4x_read32(csa, TRCTRACEIDR); - if (drvdata->q_filt) + if (caps->q_filt) state->trcqctlr =3D etm4x_read32(csa, TRCQCTLR); =20 state->trcvictlr =3D etm4x_read32(csa, TRCVICTLR); state->trcviiectlr =3D etm4x_read32(csa, TRCVIIECTLR); state->trcvissctlr =3D etm4x_read32(csa, TRCVISSCTLR); - if (drvdata->nr_pe_cmp) + if (caps->nr_pe_cmp) state->trcvipcssctlr =3D etm4x_read32(csa, TRCVIPCSSCTLR); =20 - if (drvdata->nrseqstate) { - for (i =3D 0; i < drvdata->nrseqstate - 1; i++) + if (caps->nrseqstate) { + for (i =3D 0; i < caps->nrseqstate - 1; i++) state->trcseqevr[i] =3D etm4x_read32(csa, TRCSEQEVRn(i)); =20 state->trcseqrstevr =3D etm4x_read32(csa, TRCSEQRSTEVR); state->trcseqstr =3D etm4x_read32(csa, TRCSEQSTR); } =20 - if (drvdata->numextinsel) + if (caps->numextinsel) state->trcextinselr =3D etm4x_read32(csa, TRCEXTINSELR); =20 - for (i =3D 0; i < drvdata->nr_cntr; i++) { + for (i =3D 0; i < caps->nr_cntr; i++) { state->trccntrldvr[i] =3D etm4x_read32(csa, TRCCNTRLDVRn(i)); state->trccntctlr[i] =3D etm4x_read32(csa, TRCCNTCTLRn(i)); state->trccntvr[i] =3D etm4x_read32(csa, TRCCNTVRn(i)); } =20 /* Resource selector pair 0 is reserved */ - for (i =3D 2; i < drvdata->nr_resource * 2; i++) + for (i =3D 2; i < caps->nr_resource * 2; i++) state->trcrsctlr[i] =3D etm4x_read32(csa, TRCRSCTLRn(i)); =20 - for (i =3D 0; i < drvdata->nr_ss_cmp; i++) { + for (i =3D 0; i < caps->nr_ss_cmp; i++) { state->trcssccr[i] =3D etm4x_read32(csa, TRCSSCCRn(i)); state->trcsscsr[i] =3D etm4x_read32(csa, TRCSSCSRn(i)); if (etm4x_sspcicrn_present(drvdata, i)) state->trcsspcicr[i] =3D etm4x_read32(csa, TRCSSPCICRn(i)); } =20 - for (i =3D 0; i < drvdata->nr_addr_cmp * 2; i++) { + for (i =3D 0; i < caps->nr_addr_cmp * 2; i++) { state->trcacvr[i] =3D etm4x_read64(csa, TRCACVRn(i)); state->trcacatr[i] =3D etm4x_read64(csa, TRCACATRn(i)); } @@ -1969,23 +1980,23 @@ static int __etm4_cpu_save(struct etmv4_drvdata *dr= vdata) * unit") of ARM IHI 0064D. */ =20 - for (i =3D 0; i < drvdata->numcidc; i++) + for (i =3D 0; i < caps->numcidc; i++) state->trccidcvr[i] =3D etm4x_read64(csa, TRCCIDCVRn(i)); =20 - for (i =3D 0; i < drvdata->numvmidc; i++) + for (i =3D 0; i < caps->numvmidc; i++) state->trcvmidcvr[i] =3D etm4x_read64(csa, TRCVMIDCVRn(i)); =20 state->trccidcctlr0 =3D etm4x_read32(csa, TRCCIDCCTLR0); - if (drvdata->numcidc > 4) + if (caps->numcidc > 4) state->trccidcctlr1 =3D etm4x_read32(csa, TRCCIDCCTLR1); =20 state->trcvmidcctlr0 =3D etm4x_read32(csa, TRCVMIDCCTLR0); - if (drvdata->numvmidc > 4) + if (caps->numvmidc > 4) state->trcvmidcctlr0 =3D etm4x_read32(csa, TRCVMIDCCTLR1); =20 state->trcclaimset =3D etm4x_read32(csa, TRCCLAIMCLR); =20 - if (!drvdata->skip_power_up) + if (!caps->skip_power_up) state->trcpdcr =3D etm4x_read32(csa, TRCPDCR); =20 /* wait for TRCSTATR.IDLE to go up */ @@ -2002,7 +2013,7 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvd= ata) * potentially save power on systems that respect the TRCPDCR_PU * despite requesting software to save/restore state. */ - if (!drvdata->skip_power_up) + if (!caps->skip_power_up) etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), TRCPDCR); out: @@ -2029,6 +2040,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdat= a) static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) { int i; + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_save_state *state =3D drvdata->save_state; struct csdev_access *csa =3D &drvdata->csdev->access; =20 @@ -2038,77 +2050,77 @@ static void __etm4_cpu_restore(struct etmv4_drvdata= *drvdata) etm4_cs_unlock(drvdata, csa); etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); =20 - if (drvdata->nr_pe) + if (caps->nr_pe) etm4x_relaxed_write32(csa, state->trcprocselr, TRCPROCSELR); etm4x_relaxed_write32(csa, state->trcconfigr, TRCCONFIGR); etm4x_relaxed_write32(csa, state->trcauxctlr, TRCAUXCTLR); etm4x_relaxed_write32(csa, state->trceventctl0r, TRCEVENTCTL0R); etm4x_relaxed_write32(csa, state->trceventctl1r, TRCEVENTCTL1R); - if (drvdata->stallctl) + if (caps->stallctl) etm4x_relaxed_write32(csa, state->trcstallctlr, TRCSTALLCTLR); etm4x_relaxed_write32(csa, state->trctsctlr, TRCTSCTLR); etm4x_relaxed_write32(csa, state->trcsyncpr, TRCSYNCPR); etm4x_relaxed_write32(csa, state->trcccctlr, TRCCCCTLR); etm4x_relaxed_write32(csa, state->trcbbctlr, TRCBBCTLR); etm4x_relaxed_write32(csa, state->trctraceidr, TRCTRACEIDR); - if (drvdata->q_filt) + if (caps->q_filt) etm4x_relaxed_write32(csa, state->trcqctlr, TRCQCTLR); =20 etm4x_relaxed_write32(csa, state->trcvictlr, TRCVICTLR); etm4x_relaxed_write32(csa, state->trcviiectlr, TRCVIIECTLR); etm4x_relaxed_write32(csa, state->trcvissctlr, TRCVISSCTLR); - if (drvdata->nr_pe_cmp) + if (caps->nr_pe_cmp) etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR); =20 - if (drvdata->nrseqstate) { - for (i =3D 0; i < drvdata->nrseqstate - 1; i++) + if (caps->nrseqstate) { + for (i =3D 0; i < caps->nrseqstate - 1; i++) etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); =20 etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); } - if (drvdata->numextinsel) + if (caps->numextinsel) etm4x_relaxed_write32(csa, state->trcextinselr, TRCEXTINSELR); =20 - for (i =3D 0; i < drvdata->nr_cntr; i++) { + for (i =3D 0; i < caps->nr_cntr; i++) { etm4x_relaxed_write32(csa, state->trccntrldvr[i], TRCCNTRLDVRn(i)); etm4x_relaxed_write32(csa, state->trccntctlr[i], TRCCNTCTLRn(i)); etm4x_relaxed_write32(csa, state->trccntvr[i], TRCCNTVRn(i)); } =20 /* Resource selector pair 0 is reserved */ - for (i =3D 2; i < drvdata->nr_resource * 2; i++) + for (i =3D 2; i < caps->nr_resource * 2; i++) etm4x_relaxed_write32(csa, state->trcrsctlr[i], TRCRSCTLRn(i)); =20 - for (i =3D 0; i < drvdata->nr_ss_cmp; i++) { + for (i =3D 0; i < caps->nr_ss_cmp; i++) { etm4x_relaxed_write32(csa, state->trcssccr[i], TRCSSCCRn(i)); etm4x_relaxed_write32(csa, state->trcsscsr[i], TRCSSCSRn(i)); if (etm4x_sspcicrn_present(drvdata, i)) etm4x_relaxed_write32(csa, state->trcsspcicr[i], TRCSSPCICRn(i)); } =20 - for (i =3D 0; i < drvdata->nr_addr_cmp * 2; i++) { + for (i =3D 0; i < caps->nr_addr_cmp * 2; i++) { etm4x_relaxed_write64(csa, state->trcacvr[i], TRCACVRn(i)); etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i)); } =20 - for (i =3D 0; i < drvdata->numcidc; i++) + for (i =3D 0; i < caps->numcidc; i++) etm4x_relaxed_write64(csa, state->trccidcvr[i], TRCCIDCVRn(i)); =20 - for (i =3D 0; i < drvdata->numvmidc; i++) + for (i =3D 0; i < caps->numvmidc; i++) etm4x_relaxed_write64(csa, state->trcvmidcvr[i], TRCVMIDCVRn(i)); =20 etm4x_relaxed_write32(csa, state->trccidcctlr0, TRCCIDCCTLR0); - if (drvdata->numcidc > 4) + if (caps->numcidc > 4) etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1); =20 etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR0); - if (drvdata->numvmidc > 4) + if (caps->numvmidc > 4) etm4x_relaxed_write32(csa, state->trcvmidcctlr0, TRCVMIDCCTLR1); =20 etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET); =20 - if (!drvdata->skip_power_up) + if (!caps->skip_power_up) etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR); =20 /* diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm4x-sysfs.c index d866dcfa2a36..8bd28e71d4c9 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -62,8 +62,9 @@ static ssize_t nr_pe_cmp_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; =20 - val =3D drvdata->nr_pe_cmp; + val =3D caps->nr_pe_cmp; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_pe_cmp); @@ -74,8 +75,9 @@ static ssize_t nr_addr_cmp_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; =20 - val =3D drvdata->nr_addr_cmp; + val =3D caps->nr_addr_cmp; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_addr_cmp); @@ -86,8 +88,9 @@ static ssize_t nr_cntr_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; =20 - val =3D drvdata->nr_cntr; + val =3D caps->nr_cntr; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_cntr); @@ -98,8 +101,9 @@ static ssize_t nr_ext_inp_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; =20 - val =3D drvdata->nr_ext_inp; + val =3D caps->nr_ext_inp; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_ext_inp); @@ -110,8 +114,9 @@ static ssize_t numcidc_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; =20 - val =3D drvdata->numcidc; + val =3D caps->numcidc; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(numcidc); @@ -122,8 +127,9 @@ static ssize_t numvmidc_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; =20 - val =3D drvdata->numvmidc; + val =3D caps->numvmidc; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(numvmidc); @@ -134,8 +140,9 @@ static ssize_t nrseqstate_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; =20 - val =3D drvdata->nrseqstate; + val =3D caps->nrseqstate; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nrseqstate); @@ -146,8 +153,9 @@ static ssize_t nr_resource_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; =20 - val =3D drvdata->nr_resource; + val =3D caps->nr_resource; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_resource); @@ -158,8 +166,9 @@ static ssize_t nr_ss_cmp_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; =20 - val =3D drvdata->nr_ss_cmp; + val =3D caps->nr_ss_cmp; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_ss_cmp); @@ -171,6 +180,7 @@ static ssize_t reset_store(struct device *dev, int i; unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) @@ -200,7 +210,7 @@ static ssize_t reset_store(struct device *dev, config->stall_ctrl =3D 0x0; =20 /* Reset trace synchronization period to 2^8 =3D 256 bytes*/ - if (drvdata->syncpr =3D=3D false) + if (!caps->syncpr) config->syncfreq =3D 0x8; =20 /* @@ -209,7 +219,7 @@ static ssize_t reset_store(struct device *dev, * each trace run. */ config->vinst_ctrl =3D FIELD_PREP(TRCVICTLR_EVENT_MASK, 0x01); - if (drvdata->nr_addr_cmp > 0) { + if (caps->nr_addr_cmp > 0) { config->mode |=3D ETM_MODE_VIEWINST_STARTSTOP; /* SSSTATUS, bit[9] */ config->vinst_ctrl |=3D TRCVICTLR_SSSTATUS; @@ -223,7 +233,7 @@ static ssize_t reset_store(struct device *dev, config->vipcssctlr =3D 0x0; =20 /* Disable seq events */ - for (i =3D 0; i < drvdata->nrseqstate-1; i++) + for (i =3D 0; i < caps->nrseqstate - 1; i++) config->seq_ctrl[i] =3D 0x0; config->seq_rst =3D 0x0; config->seq_state =3D 0x0; @@ -232,38 +242,38 @@ static ssize_t reset_store(struct device *dev, config->ext_inp =3D 0x0; =20 config->cntr_idx =3D 0x0; - for (i =3D 0; i < drvdata->nr_cntr; i++) { + for (i =3D 0; i < caps->nr_cntr; i++) { config->cntrldvr[i] =3D 0x0; config->cntr_ctrl[i] =3D 0x0; config->cntr_val[i] =3D 0x0; } =20 config->res_idx =3D 0x0; - for (i =3D 2; i < 2 * drvdata->nr_resource; i++) + for (i =3D 2; i < 2 * caps->nr_resource; i++) config->res_ctrl[i] =3D 0x0; =20 config->ss_idx =3D 0x0; - for (i =3D 0; i < drvdata->nr_ss_cmp; i++) { + for (i =3D 0; i < caps->nr_ss_cmp; i++) { config->ss_ctrl[i] =3D 0x0; config->ss_pe_cmp[i] =3D 0x0; } =20 config->addr_idx =3D 0x0; - for (i =3D 0; i < drvdata->nr_addr_cmp * 2; i++) { + for (i =3D 0; i < caps->nr_addr_cmp * 2; i++) { config->addr_val[i] =3D 0x0; config->addr_acc[i] =3D 0x0; config->addr_type[i] =3D ETM_ADDR_TYPE_NONE; } =20 config->ctxid_idx =3D 0x0; - for (i =3D 0; i < drvdata->numcidc; i++) + for (i =3D 0; i < caps->numcidc; i++) config->ctxid_pid[i] =3D 0x0; =20 config->ctxid_mask0 =3D 0x0; config->ctxid_mask1 =3D 0x0; =20 config->vmid_idx =3D 0x0; - for (i =3D 0; i < drvdata->numvmidc; i++) + for (i =3D 0; i < caps->numvmidc; i++) config->vmid_val[i] =3D 0x0; config->vmid_mask0 =3D 0x0; config->vmid_mask1 =3D 0x0; @@ -297,6 +307,7 @@ static ssize_t mode_store(struct device *dev, { unsigned long val, mode; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) @@ -305,7 +316,7 @@ static ssize_t mode_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); config->mode =3D val & ETMv4_MODE_ALL; =20 - if (drvdata->instrp0 =3D=3D true) { + if (caps->instrp0) { /* start by clearing instruction P0 field */ config->cfg &=3D ~TRCCONFIGR_INSTP0_LOAD_STORE; if (config->mode & ETM_MODE_LOAD) @@ -323,45 +334,44 @@ static ssize_t mode_store(struct device *dev, } =20 /* bit[3], Branch broadcast mode */ - if ((config->mode & ETM_MODE_BB) && (drvdata->trcbb =3D=3D true)) + if ((config->mode & ETM_MODE_BB) && (caps->trcbb)) config->cfg |=3D TRCCONFIGR_BB; else config->cfg &=3D ~TRCCONFIGR_BB; =20 /* bit[4], Cycle counting instruction trace bit */ if ((config->mode & ETMv4_MODE_CYCACC) && - (drvdata->trccci =3D=3D true)) + (caps->trccci =3D=3D true)) config->cfg |=3D TRCCONFIGR_CCI; else config->cfg &=3D ~TRCCONFIGR_CCI; =20 /* bit[6], Context ID tracing bit */ - if ((config->mode & ETMv4_MODE_CTXID) && (drvdata->ctxid_size)) + if ((config->mode & ETMv4_MODE_CTXID) && (caps->ctxid_size)) config->cfg |=3D TRCCONFIGR_CID; else config->cfg &=3D ~TRCCONFIGR_CID; =20 - if ((config->mode & ETM_MODE_VMID) && (drvdata->vmid_size)) + if ((config->mode & ETM_MODE_VMID) && (caps->vmid_size)) config->cfg |=3D TRCCONFIGR_VMID; else config->cfg &=3D ~TRCCONFIGR_VMID; =20 /* bits[10:8], Conditional instruction tracing bit */ mode =3D ETM_MODE_COND(config->mode); - if (drvdata->trccond =3D=3D true) { + if (caps->trccond) { config->cfg &=3D ~TRCCONFIGR_COND_MASK; config->cfg |=3D mode << __bf_shf(TRCCONFIGR_COND_MASK); } =20 /* bit[11], Global timestamp tracing bit */ - if ((config->mode & ETMv4_MODE_TIMESTAMP) && (drvdata->ts_size)) + if ((config->mode & ETMv4_MODE_TIMESTAMP) && (caps->ts_size)) config->cfg |=3D TRCCONFIGR_TS; else config->cfg &=3D ~TRCCONFIGR_TS; =20 /* bit[12], Return stack enable bit */ - if ((config->mode & ETM_MODE_RETURNSTACK) && - (drvdata->retstack =3D=3D true)) + if ((config->mode & ETM_MODE_RETURNSTACK) && (caps->retstack)) config->cfg |=3D TRCCONFIGR_RS; else config->cfg &=3D ~TRCCONFIGR_RS; @@ -375,31 +385,29 @@ static ssize_t mode_store(struct device *dev, * Always set the low bit for any requested mode. Valid combos are * 0b00, 0b01 and 0b11. */ - if (mode && drvdata->q_support) + if (mode && caps->q_support) config->cfg |=3D TRCCONFIGR_QE_W_COUNTS; /* * if supported, Q elements with and without instruction * counts are enabled */ - if ((mode & BIT(1)) && (drvdata->q_support & BIT(1))) + if ((mode & BIT(1)) && (caps->q_support & BIT(1))) config->cfg |=3D TRCCONFIGR_QE_WO_COUNTS; =20 /* bit[11], AMBA Trace Bus (ATB) trigger enable bit */ - if ((config->mode & ETM_MODE_ATB_TRIGGER) && - (drvdata->atbtrig =3D=3D true)) + if ((config->mode & ETM_MODE_ATB_TRIGGER) && (caps->atbtrig)) config->eventctrl1 |=3D TRCEVENTCTL1R_ATB; else config->eventctrl1 &=3D ~TRCEVENTCTL1R_ATB; =20 /* bit[12], Low-power state behavior override bit */ - if ((config->mode & ETM_MODE_LPOVERRIDE) && - (drvdata->lpoverride =3D=3D true)) + if ((config->mode & ETM_MODE_LPOVERRIDE) && (caps->lpoverride)) config->eventctrl1 |=3D TRCEVENTCTL1R_LPOVERRIDE; else config->eventctrl1 &=3D ~TRCEVENTCTL1R_LPOVERRIDE; =20 /* bit[8], Instruction stall bit */ - if ((config->mode & ETM_MODE_ISTALL_EN) && (drvdata->stallctl =3D=3D true= )) + if ((config->mode & ETM_MODE_ISTALL_EN) && (caps->stallctl)) config->stall_ctrl |=3D TRCSTALLCTLR_ISTALL; else config->stall_ctrl &=3D ~TRCSTALLCTLR_ISTALL; @@ -411,8 +419,7 @@ static ssize_t mode_store(struct device *dev, config->stall_ctrl &=3D ~TRCSTALLCTLR_INSTPRIORITY; =20 /* bit[13], Trace overflow prevention bit */ - if ((config->mode & ETM_MODE_NOOVERFLOW) && - (drvdata->nooverflow =3D=3D true)) + if ((config->mode & ETM_MODE_NOOVERFLOW) && (caps->nooverflow)) config->stall_ctrl |=3D TRCSTALLCTLR_NOOVERFLOW; else config->stall_ctrl &=3D ~TRCSTALLCTLR_NOOVERFLOW; @@ -430,8 +437,7 @@ static ssize_t mode_store(struct device *dev, config->vinst_ctrl &=3D ~TRCVICTLR_TRCRESET; =20 /* bit[11], Whether a trace unit must trace a system error exception */ - if ((config->mode & ETM_MODE_TRACE_ERR) && - (drvdata->trc_error =3D=3D true)) + if ((config->mode & ETM_MODE_TRACE_ERR) && (caps->trc_error)) config->vinst_ctrl |=3D TRCVICTLR_TRCERR; else config->vinst_ctrl &=3D ~TRCVICTLR_TRCERR; @@ -463,13 +469,14 @@ static ssize_t pe_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) return -EINVAL; =20 raw_spin_lock(&drvdata->spinlock); - if (val > drvdata->nr_pe) { + if (val > caps->nr_pe) { raw_spin_unlock(&drvdata->spinlock); return -EINVAL; } @@ -498,13 +505,14 @@ static ssize_t event_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) return -EINVAL; =20 raw_spin_lock(&drvdata->spinlock); - switch (drvdata->nr_event) { + switch (caps->nr_event) { case 0x0: /* EVENT0, bits[7:0] */ config->eventctrl0 =3D val & 0xFF; @@ -547,6 +555,7 @@ static ssize_t event_instren_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) @@ -555,7 +564,7 @@ static ssize_t event_instren_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); /* start by clearing all instruction event enable bits */ config->eventctrl1 &=3D ~TRCEVENTCTL1R_INSTEN_MASK; - switch (drvdata->nr_event) { + switch (caps->nr_event) { case 0x0: /* generate Event element for event 1 */ config->eventctrl1 |=3D val & TRCEVENTCTL1R_INSTEN_1; @@ -603,11 +612,12 @@ static ssize_t event_ts_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (!drvdata->ts_size) + if (!caps->ts_size) return -EINVAL; =20 config->ts_ctrl =3D val & ETMv4_EVENT_MASK; @@ -633,11 +643,12 @@ static ssize_t syncfreq_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (drvdata->syncpr =3D=3D true) + if (caps->syncpr) return -EINVAL; =20 config->syncfreq =3D val & ETMv4_SYNC_MASK; @@ -663,6 +674,7 @@ static ssize_t cyc_threshold_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) @@ -670,7 +682,7 @@ static ssize_t cyc_threshold_store(struct device *dev, =20 /* mask off max threshold before checking min value */ val &=3D ETM_CYC_THRESHOLD_MASK; - if (val < drvdata->ccitmin) + if (val < caps->ccitmin) return -EINVAL; =20 config->ccctlr =3D val; @@ -696,13 +708,14 @@ static ssize_t bb_ctrl_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (drvdata->trcbb =3D=3D false) + if (!caps->trcbb) return -EINVAL; - if (!drvdata->nr_addr_cmp) + if (!caps->nr_addr_cmp) return -EINVAL; =20 /* @@ -768,6 +781,7 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) @@ -777,7 +791,7 @@ static ssize_t s_exlevel_vinst_store(struct device *dev, /* clear all EXLEVEL_S bits */ config->vinst_ctrl &=3D ~TRCVICTLR_EXLEVEL_S_MASK; /* enable instruction tracing for corresponding exception level */ - val &=3D drvdata->s_ex_level; + val &=3D caps->s_ex_level; config->vinst_ctrl |=3D val << __bf_shf(TRCVICTLR_EXLEVEL_S_MASK); raw_spin_unlock(&drvdata->spinlock); return size; @@ -803,6 +817,7 @@ static ssize_t ns_exlevel_vinst_store(struct device *de= v, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) @@ -812,7 +827,7 @@ static ssize_t ns_exlevel_vinst_store(struct device *de= v, /* clear EXLEVEL_NS bits */ config->vinst_ctrl &=3D ~TRCVICTLR_EXLEVEL_NS_MASK; /* enable instruction tracing for corresponding exception level */ - val &=3D drvdata->ns_ex_level; + val &=3D caps->ns_ex_level; config->vinst_ctrl |=3D val << __bf_shf(TRCVICTLR_EXLEVEL_NS_MASK); raw_spin_unlock(&drvdata->spinlock); return size; @@ -837,11 +852,12 @@ static ssize_t addr_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (val >=3D drvdata->nr_addr_cmp * 2) + if (val >=3D caps->nr_addr_cmp * 2) return -EINVAL; =20 /* @@ -1060,6 +1076,7 @@ static ssize_t addr_start_store(struct device *dev, u8 idx; unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) @@ -1067,7 +1084,7 @@ static ssize_t addr_start_store(struct device *dev, =20 raw_spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; - if (!drvdata->nr_addr_cmp) { + if (!caps->nr_addr_cmp) { raw_spin_unlock(&drvdata->spinlock); return -EINVAL; } @@ -1115,6 +1132,7 @@ static ssize_t addr_stop_store(struct device *dev, u8 idx; unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) @@ -1122,7 +1140,7 @@ static ssize_t addr_stop_store(struct device *dev, =20 raw_spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; - if (!drvdata->nr_addr_cmp) { + if (!caps->nr_addr_cmp) { raw_spin_unlock(&drvdata->spinlock); return -EINVAL; } @@ -1167,6 +1185,7 @@ static ssize_t addr_ctxtype_store(struct device *dev, u8 idx; char str[10] =3D ""; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (strlen(buf) >=3D 10) @@ -1181,13 +1200,13 @@ static ssize_t addr_ctxtype_store(struct device *de= v, config->addr_acc[idx] &=3D ~TRCACATRn_CONTEXTTYPE_MASK; else if (!strcmp(str, "ctxid")) { /* 0b01 The trace unit performs a Context ID */ - if (drvdata->numcidc) { + if (caps->numcidc) { config->addr_acc[idx] |=3D TRCACATRn_CONTEXTTYPE_CTXID; config->addr_acc[idx] &=3D ~TRCACATRn_CONTEXTTYPE_VMID; } } else if (!strcmp(str, "vmid")) { /* 0b10 The trace unit performs a VMID */ - if (drvdata->numvmidc) { + if (caps->numvmidc) { config->addr_acc[idx] &=3D ~TRCACATRn_CONTEXTTYPE_CTXID; config->addr_acc[idx] |=3D TRCACATRn_CONTEXTTYPE_VMID; } @@ -1196,9 +1215,9 @@ static ssize_t addr_ctxtype_store(struct device *dev, * 0b11 The trace unit performs a Context ID * comparison and a VMID */ - if (drvdata->numcidc) + if (caps->numcidc) config->addr_acc[idx] |=3D TRCACATRn_CONTEXTTYPE_CTXID; - if (drvdata->numvmidc) + if (caps->numvmidc) config->addr_acc[idx] |=3D TRCACATRn_CONTEXTTYPE_VMID; } raw_spin_unlock(&drvdata->spinlock); @@ -1230,14 +1249,15 @@ static ssize_t addr_context_store(struct device *de= v, u8 idx; unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) return -EINVAL; - if ((drvdata->numcidc <=3D 1) && (drvdata->numvmidc <=3D 1)) + if ((caps->numcidc <=3D 1) && (caps->numvmidc <=3D 1)) return -EINVAL; - if (val >=3D (drvdata->numcidc >=3D drvdata->numvmidc ? - drvdata->numcidc : drvdata->numvmidc)) + if (val >=3D (caps->numcidc >=3D caps->numvmidc ? + caps->numcidc : caps->numvmidc)) return -EINVAL; =20 raw_spin_lock(&drvdata->spinlock); @@ -1348,9 +1368,10 @@ static ssize_t vinst_pe_cmp_start_stop_show(struct d= evice *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 - if (!drvdata->nr_pe_cmp) + if (!caps->nr_pe_cmp) return -EINVAL; val =3D config->vipcssctlr; return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); @@ -1361,11 +1382,12 @@ static ssize_t vinst_pe_cmp_start_stop_store(struct= device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (!drvdata->nr_pe_cmp) + if (!caps->nr_pe_cmp) return -EINVAL; =20 raw_spin_lock(&drvdata->spinlock); @@ -1393,13 +1415,14 @@ static ssize_t seq_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 - if (!drvdata->nrseqstate) + if (!caps->nrseqstate) return -EINVAL; if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (val >=3D drvdata->nrseqstate - 1) + if (val >=3D caps->nrseqstate - 1) return -EINVAL; =20 /* @@ -1431,11 +1454,12 @@ static ssize_t seq_state_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (val >=3D drvdata->nrseqstate) + if (val >=3D caps->nrseqstate) return -EINVAL; =20 config->seq_state =3D val; @@ -1498,11 +1522,12 @@ static ssize_t seq_reset_event_store(struct device = *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (!(drvdata->nrseqstate)) + if (!(caps->nrseqstate)) return -EINVAL; =20 config->seq_rst =3D val & ETMv4_EVENT_MASK; @@ -1528,11 +1553,12 @@ static ssize_t cntr_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (val >=3D drvdata->nr_cntr) + if (val >=3D caps->nr_cntr) return -EINVAL; =20 /* @@ -1676,6 +1702,7 @@ static ssize_t res_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) @@ -1684,7 +1711,7 @@ static ssize_t res_idx_store(struct device *dev, * Resource selector pair 0 is always implemented and reserved, * namely an idx with 0 and 1 is illegal. */ - if ((val < 2) || (val >=3D 2 * drvdata->nr_resource)) + if ((val < 2) || (val >=3D 2 * caps->nr_resource)) return -EINVAL; =20 /* @@ -1758,11 +1785,12 @@ static ssize_t sshot_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (val >=3D drvdata->nr_ss_cmp) + if (val >=3D caps->nr_ss_cmp) return -EINVAL; =20 raw_spin_lock(&drvdata->spinlock); @@ -1876,11 +1904,12 @@ static ssize_t ctxid_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (val >=3D drvdata->numcidc) + if (val >=3D caps->numcidc) return -EINVAL; =20 /* @@ -1924,6 +1953,7 @@ static ssize_t ctxid_pid_store(struct device *dev, u8 idx; unsigned long pid; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 /* @@ -1943,7 +1973,7 @@ static ssize_t ctxid_pid_store(struct device *dev, * ctxid comparator is implemented and ctxid is greater than 0 bits * in length */ - if (!drvdata->ctxid_size || !drvdata->numcidc) + if (!caps->ctxid_size || !caps->numcidc) return -EINVAL; if (kstrtoul(buf, 16, &pid)) return -EINVAL; @@ -1985,6 +2015,7 @@ static ssize_t ctxid_masks_store(struct device *dev, u8 i, j, maskbyte; unsigned long val1, val2, mask; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; int nr_inputs; =20 @@ -2000,11 +2031,11 @@ static ssize_t ctxid_masks_store(struct device *dev, * ctxid comparator is implemented and ctxid is greater than 0 bits * in length */ - if (!drvdata->ctxid_size || !drvdata->numcidc) + if (!caps->ctxid_size || !caps->numcidc) return -EINVAL; /* one mask if <=3D 4 comparators, two for up to 8 */ nr_inputs =3D sscanf(buf, "%lx %lx", &val1, &val2); - if ((drvdata->numcidc > 4) && (nr_inputs !=3D 2)) + if ((caps->numcidc > 4) && (nr_inputs !=3D 2)) return -EINVAL; =20 raw_spin_lock(&drvdata->spinlock); @@ -2012,7 +2043,7 @@ static ssize_t ctxid_masks_store(struct device *dev, * each byte[0..3] controls mask value applied to ctxid * comparator[0..3] */ - switch (drvdata->numcidc) { + switch (caps->numcidc) { case 0x1: /* COMP0, bits[7:0] */ config->ctxid_mask0 =3D val1 & 0xFF; @@ -2059,7 +2090,7 @@ static ssize_t ctxid_masks_store(struct device *dev, * of ctxid comparator0 value (corresponding to byte 0) register. */ mask =3D config->ctxid_mask0; - for (i =3D 0; i < drvdata->numcidc; i++) { + for (i =3D 0; i < caps->numcidc; i++) { /* mask value of corresponding ctxid comparator */ maskbyte =3D mask & ETMv4_EVENT_MASK; /* @@ -2102,11 +2133,12 @@ static ssize_t vmid_idx_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 if (kstrtoul(buf, 16, &val)) return -EINVAL; - if (val >=3D drvdata->numvmidc) + if (val >=3D caps->numvmidc) return -EINVAL; =20 /* @@ -2147,6 +2179,7 @@ static ssize_t vmid_val_store(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 /* @@ -2160,7 +2193,7 @@ static ssize_t vmid_val_store(struct device *dev, * only implemented when vmid tracing is enabled, i.e. at least one * vmid comparator is implemented and at least 8 bit vmid size */ - if (!drvdata->vmid_size || !drvdata->numvmidc) + if (!caps->vmid_size || !caps->numvmidc) return -EINVAL; if (kstrtoul(buf, 16, &val)) return -EINVAL; @@ -2200,6 +2233,7 @@ static ssize_t vmid_masks_store(struct device *dev, u8 i, j, maskbyte; unsigned long val1, val2, mask; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; int nr_inputs; =20 @@ -2214,11 +2248,11 @@ static ssize_t vmid_masks_store(struct device *dev, * only implemented when vmid tracing is enabled, i.e. at least one * vmid comparator is implemented and at least 8 bit vmid size */ - if (!drvdata->vmid_size || !drvdata->numvmidc) + if (!caps->vmid_size || !caps->numvmidc) return -EINVAL; /* one mask if <=3D 4 comparators, two for up to 8 */ nr_inputs =3D sscanf(buf, "%lx %lx", &val1, &val2); - if ((drvdata->numvmidc > 4) && (nr_inputs !=3D 2)) + if ((caps->numvmidc > 4) && (nr_inputs !=3D 2)) return -EINVAL; =20 raw_spin_lock(&drvdata->spinlock); @@ -2227,7 +2261,7 @@ static ssize_t vmid_masks_store(struct device *dev, * each byte[0..3] controls mask value applied to vmid * comparator[0..3] */ - switch (drvdata->numvmidc) { + switch (caps->numvmidc) { case 0x1: /* COMP0, bits[7:0] */ config->vmid_mask0 =3D val1 & 0xFF; @@ -2275,7 +2309,7 @@ static ssize_t vmid_masks_store(struct device *dev, * of vmid comparator0 value (corresponding to byte 0) register. */ mask =3D config->vmid_mask0; - for (i =3D 0; i < drvdata->numvmidc; i++) { + for (i =3D 0; i < caps->numvmidc; i++) { /* mask value of corresponding vmid comparator */ maskbyte =3D mask & ETMv4_EVENT_MASK; /* diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index 89d81ce4e04e..8168676f2945 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -812,6 +812,95 @@ enum etm_impdef_type { ETM4_IMPDEF_FEATURE_MAX, }; =20 +/** + * struct etmv4_caps - specifics ETM capabilities + * @nr_pe: The number of processing entity available for tracing. + * @nr_pe_cmp: The number of processing entity comparator inputs that are + * available for tracing. + * @nr_addr_cmp:Number of pairs of address comparators available + * as found in ETMIDR4 0-3. + * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30. + * @nr_ext_inp: Number of external input. + * @numcidc: Number of contextID comparators. + * @numextinsel: Number of external input selector resources. + * @numvmidc: Number of VMID comparators. + * @nrseqstate: The number of sequencer states that are implemented. + * @nr_event: Indicates how many events the trace unit support. + * @nr_resource:The number of resource selection pairs available for traci= ng. + * @nr_ss_cmp: Number of single-shot comparator controls that are availabl= e. + * @trcid_size: Indicates the trace ID width. + * @ts_size: Global timestamp size field. + * @ctxid_size: Size of the context ID field to consider. + * @vmid_size: Size of the VM ID comparator to consider. + * @ccsize: Indicates the size of the cycle counter in bits. + * @ccitmin: minimum value that can be programmed in + * @s_ex_level: In secure state, indicates whether instruction tracing is + * supported for the corresponding Exception level. + * @ns_ex_level:In non-secure state, indicates whether instruction tracing= is + * supported for the corresponding Exception level. + * @q_support: Q element support characteristics. + * @os_lock_model: OSLock model. + * @instrp0: Tracing of load and store instructions + * as P0 elements is supported. + * @q_filt: Q element filtering support, if Q elements are supported. + * @trcbb: Indicates if the trace unit supports branch broadcast tracing. + * @trccond: If the trace unit supports conditional + * instruction tracing. + * @retstack: Indicates if the implementation supports a return stack. + * @trccci: Indicates if the trace unit supports cycle counting + * for instruction. + * @trc_error: Whether a trace unit can trace a system + * error exception. + * @syncpr: Indicates if an implementation has a fixed + * synchronization period. + * @stallctl: If functionality that prevents trace unit buffer overflows + * is available. + * @sysstall: Does the system support stall control of the PE? + * @nooverflow: Indicate if overflow prevention is supported. + * @atbtrig: If the implementation can support ATB triggers + * @lpoverride: If the implementation can support low-power state over. + * @skip_power_up: Indicates if an implementation can skip powering up + * the trace unit. + */ +struct etmv4_caps { + u8 nr_pe; + u8 nr_pe_cmp; + u8 nr_addr_cmp; + u8 nr_cntr; + u8 nr_ext_inp; + u8 numcidc; + u8 numextinsel; + u8 numvmidc; + u8 nrseqstate; + u8 nr_event; + u8 nr_resource; + u8 nr_ss_cmp; + u8 trcid_size; + u8 ts_size; + u8 ctxid_size; + u8 vmid_size; + u8 ccsize; + u16 ccitmin; + u8 s_ex_level; + u8 ns_ex_level; + u8 q_support; + u8 os_lock_model; + bool instrp0 : 1; + bool q_filt : 1; + bool trcbb : 1; + bool trccond : 1; + bool retstack : 1; + bool trccci : 1; + bool trc_error : 1; + bool syncpr : 1; + bool stallctl : 1; + bool sysstall : 1; + bool nooverflow : 1; + bool atbtrig : 1; + bool lpoverride : 1; + bool skip_power_up : 1; +}; + /** * struct etmv4_config - configuration information related to an ETMv4 * @mode: Controls various modes supported by this ETM. @@ -819,8 +908,8 @@ enum etm_impdef_type { * @cfg: Controls the tracing options. * @eventctrl0: Controls the tracing of arbitrary events. * @eventctrl1: Controls the behavior of the events that @event_ctrl0 sele= cts. - * @stallctl: If functionality that prevents trace unit buffer overflows - * is available. + * @stall_ctrl: Enables trace unit functionality that prevents trace + * unit buffer overflows. * @ts_ctrl: Controls the insertion of global timestamps in the * trace streams. * @syncfreq: Controls how often trace synchronization requests occur. @@ -971,61 +1060,17 @@ struct etmv4_save_state { * @mode: This tracer's mode, i.e sysFS, Perf or disabled. * @cpu: The cpu this component is affined to. * @arch: ETM architecture version. - * @nr_pe: The number of processing entity available for tracing. - * @nr_pe_cmp: The number of processing entity comparator inputs that are - * available for tracing. - * @nr_addr_cmp:Number of pairs of address comparators available - * as found in ETMIDR4 0-3. - * @nr_cntr: Number of counters as found in ETMIDR5 bit 28-30. - * @nr_ext_inp: Number of external input. - * @numcidc: Number of contextID comparators. - * @numvmidc: Number of VMID comparators. - * @nrseqstate: The number of sequencer states that are implemented. - * @nr_event: Indicates how many events the trace unit support. - * @nr_resource:The number of resource selection pairs available for traci= ng. - * @nr_ss_cmp: Number of single-shot comparator controls that are availabl= e. + * @caps: ETM capabilities. * @trcid: value of the current ID for this component. - * @trcid_size: Indicates the trace ID width. - * @ts_size: Global timestamp size field. - * @ctxid_size: Size of the context ID field to consider. - * @vmid_size: Size of the VM ID comparator to consider. - * @ccsize: Indicates the size of the cycle counter in bits. - * @ccitmin: minimum value that can be programmed in - * @s_ex_level: In secure state, indicates whether instruction tracing is - * supported for the corresponding Exception level. - * @ns_ex_level:In non-secure state, indicates whether instruction tracing= is - * supported for the corresponding Exception level. * @sticky_enable: true if ETM base configuration has been done. * @boot_enable:True if we should start tracing at boot time. * @os_unlock: True if access to management registers is allowed. - * @instrp0: Tracing of load and store instructions - * as P0 elements is supported. - * @q_filt: Q element filtering support, if Q elements are supported. - * @trcbb: Indicates if the trace unit supports branch broadcast tracing. - * @trccond: If the trace unit supports conditional - * instruction tracing. - * @retstack: Indicates if the implementation supports a return stack. - * @trccci: Indicates if the trace unit supports cycle counting - * for instruction. - * @q_support: Q element support characteristics. - * @trc_error: Whether a trace unit can trace a system - * error exception. - * @syncpr: Indicates if an implementation has a fixed - * synchronization period. - * @stall_ctrl: Enables trace unit functionality that prevents trace - * unit buffer overflows. - * @sysstall: Does the system support stall control of the PE? - * @nooverflow: Indicate if overflow prevention is supported. - * @atbtrig: If the implementation can support ATB triggers - * @lpoverride: If the implementation can support low-power state over. * @trfcr: If the CPU supports FEAT_TRF, value of the TRFCR_ELx that * allows tracing at all ELs. We don't want to compute this * at runtime, due to the additional setting of TRFCR_CX when * in EL2. Otherwise, 0. * @config: structure holding configuration parameters. * @save_state: State to be preserved across power loss - * @skip_power_up: Indicates if an implementation can skip powering up - * the trace unit. * @paused: Indicates if the trace unit is paused. * @arch_features: Bitmap of arch features of etmv4 devices. */ @@ -1037,46 +1082,11 @@ struct etmv4_drvdata { raw_spinlock_t spinlock; int cpu; u8 arch; - u8 nr_pe; - u8 nr_pe_cmp; - u8 nr_addr_cmp; - u8 nr_cntr; - u8 nr_ext_inp; - u8 numcidc; - u8 numextinsel; - u8 numvmidc; - u8 nrseqstate; - u8 nr_event; - u8 nr_resource; - u8 nr_ss_cmp; + struct etmv4_caps caps; u8 trcid; - u8 trcid_size; - u8 ts_size; - u8 ctxid_size; - u8 vmid_size; - u8 ccsize; - u16 ccitmin; - u8 s_ex_level; - u8 ns_ex_level; - u8 q_support; - u8 os_lock_model; bool sticky_enable : 1; bool boot_enable : 1; bool os_unlock : 1; - bool instrp0 : 1; - bool q_filt : 1; - bool trcbb : 1; - bool trccond : 1; - bool retstack : 1; - bool trccci : 1; - bool trc_error : 1; - bool syncpr : 1; - bool stallctl : 1; - bool sysstall : 1; - bool nooverflow : 1; - bool atbtrig : 1; - bool lpoverride : 1; - bool skip_power_up : 1; bool paused : 1; u64 trfcr; struct etmv4_config config; --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Jun 20 11:51:19 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DAE013EAC71 for ; Wed, 15 Apr 2026 16:55:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272143; cv=none; b=bcIqBhNGyFWwYuyqdHxzcr77ZDU3LwIMEWRUOxW7s0/gjq/qkF/g+z89QZ9LA/v2SM+S+Hdr0GwRb0727UaeAlaJfZNjdpo/5F1BvO7jdxg3Dd9ajoi77RV0CyYtp93GYjqokwfXXEoY75tpWLbKPLzhukwPVuktJRZpTB52tlI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272143; c=relaxed/simple; bh=UyAplWgdO16yZfwmWZ/U9RvQUdrrgrP41E5pZvT4j7w=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=NzDmO7aFMDjpu47C93fIBOCeaf7QRNPXmgeTZhGAxrfA4qb0Ilxm3kDKsSvyzNbD2nPrzwF4j2Rrm0nDn8jTNz5MPfzOm8JgX6LLgWJQLfdwMy5h5BI6GUmbudIDXe70VoGkQVwB9GtJ0h65ITZFDZBeWwyidX3QPnR+PGzWIfw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=Bg8j+H0C; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="Bg8j+H0C" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8DEB132FB; Wed, 15 Apr 2026 09:55:35 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5EE5D3F7D8; Wed, 15 Apr 2026 09:55:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776272141; bh=UyAplWgdO16yZfwmWZ/U9RvQUdrrgrP41E5pZvT4j7w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Bg8j+H0CsOAeqUVOKvoP6uDmAo2b0PZ7VLOg8+8HDRTRBZvOHuF29WS5+FoBca26M /EVKdlrcb+NRVog4RkPm6K5oPb5Ln0RC1zRlMtd+E2SwsvUG8wDMUPnz6qNgoLQUKy ui5khZhevWxO7OydpXoRMCtLtdCMPrGJFhCe3NW4= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v5 04/12] coresight: etm4x: exclude ss_status from drvdata->config Date: Wed, 15 Apr 2026 17:55:20 +0100 Message-Id: <20260415165528.3369607-5-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260415165528.3369607-1-yeoreum.yun@arm.com> References: <20260415165528.3369607-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The purpose of TRCSSCSRn register is to show status of the corresponding Single-shot Comparator Control and input supports. That means writable field's purpose for reset or restore from idle status not for configuration. Therefore, exclude ss_status from drvdata->config, move it to etm4x_caps and rename it to ss_smp. This includes remove TRCSSCRn from configurable item and remove saving in etm4_disable_hw(). Signed-off-by: Yeoreum Yun --- .../hwtracing/coresight/coresight-etm4x-cfg.c | 1 - .../coresight/coresight-etm4x-core.c | 19 ++++++------------- .../coresight/coresight-etm4x-sysfs.c | 7 ++----- drivers/hwtracing/coresight/coresight-etm4x.h | 7 ++++++- 4 files changed, 14 insertions(+), 20 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hw= tracing/coresight/coresight-etm4x-cfg.c index c302072b293a..d14d7c8a23e5 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c @@ -86,7 +86,6 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *= drvdata, off_mask =3D (offset & GENMASK(11, 5)); do { CHECKREGIDX(TRCSSCCRn(0), ss_ctrl, idx, off_mask); - CHECKREGIDX(TRCSSCSRn(0), ss_status, idx, off_mask); CHECKREGIDX(TRCSSPCICRn(0), ss_pe_cmp, idx, off_mask); } while (0); } else if ((offset >=3D TRCCIDCVRn(0)) && (offset <=3D TRCVMIDCVRn(7))) { diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index b2b092a76eb5..f55338a4989d 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -91,7 +91,7 @@ static bool etm4x_sspcicrn_present(struct etmv4_drvdata *= drvdata, int n) const struct etmv4_caps *caps =3D &drvdata->caps; =20 return (n < caps->nr_ss_cmp) && caps->nr_pe_cmp && - (drvdata->config.ss_status[n] & TRCSSCSRn_PC); + (caps->ss_cmp[n] & TRCSSCSRn_PC); } =20 u64 etm4x_sysreg_read(u32 offset, bool _relaxed, bool _64bit) @@ -573,11 +573,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdat= a) etm4x_relaxed_write32(csa, config->res_ctrl[i], TRCRSCTLRn(i)); =20 for (i =3D 0; i < caps->nr_ss_cmp; i++) { - /* always clear status bit on restart if using single-shot */ - if (config->ss_ctrl[i] || config->ss_pe_cmp[i]) - config->ss_status[i] &=3D ~TRCSSCSRn_STATUS; etm4x_relaxed_write32(csa, config->ss_ctrl[i], TRCSSCCRn(i)); - etm4x_relaxed_write32(csa, config->ss_status[i], TRCSSCSRn(i)); + /* always clear status and pending bits on restart if using single-shot = */ + etm4x_relaxed_write32(csa, 0x0, TRCSSCSRn(i)); if (etm4x_sspcicrn_present(drvdata, i)) etm4x_relaxed_write32(csa, config->ss_pe_cmp[i], TRCSSPCICRn(i)); } @@ -1055,12 +1053,6 @@ static void etm4_disable_hw(struct etmv4_drvdata *dr= vdata) =20 etm4_disable_trace_unit(drvdata); =20 - /* read the status of the single shot comparators */ - for (i =3D 0; i < caps->nr_ss_cmp; i++) { - config->ss_status[i] =3D - etm4x_relaxed_read32(csa, TRCSSCSRn(i)); - } - /* read back the current counter values */ for (i =3D 0; i < caps->nr_cntr; i++) { config->cntr_val[i] =3D @@ -1503,8 +1495,9 @@ static void etm4_init_arch_data(void *info) */ caps->nr_ss_cmp =3D FIELD_GET(TRCIDR4_NUMSSCC_MASK, etmidr4); for (i =3D 0; i < caps->nr_ss_cmp; i++) { - drvdata->config.ss_status[i] =3D - etm4x_relaxed_read32(csa, TRCSSCSRn(i)); + caps->ss_cmp[i] =3D etm4x_relaxed_read32(csa, TRCSSCSRn(i)); + caps->ss_cmp[i] &=3D (TRCSSCSRn_PC | TRCSSCSRn_DV | + TRCSSCSRn_DA | TRCSSCSRn_INST); } /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */ caps->numcidc =3D FIELD_GET(TRCIDR4_NUMCIDC_MASK, etmidr4); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm4x-sysfs.c index 8bd28e71d4c9..5e26c2ec8f7b 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1829,8 +1829,6 @@ static ssize_t sshot_ctrl_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); idx =3D config->ss_idx; config->ss_ctrl[idx] =3D FIELD_PREP(TRCSSCCRn_SAC_ARC_RST_MASK, val); - /* must clear bit 31 in related status register on programming */ - config->ss_status[idx] &=3D ~TRCSSCSRn_STATUS; raw_spin_unlock(&drvdata->spinlock); return size; } @@ -1841,10 +1839,11 @@ static ssize_t sshot_status_show(struct device *dev, { unsigned long val; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etmv4_caps *caps =3D &drvdata->caps; struct etmv4_config *config =3D &drvdata->config; =20 raw_spin_lock(&drvdata->spinlock); - val =3D config->ss_status[config->ss_idx]; + val =3D caps->ss_cmp[config->ss_idx]; raw_spin_unlock(&drvdata->spinlock); return scnprintf(buf, PAGE_SIZE, "%#lx\n", val); } @@ -1879,8 +1878,6 @@ static ssize_t sshot_pe_ctrl_store(struct device *dev, raw_spin_lock(&drvdata->spinlock); idx =3D config->ss_idx; config->ss_pe_cmp[idx] =3D FIELD_PREP(TRCSSPCICRn_PC_MASK, val); - /* must clear bit 31 in related status register on programming */ - config->ss_status[idx] &=3D ~TRCSSCSRn_STATUS; raw_spin_unlock(&drvdata->spinlock); return size; } diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index 8168676f2945..db56c4414873 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -213,6 +213,7 @@ #define TRCACATRn_EXLEVEL_MASK GENMASK(14, 8) =20 #define TRCSSCSRn_STATUS BIT(31) +#define TRCSSCSRn_PENDING BIT(30) #define TRCSSCCRn_SAC_ARC_RST_MASK GENMASK(24, 0) =20 #define TRCSSPCICRn_PC_MASK GENMASK(7, 0) @@ -729,6 +730,9 @@ static inline u32 etm4_res_sel_pair(u8 res_sel_idx) #define ETM_DEFAULT_ADDR_COMP 0 =20 #define TRCSSCSRn_PC BIT(3) +#define TRCSSCSRn_DV BIT(2) +#define TRCSSCSRn_DA BIT(1) +#define TRCSSCSRn_INST BIT(0) =20 /* PowerDown Control Register bits */ #define TRCPDCR_PU BIT(3) @@ -861,6 +865,7 @@ enum etm_impdef_type { * @lpoverride: If the implementation can support low-power state over. * @skip_power_up: Indicates if an implementation can skip powering up * the trace unit. + * @ss_cmp: Indicates supported single-shot comparators. */ struct etmv4_caps { u8 nr_pe; @@ -899,6 +904,7 @@ struct etmv4_caps { bool atbtrig : 1; bool lpoverride : 1; bool skip_power_up : 1; + u32 ss_cmp[ETM_MAX_SS_CMP]; }; =20 /** @@ -977,7 +983,6 @@ struct etmv4_config { u32 res_ctrl[ETM_MAX_RES_SEL]; /* TRCRSCTLRn */ u8 ss_idx; u32 ss_ctrl[ETM_MAX_SS_CMP]; - u32 ss_status[ETM_MAX_SS_CMP]; u32 ss_pe_cmp[ETM_MAX_SS_CMP]; u8 addr_idx; u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP]; --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Jun 20 11:51:19 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F24B73E63A2 for ; Wed, 15 Apr 2026 16:55:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272145; cv=none; b=WrNfEIHI4Brr2yXPx/jMlSkhmuratVjU37SzjFkwktD5rl6uYoOjHzUblVolnrk1dnu2aML5JM1UOHpAefdbz2Pm24sqLRmgQh6TiOMk21ecnb80yJy69S2SZ4EUaPksdq9MKUn6M76hiBqaUP1v3lk110895fMMyoBsxPHTJEw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272145; c=relaxed/simple; bh=NHwM0SSeOIcKoFO7iDJI3DKim2DPDP/5ZwxvxWPLe1o=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=MXZLv8G6qA5LG3Qo/lbMfghbf+LT+I6jhf26muzSEEPNWKem6FWOg4EvYiSVgaTkyJMdnWWL4cgdIwEd+NhgDrNQZ/TEJ22dNJJCkZVkTXgGAQ0a4h7QaM92Ku0L4DrwIzdgyl1TYuqWMWwhfMM1+49CGSFc+fBad5tFiRoIeqM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=TmAxFcdB; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="TmAxFcdB" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C5F7432D1; Wed, 15 Apr 2026 09:55:37 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8F4D63F7D8; Wed, 15 Apr 2026 09:55:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776272143; bh=NHwM0SSeOIcKoFO7iDJI3DKim2DPDP/5ZwxvxWPLe1o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TmAxFcdB+P3a4uekx96c/ifwiqQWVQI2M0Zg3M0ConrrRPC9l/WzdpgLcoEqlR8IK rceVji5Vf4loaVM5Q1h4MtTRo5KfFvTEU5I59GAEA/izQzfot31vAri8tTEajHCWd1 ZNSOZZoY/P2g2YOfbQmlH6LIvbhNxTeryTx/qpwU= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v5 05/12] coresight: etm4x: remove redundant fields in etmv4_save_state Date: Wed, 15 Apr 2026 17:55:21 +0100 Message-Id: <20260415165528.3369607-6-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260415165528.3369607-1-yeoreum.yun@arm.com> References: <20260415165528.3369607-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some of fields are redundant in etmv4_save_state and never used: ss_status =3D> trcsscsr seq_state =3D> trcseqstr cntr_val =3D> trccntvr vinst_ctrl =3D> trcvictlr Signed-off-by: Yeoreum Yun Reviewed-by: Leo Yan --- drivers/hwtracing/coresight/coresight-etm4x.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index db56c4414873..cbd8890d166a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1047,11 +1047,6 @@ struct etmv4_save_state { =20 u32 trcclaimset; =20 - u32 cntr_val[ETMv4_MAX_CNTR]; - u32 seq_state; - u32 vinst_ctrl; - u32 ss_status[ETM_MAX_SS_CMP]; - u32 trcpdcr; }; =20 --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Jun 20 11:51:19 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 471573EBF1A for ; Wed, 15 Apr 2026 16:55:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272147; cv=none; b=mg5RVtUlpLA7ndG8/v2U+ZOEbX9POXssplV7hTxZCbNpliETR/vDPZY0Vw01gz6k7am76ZEfuwJbBTjvY/RpDxKlx3XhBHDMNJcd86ejOuOnu1oy2dUOpmktQFXJDu/VOvt53cPareHySsYhQZIsDTMsoOvu2lyEgx1AAj+2sq4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272147; c=relaxed/simple; bh=Ewh6cA8o+NqF7LLawvfJJyMTyhJYUObSRPM1ExAFkfc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Au1Hk7Qd3cIGpit2nanA3ojBNQg/0k0zOSnkW2XWOX/KPtErbns+RcMDK9WsCRgshqMgjF60GpIjGHU05vsfFtDOnlUBlAzMioV3jixQw21rXKFY59MxtQc4tNuvYy7rBGNDfwcMnJS8nvLfDixONBxMJ3Jgut0V/Of8XwC+HiY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=AAgTVC49; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="AAgTVC49" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0A77F32FB; Wed, 15 Apr 2026 09:55:40 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id C81E13F7D8; Wed, 15 Apr 2026 09:55:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776272145; bh=Ewh6cA8o+NqF7LLawvfJJyMTyhJYUObSRPM1ExAFkfc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AAgTVC49TckOCB4CwFX2pzaCQZyoa6CWcVoQolgpsZ2AgEU6k2MPmEZ5Z60lQ1cTY nLIsV9xbVG3Qj8Qg5FhdKhZ1mNaXrQb96GvqIsY3htxr5WXWEm/B3LngAs+44J21To 7Yd/tAG5r6cH4AsniXPouaATmEORZAtk7/0FDQ6U= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v5 06/12] coresight: etm4x: fix leaked trace id Date: Wed, 15 Apr 2026 17:55:22 +0100 Message-Id: <20260415165528.3369607-7-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260415165528.3369607-1-yeoreum.yun@arm.com> References: <20260415165528.3369607-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If etm4_enable_sysfs() fails in cscfg_csdev_enable_active_config(), the trace ID may be leaked because it is not released. To address this, call etm4_release_trace_id() when etm4_enable_sysfs() fails in cscfg_csdev_enable_active_config(). Reviewed-by: Jie Gan Signed-off-by: Yeoreum Yun Reviewed-by: Leo Yan --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index f55338a4989d..b199aebbdb60 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -920,8 +920,10 @@ static int etm4_enable_sysfs(struct coresight_device *= csdev, struct coresight_pa cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset); if (cfg_hash) { ret =3D cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); - if (ret) + if (ret) { + etm4_release_trace_id(drvdata); return ret; + } } =20 raw_spin_lock(&drvdata->spinlock); --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Jun 20 11:51:19 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3B64A3E63A2 for ; Wed, 15 Apr 2026 16:55:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272149; cv=none; b=Fz/KevzGKfDDcSOgXK1vkLIB1AF5kIxhRuTFqyqwROL95TuPHjuVkV86wEgL22ENtJgIAZqSXA+5lJYaXBQQFp+beoGIiq1nV81cmqSiqU47qRDnefGFE6aSxMdr0Ntc920ErmQ1BPXNIayeK595eTujKwJUpGCHi2T6knxFjMA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272149; c=relaxed/simple; bh=6u4jrZlea0UhDSy2tvdgz3PanKx80/KItEaTdYG6gKg=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DbMa9FcT+JII9+49BXEG2fgN5Y7rH0PdlN4dA5NYrgEvrdzbgRPKbwuDLNlGhDzuXfSJGecNtHKek4AKR0X1l+SVMh81Md00XeEsptUv+wPI27dys0G9i4ELbUTg6QM2GVMGVLwr3lwrH5lXVO/TlkujXcdpwMomrc9YiWa5VN0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=XO87QKbj; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="XO87QKbj" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3A0B732D1; Wed, 15 Apr 2026 09:55:42 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0D3E23F7D8; Wed, 15 Apr 2026 09:55:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776272147; bh=6u4jrZlea0UhDSy2tvdgz3PanKx80/KItEaTdYG6gKg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=XO87QKbjDQuTeVuCBfuJ6puvw9MZf26L2Lf9/n7o378sZ6fPrxZYJZkAz8yRt4aba RzRgkcAsY4Tn42044QMTQ31ODZ80dsCEV2RkB0qBDQGN0ZTCGRb+hrsH/U+c59BZ44 HtoFEgmYSKI+nn5DIX7dNlStTgvJtCzm7sxxzwE8= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v5 07/12] coresight: etm4x: fix inconsistencies with sysfs configuration Date: Wed, 15 Apr 2026 17:55:23 +0100 Message-Id: <20260415165528.3369607-8-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260415165528.3369607-1-yeoreum.yun@arm.com> References: <20260415165528.3369607-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current ETM4x configuration via sysfs can lead to several inconsistencies: - If the configuration is modified via sysfs while a perf session is active, the running configuration may differ before a sched-out and after a subsequent sched-in. - If a perf session and a sysfs session enable tracing concurrently, the configuration from configfs may become corrupted. - There is a risk of corrupting drvdata->config if a perf session enables tracing while cscfg_csdev_disable_active_config() is being handled in etm4_disable_sysfs(). To resolve these issues, separate the configuration into: - active_config: the configuration applied to the current session - config: the configuration set via sysfs Additionally: - Apply the configuration from configfs after taking the appropriate mode. - Since active_config and related fields are accessed only by the local C= PU in etm4_enable/disable_sysfs_smp_call() (similar to perf enable/disable= ), remove the lock/unlock from the sysfs enable/disable path and startup/dying_cpu except when to access config fields. Signed-off-by: Yeoreum Yun --- .../hwtracing/coresight/coresight-etm4x-cfg.c | 2 +- .../coresight/coresight-etm4x-core.c | 107 ++++++++++-------- drivers/hwtracing/coresight/coresight-etm4x.h | 2 + 3 files changed, 63 insertions(+), 48 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c b/drivers/hw= tracing/coresight/coresight-etm4x-cfg.c index d14d7c8a23e5..0553771d04e7 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-cfg.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-cfg.c @@ -47,7 +47,7 @@ static int etm4_cfg_map_reg_offset(struct etmv4_drvdata *= drvdata, struct cscfg_regval_csdev *reg_csdev, u32 offset) { int err =3D -EINVAL, idx; - struct etmv4_config *drvcfg =3D &drvdata->config; + struct etmv4_config *drvcfg =3D &drvdata->active_config; u32 off_mask; =20 if (((offset >=3D TRCEVENTCTL0R) && (offset <=3D TRCVIPCSSCTLR)) || diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index b199aebbdb60..15aaf4a898e1 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -245,6 +245,10 @@ void etm4_release_trace_id(struct etmv4_drvdata *drvda= ta) =20 struct etm4_enable_arg { struct etmv4_drvdata *drvdata; + unsigned long cfg_hash; + int preset; + u8 trace_id; + struct etmv4_config config; int rc; }; =20 @@ -270,10 +274,11 @@ static void etm4x_prohibit_trace(struct etmv4_drvdata= *drvdata) static u64 etm4x_get_kern_user_filter(struct etmv4_drvdata *drvdata) { u64 trfcr =3D drvdata->trfcr; + struct etmv4_config *config =3D &drvdata->active_config; =20 - if (drvdata->config.mode & ETM_MODE_EXCL_KERN) + if (config->mode & ETM_MODE_EXCL_KERN) trfcr &=3D ~TRFCR_EL1_ExTRE; - if (drvdata->config.mode & ETM_MODE_EXCL_USER) + if (config->mode & ETM_MODE_EXCL_USER) trfcr &=3D ~TRFCR_EL1_E0TRE; =20 return trfcr; @@ -281,7 +286,7 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_drvd= ata *drvdata) =20 /* * etm4x_allow_trace - Allow CPU tracing in the respective ELs, - * as configured by the drvdata->config.mode for the current + * as configured by the drvdata->active_config.mode for the current * session. Even though we have TRCVICTLR bits to filter the * trace in the ELs, it doesn't prevent the ETM from generating * a packet (e.g, TraceInfo) that might contain the addresses from @@ -292,12 +297,13 @@ static u64 etm4x_get_kern_user_filter(struct etmv4_dr= vdata *drvdata) static void etm4x_allow_trace(struct etmv4_drvdata *drvdata) { u64 trfcr, guest_trfcr; + struct etmv4_config *config =3D &drvdata->active_config; =20 /* If the CPU doesn't support FEAT_TRF, nothing to do */ if (!drvdata->trfcr) return; =20 - if (drvdata->config.mode & ETM_MODE_EXCL_HOST) + if (config->mode & ETM_MODE_EXCL_HOST) trfcr =3D drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE); else trfcr =3D etm4x_get_kern_user_filter(drvdata); @@ -305,7 +311,7 @@ static void etm4x_allow_trace(struct etmv4_drvdata *drv= data) write_trfcr(trfcr); =20 /* Set filters for guests and pass to KVM */ - if (drvdata->config.mode & ETM_MODE_EXCL_GUEST) + if (config->mode & ETM_MODE_EXCL_GUEST) guest_trfcr =3D drvdata->trfcr & ~(TRFCR_EL1_ExTRE | TRFCR_EL1_E0TRE); else guest_trfcr =3D etm4x_get_kern_user_filter(drvdata); @@ -499,7 +505,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) { int i, rc; const struct etmv4_caps *caps =3D &drvdata->caps; - struct etmv4_config *config =3D &drvdata->config; + struct etmv4_config *config =3D &drvdata->active_config; struct coresight_device *csdev =3D drvdata->csdev; struct device *etm_dev =3D &csdev->dev; struct csdev_access *csa =3D &csdev->access; @@ -618,23 +624,45 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvda= ta) static void etm4_enable_sysfs_smp_call(void *info) { struct etm4_enable_arg *arg =3D info; + struct etmv4_drvdata *drvdata; struct coresight_device *csdev; =20 if (WARN_ON(!arg)) return; =20 - csdev =3D arg->drvdata->csdev; + drvdata =3D arg->drvdata; + csdev =3D drvdata->csdev; if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) { /* Someone is already using the tracer */ arg->rc =3D -EBUSY; return; } =20 - arg->rc =3D etm4_enable_hw(arg->drvdata); + drvdata->active_config =3D arg->config; =20 - /* The tracer didn't start */ + if (arg->cfg_hash) { + arg->rc =3D cscfg_csdev_enable_active_config(csdev, + arg->cfg_hash, + arg->preset); + if (arg->rc) + goto err; + } + + drvdata->trcid =3D arg->trace_id; + + /* Tracer will never be paused in sysfs mode */ + drvdata->paused =3D false; + + arg->rc =3D etm4_enable_hw(drvdata); if (arg->rc) - coresight_set_mode(csdev, CS_MODE_DISABLED); + goto err; + + drvdata->sticky_enable =3D true; + + return; +err: + /* The tracer didn't start */ + coresight_set_mode(csdev, CS_MODE_DISABLED); } =20 /* @@ -672,7 +700,7 @@ static int etm4_config_timestamp_event(struct etmv4_drv= data *drvdata, int ctridx; int rselector; const struct etmv4_caps *caps =3D &drvdata->caps; - struct etmv4_config *config =3D &drvdata->config; + struct etmv4_config *config =3D &drvdata->active_config; =20 /* No point in trying if we don't have at least one counter */ if (!caps->nr_cntr) @@ -756,7 +784,7 @@ static int etm4_parse_event_config(struct coresight_dev= ice *csdev, int ret =3D 0; struct etmv4_drvdata *drvdata =3D dev_get_drvdata(csdev->dev.parent); const struct etmv4_caps *caps =3D &drvdata->caps; - struct etmv4_config *config =3D &drvdata->config; + struct etmv4_config *config =3D &drvdata->active_config; struct perf_event_attr max_timestamp =3D { .ATTR_CFG_FLD_timestamp_CFG =3D U64_MAX, }; @@ -918,40 +946,29 @@ static int etm4_enable_sysfs(struct coresight_device = *csdev, struct coresight_pa =20 /* enable any config activated by configfs */ cscfg_config_sysfs_get_active_cfg(&cfg_hash, &preset); - if (cfg_hash) { - ret =3D cscfg_csdev_enable_active_config(csdev, cfg_hash, preset); - if (ret) { - etm4_release_trace_id(drvdata); - return ret; - } - } - - raw_spin_lock(&drvdata->spinlock); - - drvdata->trcid =3D path->trace_id; - - /* Tracer will never be paused in sysfs mode */ - drvdata->paused =3D false; =20 /* * Executing etm4_enable_hw on the cpu whose ETM is being enabled * ensures that register writes occur when cpu is powered. */ arg.drvdata =3D drvdata; + arg.cfg_hash =3D cfg_hash; + arg.preset =3D preset; + arg.trace_id =3D path->trace_id; + + raw_spin_lock(&drvdata->spinlock); + arg.config =3D drvdata->config; + raw_spin_unlock(&drvdata->spinlock); + ret =3D smp_call_function_single(drvdata->cpu, etm4_enable_sysfs_smp_call, &arg, 1); if (!ret) ret =3D arg.rc; if (!ret) - drvdata->sticky_enable =3D true; - - if (ret) + dev_dbg(&csdev->dev, "ETM tracing enabled\n"); + else etm4_release_trace_id(drvdata); =20 - raw_spin_unlock(&drvdata->spinlock); - - if (!ret) - dev_dbg(&csdev->dev, "ETM tracing enabled\n"); return ret; } =20 @@ -1038,7 +1055,7 @@ static void etm4_disable_hw(struct etmv4_drvdata *drv= data) { u32 control; const struct etmv4_caps *caps =3D &drvdata->caps; - struct etmv4_config *config =3D &drvdata->config; + struct etmv4_config *config =3D &drvdata->active_config; struct coresight_device *csdev =3D drvdata->csdev; struct csdev_access *csa =3D &csdev->access; int i; @@ -1074,6 +1091,8 @@ static void etm4_disable_sysfs_smp_call(void *info) =20 etm4_disable_hw(drvdata); =20 + cscfg_csdev_disable_active_config(drvdata->csdev); + coresight_set_mode(drvdata->csdev, CS_MODE_DISABLED); } =20 @@ -1124,7 +1143,6 @@ static void etm4_disable_sysfs(struct coresight_devic= e *csdev) * DYING hotplug callback is serviced by the ETM driver. */ cpus_read_lock(); - raw_spin_lock(&drvdata->spinlock); =20 /* * Executing etm4_disable_hw on the cpu whose ETM is being disabled @@ -1133,10 +1151,6 @@ static void etm4_disable_sysfs(struct coresight_devi= ce *csdev) smp_call_function_single(drvdata->cpu, etm4_disable_sysfs_smp_call, drvdata, 1); =20 - raw_spin_unlock(&drvdata->spinlock); - - cscfg_csdev_disable_active_config(csdev); - cpus_read_unlock(); =20 /* @@ -1379,6 +1393,7 @@ static void etm4_init_arch_data(void *info) struct etm4_init_arg *init_arg =3D info; struct etmv4_drvdata *drvdata; struct etmv4_caps *caps; + struct etmv4_config *config; struct csdev_access *csa; struct device *dev =3D init_arg->dev; int i; @@ -1386,6 +1401,7 @@ static void etm4_init_arch_data(void *info) drvdata =3D dev_get_drvdata(init_arg->dev); caps =3D &drvdata->caps; csa =3D init_arg->csa; + config =3D &drvdata->active_config; =20 /* * If we are unable to detect the access mechanism, @@ -1446,7 +1462,7 @@ static void etm4_init_arch_data(void *info) =20 /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ caps->s_ex_level =3D FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3); - drvdata->config.s_ex_level =3D caps->s_ex_level; + config->s_ex_level =3D caps->s_ex_level; /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */ caps->ns_ex_level =3D FIELD_GET(TRCIDR3_EXLEVEL_NS_MASK, etmidr3); /* @@ -1692,7 +1708,7 @@ static void etm4_set_default(struct etmv4_config *con= fig) static int etm4_get_next_comparator(struct etmv4_drvdata *drvdata, u32 typ= e) { int nr_comparator, index =3D 0; - struct etmv4_config *config =3D &drvdata->config; + struct etmv4_config *config =3D &drvdata->active_config; =20 /* * nr_addr_cmp holds the number of comparator _pair_, so time 2 @@ -1733,7 +1749,7 @@ static int etm4_set_event_filters(struct etmv4_drvdat= a *drvdata, { int i, comparator, ret =3D 0; u64 address; - struct etmv4_config *config =3D &drvdata->config; + struct etmv4_config *config =3D &drvdata->active_config; struct etm_filters *filters =3D event->hw.addr_filters; =20 if (!filters) @@ -1851,13 +1867,11 @@ static int etm4_starting_cpu(unsigned int cpu) if (!etmdrvdata[cpu]) return 0; =20 - raw_spin_lock(&etmdrvdata[cpu]->spinlock); if (!etmdrvdata[cpu]->os_unlock) etm4_os_unlock(etmdrvdata[cpu]); =20 if (coresight_get_mode(etmdrvdata[cpu]->csdev)) etm4_enable_hw(etmdrvdata[cpu]); - raw_spin_unlock(&etmdrvdata[cpu]->spinlock); return 0; } =20 @@ -1866,10 +1880,8 @@ static int etm4_dying_cpu(unsigned int cpu) if (!etmdrvdata[cpu]) return 0; =20 - raw_spin_lock(&etmdrvdata[cpu]->spinlock); if (coresight_get_mode(etmdrvdata[cpu]->csdev)) etm4_disable_hw(etmdrvdata[cpu]); - raw_spin_unlock(&etmdrvdata[cpu]->spinlock); return 0; } =20 @@ -2255,7 +2267,8 @@ static int etm4_add_coresight_dev(struct etm4_init_ar= g *init_arg) if (!desc.name) return -ENOMEM; =20 - etm4_set_default(&drvdata->config); + etm4_set_default(&drvdata->active_config); + drvdata->config =3D drvdata->active_config; =20 pdata =3D coresight_get_platform_data(dev); if (IS_ERR(pdata)) diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtrac= ing/coresight/coresight-etm4x.h index cbd8890d166a..9b50aaa368cf 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x.h +++ b/drivers/hwtracing/coresight/coresight-etm4x.h @@ -1069,6 +1069,7 @@ struct etmv4_save_state { * allows tracing at all ELs. We don't want to compute this * at runtime, due to the additional setting of TRFCR_CX when * in EL2. Otherwise, 0. + * @active_config: structure holding current applied configuration paramet= ers. * @config: structure holding configuration parameters. * @save_state: State to be preserved across power loss * @paused: Indicates if the trace unit is paused. @@ -1089,6 +1090,7 @@ struct etmv4_drvdata { bool os_unlock : 1; bool paused : 1; u64 trfcr; + struct etmv4_config active_config; struct etmv4_config config; struct etmv4_save_state *save_state; DECLARE_BITMAP(arch_features, ETM4_IMPDEF_FEATURE_MAX); --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Jun 20 11:51:19 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A85CE3ECBDC for ; Wed, 15 Apr 2026 16:55:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272152; cv=none; b=ScqvaDPdjoSLVTo2YeXdOLLzThjSTnwj/j4lX4e3EEb+QB5xA1c4/I46KultvV0fBzpplyRUl/t4RRIkfbMCELLxD3IFa3IEFAzD8EQC7Cii2OVXMNevyNwnfkp8ZulVDiNEfCrs14iyXNySP7508SOmc2+UDZsbxBsHlgztUJo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272152; c=relaxed/simple; bh=jJ7Gqb7ORflx/3s434eoHtGC4lP0qNeMEXUWzGOGbhM=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=HNz5CBRDS3Gx72zAM0g55OCAV1ByQpb3FXule5DF8jYGhHwNpnQe0wP0HzLN5DuEBbQyN0J1gpUYcPTfWfo7PEL7ZkJj/LmJZ6rAkzw92v+yLSr5vbn7O93lw7NxcCAmQzMGBdH7uqVrRwPZswwvhlYpj5mEE4iDMSAEfmngpao= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=PZxzD5lH; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="PZxzD5lH" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7259D32FB; Wed, 15 Apr 2026 09:55:44 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 3D7BC3F7D8; Wed, 15 Apr 2026 09:55:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776272150; bh=jJ7Gqb7ORflx/3s434eoHtGC4lP0qNeMEXUWzGOGbhM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PZxzD5lHR3fI7V1E5l2IikUK3PmlNAPlbqlsffwjqG5WaYRMpLwTGWQaVkTgiZxL2 C3orhkeS2ybYM2pZlXZXj+15gfvQEQ9h9eGHjbK4J9/ZUkYME3DfxYlsco5RbUVK/Y yXgBcZ/JQybFrYRYc4wTreidmhBNoYSpDPv16MZ0= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v5 08/12] coresight: etm4x: remove redundant call etm4_enable_hw() with hotplug Date: Wed, 15 Apr 2026 17:55:24 +0100 Message-Id: <20260415165528.3369607-9-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260415165528.3369607-1-yeoreum.yun@arm.com> References: <20260415165528.3369607-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cpu_online_mask is set at the CPUHP_BRINGUP_CPU step. In other words, if etm4_enable_sysfs() is called between CPUHP_BRINGUP_CPU and CPUHP_AP_ARM_CORESIGHT_STARTING, etm4_enable_hw() may be invoked in etm4_enable_sysfs_smp_call() and then executed again in etm4_starting_cpu(). To remove this redundant call, take the hotplug lock before executing etm4_enable_sysfs_smp_call(). Reviewed-by: Jie Gan Signed-off-by: Yeoreum Yun --- drivers/hwtracing/coresight/coresight-etm4x-core.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 15aaf4a898e1..2ce6b08f7f54 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -960,8 +960,20 @@ static int etm4_enable_sysfs(struct coresight_device *= csdev, struct coresight_pa arg.config =3D drvdata->config; raw_spin_unlock(&drvdata->spinlock); =20 + /* + * Take the hotplug lock to prevent redundant calls to etm4_enable_hw(). + * + * The cpu_online_mask is set at the CPUHP_BRINGUP_CPU step. + * In other words, if etm4_enable_sysfs() is called between + * CPUHP_BRINGUP_CPU and CPUHP_AP_ARM_CORESIGHT_STARTING, + * etm4_enable_hw() may be invoked in etm4_enable_sysfs_smp_call() + * and then executed again in etm4_starting_cpu(). + */ + cpus_read_lock(); ret =3D smp_call_function_single(drvdata->cpu, etm4_enable_sysfs_smp_call, &arg, 1); + cpus_read_unlock(); + if (!ret) ret =3D arg.rc; if (!ret) --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Jun 20 11:51:19 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D03833ECBFF for ; Wed, 15 Apr 2026 16:55:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272154; cv=none; b=ccXXTsohGq8x5O6Vo9tVxEl3HAKRkTSaf9VU3zgjoPGBcOoozoKpNOjro5Ic5IGDudUA/FA1Pb0+qdoZ67XX/rPJTwXFgEJZm1Mrfy0VUns7aO7+yMnXt8zSC66mWFhfqt6ne3ZDU39RSSF1X7kFMnbH8L0vr68ITcBlkIQ/bcc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272154; c=relaxed/simple; bh=SSyrjZ1m4gqnvakTvMsUm0fyvjSU1GFfyo1w16A1OtQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qsb5KpnSMsOAuKXMWt5zrq2hGBYUTocWIwd1xy2beNA5BaPlL80/nOHmuV05f9iNWr9H4Eqi9PFkUv6ClS98SyS8ETrK1T45CDH3m+3yHxI8yqhBkQMEGjIf2CzazXP8xx306KP9q4pD/8yhK+zm8JN2Yk27E0IJ4C59izOKadw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=ZYUnAfOs; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="ZYUnAfOs" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A4AE132D1; Wed, 15 Apr 2026 09:55:46 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 723B33F7D8; Wed, 15 Apr 2026 09:55:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776272152; bh=SSyrjZ1m4gqnvakTvMsUm0fyvjSU1GFfyo1w16A1OtQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ZYUnAfOscBd5atMLfD4hXsuAS0HxJS5aDf6drbjO5UpgCw6bymkpzDHa0Gh9/9I+3 0iDzep6Z5XM8ECstyrKUMmpGcAIS8Ug1s5wa8T+2/IpPO9p0NGXqE3UMXxaz/LainW QyjL3USa7jDVWal2GXmS8aW6OlTfaeHQl9KBGwDY= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v5 09/12] coresight: etm3x: change drvdata->spinlock type to raw_spin_lock_t Date: Wed, 15 Apr 2026 17:55:25 +0100 Message-Id: <20260415165528.3369607-10-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260415165528.3369607-1-yeoreum.yun@arm.com> References: <20260415165528.3369607-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" etm_starting_cpu()/etm_dying_cpu() are called in not sleepable context. This poses an issue in PREEMPT_RT kernel where spinlock_t is sleepable. To address this, change etm3's drvdata->spinlock type to raw_spin_lock_t. This will be good to align with etm4x. Reviewed-by: Jie Gan Signed-off-by: Yeoreum Yun --- drivers/hwtracing/coresight/coresight-etm.h | 2 +- .../coresight/coresight-etm3x-core.c | 18 +-- .../coresight/coresight-etm3x-sysfs.c | 130 +++++++++--------- 3 files changed, 75 insertions(+), 75 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracin= g/coresight/coresight-etm.h index 1d753cca2943..40f20daded4f 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -232,7 +232,7 @@ struct etm_drvdata { struct csdev_access csa; struct clk *atclk; struct coresight_device *csdev; - spinlock_t spinlock; + raw_spinlock_t spinlock; int cpu; int port_size; u8 arch; diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/h= wtracing/coresight/coresight-etm3x-core.c index a547a6d2e0bd..4a702b515733 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -511,7 +511,7 @@ static int etm_enable_sysfs(struct coresight_device *cs= dev, struct coresight_pat struct etm_enable_arg arg =3D { }; int ret; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); =20 drvdata->traceid =3D path->trace_id; =20 @@ -534,7 +534,7 @@ static int etm_enable_sysfs(struct coresight_device *cs= dev, struct coresight_pat if (ret) etm_release_trace_id(drvdata); =20 - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 if (!ret) dev_dbg(&csdev->dev, "ETM tracing enabled\n"); @@ -634,7 +634,7 @@ static void etm_disable_sysfs(struct coresight_device *= csdev) * DYING hotplug callback is serviced by the ETM driver. */ cpus_read_lock(); - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); =20 /* * Executing etm_disable_hw on the cpu whose ETM is being disabled @@ -643,7 +643,7 @@ static void etm_disable_sysfs(struct coresight_device *= csdev) smp_call_function_single(drvdata->cpu, etm_disable_sysfs_smp_call, drvdata, 1); =20 - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); cpus_read_unlock(); =20 /* @@ -709,7 +709,7 @@ static int etm_starting_cpu(unsigned int cpu) if (!etmdrvdata[cpu]) return 0; =20 - spin_lock(&etmdrvdata[cpu]->spinlock); + raw_spin_lock(&etmdrvdata[cpu]->spinlock); if (!etmdrvdata[cpu]->os_unlock) { etm_os_unlock(etmdrvdata[cpu]); etmdrvdata[cpu]->os_unlock =3D true; @@ -717,7 +717,7 @@ static int etm_starting_cpu(unsigned int cpu) =20 if (coresight_get_mode(etmdrvdata[cpu]->csdev)) etm_enable_hw(etmdrvdata[cpu]); - spin_unlock(&etmdrvdata[cpu]->spinlock); + raw_spin_unlock(&etmdrvdata[cpu]->spinlock); return 0; } =20 @@ -726,10 +726,10 @@ static int etm_dying_cpu(unsigned int cpu) if (!etmdrvdata[cpu]) return 0; =20 - spin_lock(&etmdrvdata[cpu]->spinlock); + raw_spin_lock(&etmdrvdata[cpu]->spinlock); if (coresight_get_mode(etmdrvdata[cpu]->csdev)) etm_disable_hw(etmdrvdata[cpu]); - spin_unlock(&etmdrvdata[cpu]->spinlock); + raw_spin_unlock(&etmdrvdata[cpu]->spinlock); return 0; } =20 @@ -856,7 +856,7 @@ static int etm_probe(struct amba_device *adev, const st= ruct amba_id *id) =20 desc.access =3D drvdata->csa =3D CSDEV_ACCESS_IOMEM(base); =20 - spin_lock_init(&drvdata->spinlock); + raw_spin_lock_init(&drvdata->spinlock); =20 drvdata->atclk =3D devm_clk_get_optional_enabled(dev, "atclk"); if (IS_ERR(drvdata->atclk)) diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm3x-sysfs.c index 762109307b86..42b12c33516b 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -49,13 +49,13 @@ static ssize_t etmsr_show(struct device *dev, struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); =20 pm_runtime_get_sync(dev->parent); - spin_lock_irqsave(&drvdata->spinlock, flags); + raw_spin_lock_irqsave(&drvdata->spinlock, flags); CS_UNLOCK(drvdata->csa.base); =20 val =3D etm_readl(drvdata, ETMSR); =20 CS_LOCK(drvdata->csa.base); - spin_unlock_irqrestore(&drvdata->spinlock, flags); + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); pm_runtime_put(dev->parent); =20 return sprintf(buf, "%#lx\n", val); @@ -76,7 +76,7 @@ static ssize_t reset_store(struct device *dev, return ret; =20 if (val) { - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); memset(config, 0, sizeof(struct etm_config)); config->mode =3D ETM_MODE_EXCLUDE; config->trigger_event =3D ETM_DEFAULT_EVENT_VAL; @@ -86,7 +86,7 @@ static ssize_t reset_store(struct device *dev, =20 etm_set_default(config); etm_release_trace_id(drvdata); - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); } =20 return size; @@ -117,7 +117,7 @@ static ssize_t mode_store(struct device *dev, if (ret) return ret; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); config->mode =3D val & ETM_MODE_ALL; =20 if (config->mode & ETM_MODE_EXCLUDE) @@ -168,12 +168,12 @@ static ssize_t mode_store(struct device *dev, if (config->mode & (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER)) etm_config_trace_mode(config); =20 - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return size; =20 err_unlock: - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); return ret; } static DEVICE_ATTR_RW(mode); @@ -299,9 +299,9 @@ static ssize_t addr_idx_store(struct device *dev, * Use spinlock to ensure index doesn't change while it gets * dereferenced multiple times within a spinlock block elsewhere. */ - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); config->addr_idx =3D val; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return size; } @@ -315,16 +315,16 @@ static ssize_t addr_single_show(struct device *dev, struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct etm_config *config =3D &drvdata->config; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; if (!(config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_NONE || config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_SINGLE)) { - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); return -EINVAL; } =20 val =3D config->addr_val[idx]; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return sprintf(buf, "%#lx\n", val); } @@ -343,17 +343,17 @@ static ssize_t addr_single_store(struct device *dev, if (ret) return ret; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; if (!(config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_NONE || config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_SINGLE)) { - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); return -EINVAL; } =20 config->addr_val[idx] =3D val; config->addr_type[idx] =3D ETM_ADDR_TYPE_SINGLE; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return size; } @@ -367,23 +367,23 @@ static ssize_t addr_range_show(struct device *dev, struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct etm_config *config =3D &drvdata->config; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; if (idx % 2 !=3D 0) { - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); return -EPERM; } if (!((config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_NONE && config->addr_type[idx + 1] =3D=3D ETM_ADDR_TYPE_NONE) || (config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_RANGE && config->addr_type[idx + 1] =3D=3D ETM_ADDR_TYPE_RANGE))) { - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); return -EPERM; } =20 val1 =3D config->addr_val[idx]; val2 =3D config->addr_val[idx + 1]; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return sprintf(buf, "%#lx %#lx\n", val1, val2); } @@ -403,17 +403,17 @@ static ssize_t addr_range_store(struct device *dev, if (val1 > val2) return -EINVAL; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; if (idx % 2 !=3D 0) { - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); return -EPERM; } if (!((config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_NONE && config->addr_type[idx + 1] =3D=3D ETM_ADDR_TYPE_NONE) || (config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_RANGE && config->addr_type[idx + 1] =3D=3D ETM_ADDR_TYPE_RANGE))) { - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); return -EPERM; } =20 @@ -422,7 +422,7 @@ static ssize_t addr_range_store(struct device *dev, config->addr_val[idx + 1] =3D val2; config->addr_type[idx + 1] =3D ETM_ADDR_TYPE_RANGE; config->enable_ctrl1 |=3D (1 << (idx/2)); - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return size; } @@ -436,16 +436,16 @@ static ssize_t addr_start_show(struct device *dev, struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct etm_config *config =3D &drvdata->config; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; if (!(config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_NONE || config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_START)) { - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); return -EPERM; } =20 val =3D config->addr_val[idx]; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return sprintf(buf, "%#lx\n", val); } @@ -464,11 +464,11 @@ static ssize_t addr_start_store(struct device *dev, if (ret) return ret; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; if (!(config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_NONE || config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_START)) { - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); return -EPERM; } =20 @@ -476,7 +476,7 @@ static ssize_t addr_start_store(struct device *dev, config->addr_type[idx] =3D ETM_ADDR_TYPE_START; config->startstop_ctrl |=3D (1 << idx); config->enable_ctrl1 |=3D ETMTECR1_START_STOP; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return size; } @@ -490,16 +490,16 @@ static ssize_t addr_stop_show(struct device *dev, struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct etm_config *config =3D &drvdata->config; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; if (!(config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_NONE || config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_STOP)) { - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); return -EPERM; } =20 val =3D config->addr_val[idx]; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return sprintf(buf, "%#lx\n", val); } @@ -518,11 +518,11 @@ static ssize_t addr_stop_store(struct device *dev, if (ret) return ret; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); idx =3D config->addr_idx; if (!(config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_NONE || config->addr_type[idx] =3D=3D ETM_ADDR_TYPE_STOP)) { - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); return -EPERM; } =20 @@ -530,7 +530,7 @@ static ssize_t addr_stop_store(struct device *dev, config->addr_type[idx] =3D ETM_ADDR_TYPE_STOP; config->startstop_ctrl |=3D (1 << (idx + 16)); config->enable_ctrl1 |=3D ETMTECR1_START_STOP; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return size; } @@ -543,9 +543,9 @@ static ssize_t addr_acctype_show(struct device *dev, struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct etm_config *config =3D &drvdata->config; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); val =3D config->addr_acctype[config->addr_idx]; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return sprintf(buf, "%#lx\n", val); } @@ -563,9 +563,9 @@ static ssize_t addr_acctype_store(struct device *dev, if (ret) return ret; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); config->addr_acctype[config->addr_idx] =3D val; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return size; } @@ -601,9 +601,9 @@ static ssize_t cntr_idx_store(struct device *dev, * Use spinlock to ensure index doesn't change while it gets * dereferenced multiple times within a spinlock block elsewhere. */ - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); config->cntr_idx =3D val; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return size; } @@ -616,9 +616,9 @@ static ssize_t cntr_rld_val_show(struct device *dev, struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct etm_config *config =3D &drvdata->config; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); val =3D config->cntr_rld_val[config->cntr_idx]; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return sprintf(buf, "%#lx\n", val); } @@ -636,9 +636,9 @@ static ssize_t cntr_rld_val_store(struct device *dev, if (ret) return ret; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); config->cntr_rld_val[config->cntr_idx] =3D val; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return size; } @@ -651,9 +651,9 @@ static ssize_t cntr_event_show(struct device *dev, struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct etm_config *config =3D &drvdata->config; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); val =3D config->cntr_event[config->cntr_idx]; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return sprintf(buf, "%#lx\n", val); } @@ -671,9 +671,9 @@ static ssize_t cntr_event_store(struct device *dev, if (ret) return ret; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); config->cntr_event[config->cntr_idx] =3D val & ETM_EVENT_MASK; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return size; } @@ -686,9 +686,9 @@ static ssize_t cntr_rld_event_show(struct device *dev, struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); struct etm_config *config =3D &drvdata->config; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); val =3D config->cntr_rld_event[config->cntr_idx]; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return sprintf(buf, "%#lx\n", val); } @@ -706,9 +706,9 @@ static ssize_t cntr_rld_event_store(struct device *dev, if (ret) return ret; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); config->cntr_rld_event[config->cntr_idx] =3D val & ETM_EVENT_MASK; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return size; } @@ -723,11 +723,11 @@ static ssize_t cntr_val_show(struct device *dev, struct etm_config *config =3D &drvdata->config; =20 if (!coresight_get_mode(drvdata->csdev)) { - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); for (i =3D 0; i < drvdata->nr_cntr; i++) ret +=3D sprintf(buf, "counter %d: %x\n", i, config->cntr_val[i]); - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); return ret; } =20 @@ -752,9 +752,9 @@ static ssize_t cntr_val_store(struct device *dev, if (ret) return ret; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); config->cntr_val[config->cntr_idx] =3D val; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return size; } @@ -947,13 +947,13 @@ static ssize_t seq_curr_state_show(struct device *dev, } =20 pm_runtime_get_sync(dev->parent); - spin_lock_irqsave(&drvdata->spinlock, flags); + raw_spin_lock_irqsave(&drvdata->spinlock, flags); =20 CS_UNLOCK(drvdata->csa.base); val =3D (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK); CS_LOCK(drvdata->csa.base); =20 - spin_unlock_irqrestore(&drvdata->spinlock, flags); + raw_spin_unlock_irqrestore(&drvdata->spinlock, flags); pm_runtime_put(dev->parent); out: return sprintf(buf, "%#lx\n", val); @@ -1012,9 +1012,9 @@ static ssize_t ctxid_idx_store(struct device *dev, * Use spinlock to ensure index doesn't change while it gets * dereferenced multiple times within a spinlock block elsewhere. */ - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); config->ctxid_idx =3D val; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return size; } @@ -1034,9 +1034,9 @@ static ssize_t ctxid_pid_show(struct device *dev, if (task_active_pid_ns(current) !=3D &init_pid_ns) return -EINVAL; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); val =3D config->ctxid_pid[config->ctxid_idx]; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return sprintf(buf, "%#lx\n", val); } @@ -1066,9 +1066,9 @@ static ssize_t ctxid_pid_store(struct device *dev, if (ret) return ret; =20 - spin_lock(&drvdata->spinlock); + raw_spin_lock(&drvdata->spinlock); config->ctxid_pid[config->ctxid_idx] =3D pid; - spin_unlock(&drvdata->spinlock); + raw_spin_unlock(&drvdata->spinlock); =20 return size; } --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Jun 20 11:51:19 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 4B6B53E715F for ; Wed, 15 Apr 2026 16:55:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272157; cv=none; b=RxkSwupTX41hqb2YeSsP7gVK7h/7jukFhT/bGPXKF0sJKTDuJySSeUqRuZpSc/wGDKwNAjDqzvCOba3ujh99cFNfaYEWsOne/CnNCsuOS1ERXBFzWA2AVZNDpSVs9sA7AQbyj1uOwghSQ7iQGYbiOMrBT0W7OTdBFIWQ5tpqLes= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272157; c=relaxed/simple; bh=QbjPBGf+qDexjmqY17g2JhCMbicIAL56LoDnXG6SlxA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=p+Cy4HVgm/l0yyvMm9E+RBSsspqhp+pwTQ68KaKLRyJoJ/l9PiMRdDctLeJTrBqHGgfbM7YSicx5HJ+jrNrsCZBzataU15hgsxTSMerhhcTMISbTz6N14Pv6NgT7rqdMS49ljJErg0R4I1TQa9m3R4ewEJRePqQBN0+uceO7WVI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=KRoiMImv; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="KRoiMImv" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D3C5C354D; Wed, 15 Apr 2026 09:55:48 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A667B3F7D8; Wed, 15 Apr 2026 09:55:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776272154; bh=QbjPBGf+qDexjmqY17g2JhCMbicIAL56LoDnXG6SlxA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KRoiMImvQmGggcV6/YZUBJ/YqjH+KVkx9pmXarfNvbGNLf0HPxUDD6dwWYgqukXHu lgKL6/inUhmEY3ENCBJOrsojK7Hr/H2AGHBfeq3nLvdfRGBDVzn0com9ndxuc3XKf0 PLnudcDj+5BNt7YvK0djukNmIw4QrHgdyiB36HPg= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v5 10/12] coresight: etm3x: introduce struct etm_caps Date: Wed, 15 Apr 2026 17:55:26 +0100 Message-Id: <20260415165528.3369607-11-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260415165528.3369607-1-yeoreum.yun@arm.com> References: <20260415165528.3369607-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce struct etm_caps to describe ETMv3 capabilities and move capabilities information into it. Since drvdata->etmccr and drvdata->etmccer are used to check whether it supports fifofull logic and timestamping, remove etmccr and etmccer field from drvdata and add relevant fields in etm_caps structure. Signed-off-by: Yeoreum Yun --- drivers/hwtracing/coresight/coresight-etm.h | 42 ++++++++++++------- .../coresight/coresight-etm3x-core.c | 39 ++++++++++------- .../coresight/coresight-etm3x-sysfs.c | 29 ++++++++----- 3 files changed, 67 insertions(+), 43 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracin= g/coresight/coresight-etm.h index 40f20daded4f..932bec82fb47 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -140,6 +140,30 @@ ETM_ADD_COMP_0 | \ ETM_EVENT_NOT_A) =20 +/** + * struct etm_caps - specifics ETM capabilities + * @port_size: port size as reported by ETMCR bit 4-6 and 21. + * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR. + * @nr_cntr: Number of counters as found in ETMCCR bit 13-15. + * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19. + * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22. + * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 2= 4-25. + * @fifofull: FIFOFULL logic is present. + * @timestamp: Timestamping is implemented. + * @retstack: Return stack is implemented. + */ +struct etm_caps { + int port_size; + u8 nr_addr_cmp; + u8 nr_cntr; + u8 nr_ext_inp; + u8 nr_ext_out; + u8 nr_ctxid_cmp; + bool fifofull : 1; + bool timestamp : 1; + bool retstack : 1; +}; + /** * struct etm_config - configuration information related to an ETM * @mode: controls various modes supported by this ETM/PTM. @@ -212,19 +236,12 @@ struct etm_config { * @csdev: component vitals needed by the framework. * @spinlock: only one at a time pls. * @cpu: the cpu this component is affined to. - * @port_size: port size as reported by ETMCR bit 4-6 and 21. * @arch: ETM/PTM version number. + * @caps: ETM capabilities. * @use_cpu14: true if management registers need to be accessed via CP14. * @sticky_enable: true if ETM base configuration has been done. * @boot_enable:true if we should start tracing at boot time. * @os_unlock: true if access to management registers is allowed. - * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR. - * @nr_cntr: Number of counters as found in ETMCCR bit 13-15. - * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19. - * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22. - * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 2= 4-25. - * @etmccr: value of register ETMCCR. - * @etmccer: value of register ETMCCER. * @traceid: value of the current ID for this component. * @config: structure holding configuration parameters. */ @@ -234,19 +251,12 @@ struct etm_drvdata { struct coresight_device *csdev; raw_spinlock_t spinlock; int cpu; - int port_size; u8 arch; + struct etm_caps caps; bool use_cp14; bool sticky_enable; bool boot_enable; bool os_unlock; - u8 nr_addr_cmp; - u8 nr_cntr; - u8 nr_ext_inp; - u8 nr_ext_out; - u8 nr_ctxid_cmp; - u32 etmccr; - u32 etmccer; u32 traceid; struct etm_config config; }; diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/h= wtracing/coresight/coresight-etm3x-core.c index 4a702b515733..e42ca346da91 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -308,6 +308,7 @@ void etm_config_trace_mode(struct etm_config *config) static int etm_parse_event_config(struct etm_drvdata *drvdata, struct perf_event *event) { + const struct etm_caps *caps =3D &drvdata->caps; struct etm_config *config =3D &drvdata->config; struct perf_event_attr *attr =3D &event->attr; u8 ts_level; @@ -356,8 +357,7 @@ static int etm_parse_event_config(struct etm_drvdata *d= rvdata, * has ret stack) on the same SoC. So only enable when it can be honored * - trace will still continue normally otherwise. */ - if (ATTR_CFG_GET_FLD(attr, retstack) && - (drvdata->etmccer & ETMCCER_RETSTACK)) + if (ATTR_CFG_GET_FLD(attr, retstack) && (caps->retstack)) config->ctrl |=3D ETMCR_RETURN_STACK; =20 return 0; @@ -367,6 +367,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) { int i, rc; u32 etmcr; + const struct etm_caps *caps =3D &drvdata->caps; struct etm_config *config =3D &drvdata->config; struct coresight_device *csdev =3D drvdata->csdev; =20 @@ -388,7 +389,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) etmcr =3D etm_readl(drvdata, ETMCR); /* Clear setting from a previous run if need be */ etmcr &=3D ~ETM3X_SUPPORTED_OPTIONS; - etmcr |=3D drvdata->port_size; + etmcr |=3D caps->port_size; etmcr |=3D ETMCR_ETM_EN; etm_writel(drvdata, config->ctrl | etmcr, ETMCR); etm_writel(drvdata, config->trigger_event, ETMTRIGGER); @@ -396,11 +397,11 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) etm_writel(drvdata, config->enable_event, ETMTEEVR); etm_writel(drvdata, config->enable_ctrl1, ETMTECR1); etm_writel(drvdata, config->fifofull_level, ETMFFLR); - for (i =3D 0; i < drvdata->nr_addr_cmp; i++) { + for (i =3D 0; i < caps->nr_addr_cmp; i++) { etm_writel(drvdata, config->addr_val[i], ETMACVRn(i)); etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i)); } - for (i =3D 0; i < drvdata->nr_cntr; i++) { + for (i =3D 0; i < caps->nr_cntr; i++) { etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i)); etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i)); etm_writel(drvdata, config->cntr_rld_event[i], @@ -414,9 +415,9 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR); etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR); etm_writel(drvdata, config->seq_curr_state, ETMSQR); - for (i =3D 0; i < drvdata->nr_ext_out; i++) + for (i =3D 0; i < caps->nr_ext_out; i++) etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i)); - for (i =3D 0; i < drvdata->nr_ctxid_cmp; i++) + for (i =3D 0; i < caps->nr_ctxid_cmp; i++) etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i)); etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR); etm_writel(drvdata, config->sync_freq, ETMSYNCFR); @@ -563,6 +564,7 @@ static int etm_enable(struct coresight_device *csdev, s= truct perf_event *event, static void etm_disable_hw(struct etm_drvdata *drvdata) { int i; + const struct etm_caps *caps =3D &drvdata->caps; struct etm_config *config =3D &drvdata->config; struct coresight_device *csdev =3D drvdata->csdev; =20 @@ -572,7 +574,7 @@ static void etm_disable_hw(struct etm_drvdata *drvdata) /* Read back sequencer and counters for post trace analysis */ config->seq_curr_state =3D (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK); =20 - for (i =3D 0; i < drvdata->nr_cntr; i++) + for (i =3D 0; i < caps->nr_cntr; i++) config->cntr_val[i] =3D etm_readl(drvdata, ETMCNTVRn(i)); =20 etm_set_pwrdwn(drvdata); @@ -754,7 +756,9 @@ static void etm_init_arch_data(void *info) { u32 etmidr; u32 etmccr; + u32 etmccer; struct etm_drvdata *drvdata =3D info; + struct etm_caps *caps =3D &drvdata->caps; =20 /* Make sure all registers are accessible */ etm_os_unlock(drvdata); @@ -779,16 +783,19 @@ static void etm_init_arch_data(void *info) /* Find all capabilities */ etmidr =3D etm_readl(drvdata, ETMIDR); drvdata->arch =3D BMVAL(etmidr, 4, 11); - drvdata->port_size =3D etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK; + caps->port_size =3D etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK; + + etmccer =3D etm_readl(drvdata, ETMCCER); + caps->timestamp =3D !!(etmccer & ETMCCER_TIMESTAMP); + caps->retstack =3D !!(etmccer & ETMCCER_RETSTACK); =20 - drvdata->etmccer =3D etm_readl(drvdata, ETMCCER); etmccr =3D etm_readl(drvdata, ETMCCR); - drvdata->etmccr =3D etmccr; - drvdata->nr_addr_cmp =3D BMVAL(etmccr, 0, 3) * 2; - drvdata->nr_cntr =3D BMVAL(etmccr, 13, 15); - drvdata->nr_ext_inp =3D BMVAL(etmccr, 17, 19); - drvdata->nr_ext_out =3D BMVAL(etmccr, 20, 22); - drvdata->nr_ctxid_cmp =3D BMVAL(etmccr, 24, 25); + caps->fifofull =3D !!(etmccr & ETMCCR_FIFOFULL); + caps->nr_addr_cmp =3D BMVAL(etmccr, 0, 3) * 2; + caps->nr_cntr =3D BMVAL(etmccr, 13, 15); + caps->nr_ext_inp =3D BMVAL(etmccr, 17, 19); + caps->nr_ext_out =3D BMVAL(etmccr, 20, 22); + caps->nr_ctxid_cmp =3D BMVAL(etmccr, 24, 25); =20 coresight_clear_self_claim_tag_unlocked(&drvdata->csa); etm_set_pwrdwn(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm3x-sysfs.c index 42b12c33516b..f7330d830e21 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -15,8 +15,9 @@ static ssize_t nr_addr_cmp_show(struct device *dev, { unsigned long val; struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etm_caps *caps =3D &drvdata->caps; =20 - val =3D drvdata->nr_addr_cmp; + val =3D caps->nr_addr_cmp; return sprintf(buf, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_addr_cmp); @@ -25,8 +26,9 @@ static ssize_t nr_cntr_show(struct device *dev, struct device_attribute *attr, char *buf) { unsigned long val; struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etm_caps *caps =3D &drvdata->caps; =20 - val =3D drvdata->nr_cntr; + val =3D caps->nr_cntr; return sprintf(buf, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_cntr); @@ -37,7 +39,7 @@ static ssize_t nr_ctxid_cmp_show(struct device *dev, unsigned long val; struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); =20 - val =3D drvdata->nr_ctxid_cmp; + val =3D drvdata->caps.nr_ctxid_cmp; return sprintf(buf, "%#lx\n", val); } static DEVICE_ATTR_RO(nr_ctxid_cmp); @@ -80,7 +82,7 @@ static ssize_t reset_store(struct device *dev, memset(config, 0, sizeof(struct etm_config)); config->mode =3D ETM_MODE_EXCLUDE; config->trigger_event =3D ETM_DEFAULT_EVENT_VAL; - for (i =3D 0; i < drvdata->nr_addr_cmp; i++) { + for (i =3D 0; i < drvdata->caps.nr_addr_cmp; i++) { config->addr_type[i] =3D ETM_ADDR_TYPE_NONE; } =20 @@ -111,6 +113,7 @@ static ssize_t mode_store(struct device *dev, int ret; unsigned long val; struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etm_caps *caps =3D &drvdata->caps; struct etm_config *config =3D &drvdata->config; =20 ret =3D kstrtoul(buf, 16, &val); @@ -131,7 +134,7 @@ static ssize_t mode_store(struct device *dev, config->ctrl &=3D ~ETMCR_CYC_ACC; =20 if (config->mode & ETM_MODE_STALL) { - if (!(drvdata->etmccr & ETMCCR_FIFOFULL)) { + if (!caps->fifofull) { dev_warn(dev, "stall mode not supported\n"); ret =3D -EINVAL; goto err_unlock; @@ -141,7 +144,7 @@ static ssize_t mode_store(struct device *dev, config->ctrl &=3D ~ETMCR_STALL_MODE; =20 if (config->mode & ETM_MODE_TIMESTAMP) { - if (!(drvdata->etmccer & ETMCCER_TIMESTAMP)) { + if (!caps->timestamp) { dev_warn(dev, "timestamp not supported\n"); ret =3D -EINVAL; goto err_unlock; @@ -286,13 +289,14 @@ static ssize_t addr_idx_store(struct device *dev, int ret; unsigned long val; struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etm_caps *caps =3D &drvdata->caps; struct etm_config *config =3D &drvdata->config; =20 ret =3D kstrtoul(buf, 16, &val); if (ret) return ret; =20 - if (val >=3D drvdata->nr_addr_cmp) + if (val >=3D caps->nr_addr_cmp) return -EINVAL; =20 /* @@ -589,13 +593,14 @@ static ssize_t cntr_idx_store(struct device *dev, int ret; unsigned long val; struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etm_caps *caps =3D &drvdata->caps; struct etm_config *config =3D &drvdata->config; =20 ret =3D kstrtoul(buf, 16, &val); if (ret) return ret; =20 - if (val >=3D drvdata->nr_cntr) + if (val >=3D caps->nr_cntr) return -EINVAL; /* * Use spinlock to ensure index doesn't change while it gets @@ -720,18 +725,19 @@ static ssize_t cntr_val_show(struct device *dev, int i, ret =3D 0; u32 val; struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etm_caps *caps =3D &drvdata->caps; struct etm_config *config =3D &drvdata->config; =20 if (!coresight_get_mode(drvdata->csdev)) { raw_spin_lock(&drvdata->spinlock); - for (i =3D 0; i < drvdata->nr_cntr; i++) + for (i =3D 0; i < caps->nr_cntr; i++) ret +=3D sprintf(buf, "counter %d: %x\n", i, config->cntr_val[i]); raw_spin_unlock(&drvdata->spinlock); return ret; } =20 - for (i =3D 0; i < drvdata->nr_cntr; i++) { + for (i =3D 0; i < caps->nr_cntr; i++) { val =3D etm_readl(drvdata, ETMCNTVRn(i)); ret +=3D sprintf(buf, "counter %d: %x\n", i, val); } @@ -999,13 +1005,14 @@ static ssize_t ctxid_idx_store(struct device *dev, int ret; unsigned long val; struct etm_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + const struct etm_caps *caps =3D &drvdata->caps; struct etm_config *config =3D &drvdata->config; =20 ret =3D kstrtoul(buf, 16, &val); if (ret) return ret; =20 - if (val >=3D drvdata->nr_ctxid_cmp) + if (val >=3D caps->nr_ctxid_cmp) return -EINVAL; =20 /* --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Jun 20 11:51:19 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 8DEC13ECBC6 for ; Wed, 15 Apr 2026 16:55:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272159; cv=none; b=RUekTGHM7ScIWFdbb9Gl5ZYzT/s4FDyhh/zAfXuqJQ6CjPCOarQqsM/RpwwUCHMFDr8fxGfkOIt+eojFtxDx1+2/uDfOgirtwl1lpPiVEkllwLCZNRD4EMLiBVmLunpJ1Aip+8Cm8HsXlWzXVrRMSd1BdnR7Zlo3cx4Gzo1w+xM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272159; c=relaxed/simple; bh=WNMVfjl8gaY3hVEW67D1uHMsfHd4ddBYKHiIsXZZOYA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=o9Jgu+UqVZb0dWwBNy0q79NWPRF12Sgc7rstr/83Wxc+XHTCrwVnVh3R47ZoC8trZ+G5gqQcbctXi/WXt8MsBoIAwUOyHl/ey2WP8m+OYVpfPKdRbJMl9L92Tg3FiSGDfzZk5RFGhcvPjE2nOXz3ipVZqFIZzL30Z2X6mg5QjZg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=hyn6kJjn; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="hyn6kJjn" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 14FDC32D1; Wed, 15 Apr 2026 09:55:51 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D91CB3F7D8; Wed, 15 Apr 2026 09:55:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776272156; bh=WNMVfjl8gaY3hVEW67D1uHMsfHd4ddBYKHiIsXZZOYA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=hyn6kJjnOq74GEIuygELvwNojFv+O7sX9PQj9YIZDMSGvosb9x80PxinpYS0N+voM OyOXvbIznM4loqHOCjeaMe/awUXEm/ZuX8iK+u+WgCZzuUEtfxIMTJFUYKRlCO1g0o czYjCc6S03LsvlIdGckIZqJLR1dToi/qvPBbgv04= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v5 11/12] coresight: etm3x: fix inconsistencies with sysfs configuration Date: Wed, 15 Apr 2026 17:55:27 +0100 Message-Id: <20260415165528.3369607-12-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260415165528.3369607-1-yeoreum.yun@arm.com> References: <20260415165528.3369607-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current ETM3x configuration via sysfs can lead to the following inconsistencies: - If a configuration is modified via sysfs while a perf session is active, the running configuration may differ between before a sched-out and after a subsequent sched-in. To resolve these issues, separate the configuration into: - active_config: the configuration applied to the current session - config: the configuration set via sysfs Additionally: - Since active_config and related fields are accessed only by the local C= PU in etm_enable/disable_sysfs_smp_call() (similar to perf enable/disable), remove the lock/unlock from the sysfs enable/disable path and starting/dying_cpu path except when to access config fields only. Signed-off-by: Yeoreum Yun --- drivers/hwtracing/coresight/coresight-etm.h | 2 + .../coresight/coresight-etm3x-core.c | 49 ++++++++++--------- 2 files changed, 27 insertions(+), 24 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracin= g/coresight/coresight-etm.h index 932bec82fb47..01f1a7f2559c 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -243,6 +243,7 @@ struct etm_config { * @boot_enable:true if we should start tracing at boot time. * @os_unlock: true if access to management registers is allowed. * @traceid: value of the current ID for this component. + * @active_config: structure holding current running configuration paramet= ers. * @config: structure holding configuration parameters. */ struct etm_drvdata { @@ -258,6 +259,7 @@ struct etm_drvdata { bool boot_enable; bool os_unlock; u32 traceid; + struct etm_config active_config; struct etm_config config; }; =20 diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/h= wtracing/coresight/coresight-etm3x-core.c index e42ca346da91..706a4c7a40df 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -309,7 +309,7 @@ static int etm_parse_event_config(struct etm_drvdata *d= rvdata, struct perf_event *event) { const struct etm_caps *caps =3D &drvdata->caps; - struct etm_config *config =3D &drvdata->config; + struct etm_config *config =3D &drvdata->active_config; struct perf_event_attr *attr =3D &event->attr; u8 ts_level; =20 @@ -368,7 +368,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) int i, rc; u32 etmcr; const struct etm_caps *caps =3D &drvdata->caps; - struct etm_config *config =3D &drvdata->config; + struct etm_config *config =3D &drvdata->active_config; struct coresight_device *csdev =3D drvdata->csdev; =20 CS_UNLOCK(drvdata->csa.base); @@ -442,29 +442,38 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) =20 struct etm_enable_arg { struct etm_drvdata *drvdata; + u32 traceid; + struct etm_config config; int rc; }; =20 static void etm_enable_sysfs_smp_call(void *info) { struct etm_enable_arg *arg =3D info; + struct etm_drvdata *drvdata; struct coresight_device *csdev; =20 if (WARN_ON(!arg)) return; =20 - csdev =3D arg->drvdata->csdev; + drvdata =3D arg->drvdata; + csdev =3D drvdata->csdev; if (!coresight_take_mode(csdev, CS_MODE_SYSFS)) { /* Someone is already using the tracer */ arg->rc =3D -EBUSY; return; } =20 + drvdata->active_config =3D arg->config; + drvdata->traceid =3D arg->traceid; + arg->rc =3D etm_enable_hw(arg->drvdata); =20 /* The tracer didn't start */ if (arg->rc) coresight_set_mode(csdev, CS_MODE_DISABLED); + else + drvdata->sticky_enable =3D true; } =20 static int etm_cpu_id(struct coresight_device *csdev) @@ -512,9 +521,6 @@ static int etm_enable_sysfs(struct coresight_device *cs= dev, struct coresight_pat struct etm_enable_arg arg =3D { }; int ret; =20 - raw_spin_lock(&drvdata->spinlock); - - drvdata->traceid =3D path->trace_id; =20 /* * Configure the ETM only if the CPU is online. If it isn't online @@ -522,23 +528,25 @@ static int etm_enable_sysfs(struct coresight_device *= csdev, struct coresight_pat */ if (cpu_online(drvdata->cpu)) { arg.drvdata =3D drvdata; + arg.traceid =3D path->trace_id; + + raw_spin_lock(&drvdata->spinlock); + arg.config =3D drvdata->config; + raw_spin_unlock(&drvdata->spinlock); + ret =3D smp_call_function_single(drvdata->cpu, etm_enable_sysfs_smp_call, &arg, 1); if (!ret) ret =3D arg.rc; - if (!ret) - drvdata->sticky_enable =3D true; } else { ret =3D -ENODEV; } =20 - if (ret) - etm_release_trace_id(drvdata); - - raw_spin_unlock(&drvdata->spinlock); - if (!ret) dev_dbg(&csdev->dev, "ETM tracing enabled\n"); + else + etm_release_trace_id(drvdata); + return ret; } =20 @@ -565,7 +573,7 @@ static void etm_disable_hw(struct etm_drvdata *drvdata) { int i; const struct etm_caps *caps =3D &drvdata->caps; - struct etm_config *config =3D &drvdata->config; + struct etm_config *config =3D &drvdata->active_config; struct coresight_device *csdev =3D drvdata->csdev; =20 CS_UNLOCK(drvdata->csa.base); @@ -636,7 +644,6 @@ static void etm_disable_sysfs(struct coresight_device *= csdev) * DYING hotplug callback is serviced by the ETM driver. */ cpus_read_lock(); - raw_spin_lock(&drvdata->spinlock); =20 /* * Executing etm_disable_hw on the cpu whose ETM is being disabled @@ -645,7 +652,6 @@ static void etm_disable_sysfs(struct coresight_device *= csdev) smp_call_function_single(drvdata->cpu, etm_disable_sysfs_smp_call, drvdata, 1); =20 - raw_spin_unlock(&drvdata->spinlock); cpus_read_unlock(); =20 /* @@ -711,15 +717,11 @@ static int etm_starting_cpu(unsigned int cpu) if (!etmdrvdata[cpu]) return 0; =20 - raw_spin_lock(&etmdrvdata[cpu]->spinlock); - if (!etmdrvdata[cpu]->os_unlock) { + if (!etmdrvdata[cpu]->os_unlock) etm_os_unlock(etmdrvdata[cpu]); - etmdrvdata[cpu]->os_unlock =3D true; - } =20 if (coresight_get_mode(etmdrvdata[cpu]->csdev)) etm_enable_hw(etmdrvdata[cpu]); - raw_spin_unlock(&etmdrvdata[cpu]->spinlock); return 0; } =20 @@ -728,10 +730,8 @@ static int etm_dying_cpu(unsigned int cpu) if (!etmdrvdata[cpu]) return 0; =20 - raw_spin_lock(&etmdrvdata[cpu]->spinlock); if (coresight_get_mode(etmdrvdata[cpu]->csdev)) etm_disable_hw(etmdrvdata[cpu]); - raw_spin_unlock(&etmdrvdata[cpu]->spinlock); return 0; } =20 @@ -884,7 +884,8 @@ static int etm_probe(struct amba_device *adev, const st= ruct amba_id *id) if (etm_arch_supported(drvdata->arch) =3D=3D false) return -EINVAL; =20 - etm_set_default(&drvdata->config); + etm_set_default(&drvdata->active_config); + drvdata->config =3D drvdata->active_config; =20 pdata =3D coresight_get_platform_data(dev); if (IS_ERR(pdata)) --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Jun 20 11:51:19 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 3E8AB3ED5B2 for ; Wed, 15 Apr 2026 16:55:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272160; cv=none; b=ta3uNAhVHJxwY1dnMDTok1Pwi3VoVt+8efhsEIMW4vQsS8c7GVlAizQSKsylGzztPpx2jP3RSI0yAKsWRlnoICHRSv/LuaMtS7wmMldfFRofeGueN7BV/xuYmFOp/uzGoWOuZNxjU8HnfA7pXYL/9gIb3HAPBH+WFmzyThQKsXc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272160; c=relaxed/simple; bh=dBlTY/m9WM8JFBhitEJBbiQCl2HVEF88g590hzectJQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=rm2H/jkkaLNSxpZdsISRtj/rVCPCtObM1WNRY1Jn50fbxUsDI5r3P/1Sko0YgMPkrSu7eTLrhXBOsgRgUQOf8C+ukVh7DzrqAXP6Su66fKS1D6T2rmGaLT/PqzpIYq8+E63nPugCAv+gV4FBZBWzoIzjW9vJ+Ocu0MEx2O7VF9w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=vfz2VPZ+; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="vfz2VPZ+" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4176732FB; Wed, 15 Apr 2026 09:55:53 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 15A013F7D8; Wed, 15 Apr 2026 09:55:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776272158; bh=dBlTY/m9WM8JFBhitEJBbiQCl2HVEF88g590hzectJQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=vfz2VPZ+E4+S/V8gmtkEd82xHkMvjDsBPzkeQ5dRYm453U+QxKRxSfCeyv3ItuxOg 6yaNV4eyCAh0PJg1gnW8nbgNtOHBZXQMzgTonqD2jc8eMOT7+yWe2mfoISgCHzlASk QRDmLZ2RpWTLdV83NvqBxDGJUCJLTa8oeTA9iCPc= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v5 12/12] coresight: etm3x: remove redundant call etm_enable_hw() with hotplug Date: Wed, 15 Apr 2026 17:55:28 +0100 Message-Id: <20260415165528.3369607-13-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260415165528.3369607-1-yeoreum.yun@arm.com> References: <20260415165528.3369607-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The cpu_online_mask is set at the CPUHP_BRINGUP_CPU step. In other words, if etm4_enable_sysfs() is called between CPUHP_BRINGUP_CPU and CPUHP_AP_ARM_CORESIGHT_STARTING, etm_enable_hw() may be invoked in etm_enable_sysfs_smp_call() and then executed again in etm_starting_cpu(). To remove this redundant call, take the hotplug lock before executing etm_enable_sysfs_smp_call(). Signed-off-by: Yeoreum Yun --- .../coresight/coresight-etm3x-core.c | 24 +++++++++---------- 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/h= wtracing/coresight/coresight-etm3x-core.c index 706a4c7a40df..8bf7ae276096 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -521,26 +521,26 @@ static int etm_enable_sysfs(struct coresight_device *= csdev, struct coresight_pat struct etm_enable_arg arg =3D { }; int ret; =20 + arg.drvdata =3D drvdata; + arg.traceid =3D path->trace_id; + + raw_spin_lock(&drvdata->spinlock); + arg.config =3D drvdata->config; + raw_spin_unlock(&drvdata->spinlock); =20 /* * Configure the ETM only if the CPU is online. If it isn't online * hw configuration will take place on the local CPU during bring up. */ - if (cpu_online(drvdata->cpu)) { - arg.drvdata =3D drvdata; - arg.traceid =3D path->trace_id; - - raw_spin_lock(&drvdata->spinlock); - arg.config =3D drvdata->config; - raw_spin_unlock(&drvdata->spinlock); - + cpus_read_lock(); ret =3D smp_call_function_single(drvdata->cpu, etm_enable_sysfs_smp_call, &arg, 1); - if (!ret) - ret =3D arg.rc; - } else { + cpus_read_unlock(); + + if (!ret) + ret =3D arg.rc; + else ret =3D -ENODEV; - } =20 if (!ret) dev_dbg(&csdev->dev, "ETM tracing enabled\n"); --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}