From nobody Tue Jun 16 01:38:28 2026 Received: from mail-pg1-f182.google.com (mail-pg1-f182.google.com [209.85.215.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D2CED246770 for ; Wed, 15 Apr 2026 03:20:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.215.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776223242; cv=none; b=NEEvFF1w8wMYIwQIEILizE+944HGUdyIUv/17G/xkBWeeHmurp0sPd+mrjdPErjrKOEItOlImGdpzSaVy5grRgGMBhfSnmsX+BpVQcWfF9wyOJz/IHX12d4JxdYw/SJSWvCuZi41MGll8zkg6epbfQlNCI9BW8HiL/VGW9VEG3I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776223242; c=relaxed/simple; bh=/que3W7AC2Dibu4aohSxNBs50toBgGZ04DbzThd7tL8=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=qR8u2Ez0sdNUeA8VQ3ggljteZ5p3fW4DfJ+C5kBkPrYICAiYRcerTpI3AX1Ra/mes0IKUlY8trVnhd7++WiOL4lAkTIL30T1kBv4gzq3W6XvmzsfK+zHOeHq6LkjqLjloXQeYqx9T2qDQCcOaaSclNRZ8moVgfWeYj4yheUJu6I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com; spf=pass smtp.mailfrom=bytedance.com; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b=StF5CheS; arc=none smtp.client-ip=209.85.215.182 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=bytedance.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bytedance.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bytedance.com header.i=@bytedance.com header.b="StF5CheS" Received: by mail-pg1-f182.google.com with SMTP id 41be03b00d2f7-c76c60c7502so2478280a12.0 for ; Tue, 14 Apr 2026 20:20:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bytedance.com; s=google; t=1776223240; x=1776828040; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=McgM1ed/7uKct8MrTaZt/faoB6VvbROugN9eTgcOxBM=; b=StF5CheSOI/q+fE/oKLw3bTHVcw+aFu+KMS1mrlJ0NlTyuOwiF2bCbIXdJN4wfKhYo 3GWOU7olljYT0pFnrKdQsA6XuVt6ECjpPkMbODSj7c+jH3OOZ1gDoKp+1RCiUU5Dggwg F8693wAX7Gn4qAfShbVSOh7RqKe+w/xR8ol1i7XXnGNqJDDWnkjOVikebO3SxoGEIAf+ FIXAsfMKgQXjYR8XoDhlL6Ipl1w5fOe6G7w/DbrLDUsxpYrNiLwPmoOjs838XdQ3Vn/p rO1uNChMK3RLVhYhosilELeKp25Heni19jBB6i5AOW6IPeotfMklhI/HxECwSQHcoPBK P4eQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1776223240; x=1776828040; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=McgM1ed/7uKct8MrTaZt/faoB6VvbROugN9eTgcOxBM=; b=L+0e5jXffzzab/1VeftFZi4dbTauK77BVioSmnsHOD2t5m2AW8x/VYkqhZ4CqBWIKt s+5WBWAqSCvPJPq5q4mqXZNry4bmF5MMY95DaEaKiClNPfh/glieT3jw0bVszPVnX+Gz UGAtnsAmmGGrwb50UtW1M1GkXnEozdhN+kmMl+86OZINfdnqFoxOEjqjImOZ55m+yP55 JSLX9lz8hO+h9HGJt1jYl9IcAScUeGadaRkRUWD4Ki663to0P8zJ6YAbFpjWYfr/6HCz FRbhUT99aCL4cX89cUhml66tbfyW8aX/LbtYWqk1kQHF26XyvNLj2UI2FWm4xjM0kGxh 2rMQ== X-Forwarded-Encrypted: i=1; AFNElJ8A1lUsEo86RJCxKlMlk6WuUqK2wst49VWX4P4KONGEhNg52XeaKSm/EiI4446Ws4dqRcYi6+TznYtxzIs=@vger.kernel.org X-Gm-Message-State: AOJu0YwRFXB8Of0AmUhJxBNZCRlxOcMY5FEEDPBxJAGUHpu0pROgp1TS licn647We3F4SbcB8VbJdQPTfHtSMYlbw8vItBBTzOcAQ8H4EG7yhy70YAR9M9XtKyM= X-Gm-Gg: AeBDieuzdwycW4s1SpRAxkl8Z0L+VmrTyoPb1AyZxixC02poxD2ALYoY4F+mU5qKdvL R9wBJQbnI2g1W8V924ohZ/wjuUs/1A7i2M+1jahU5TAOVk5WpVbglvxhOxR5N+OhzsDJYkzARxt NrbUNKnPVittEA1z8l4vAUkJ8nQ7LQz6kmiK+3A5PxaWxRyD+awwwFsJqzu20rNxX8iNBVyKSTl CTCx1/BiBTUqLIK6OscS6FQnSX0U0lXCDmcDfPb6Moon8RCGoyVOeXxNZ2HLNw3b4G3Uq7kKx9t gvqCHRidSOPBvYdRNqccdJVj82mWSvcHHYOdKSo0Qn1v+ItkRPnKmGefzeuQgNuQTSpqe3glkmo M+V6+/0dfGved4EOzizqRe4E8uZbUGh5PAYCKzwkG7TdG0OqhE4aeGhHsviBsuRuEETuBhQozrX JexJOgglSLaOOqvfOHX/CKT2atqliK9oWoBe8RfLT8v/3J51stH8ckRMTVNuRMfXHXW7dw51hVm 4i0nM7DSQ== X-Received: by 2002:a17:90b:5283:b0:35f:c5b8:ef6d with SMTP id 98e67ed59e1d1-35fc5b8f328mr4090582a91.3.1776223239924; Tue, 14 Apr 2026 20:20:39 -0700 (PDT) Received: from FJ7FR2JRQ3.bytedance.net ([203.208.167.150]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-35fd3203a76sm372188a91.13.2026.04.14.20.20.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 14 Apr 2026 20:20:39 -0700 (PDT) From: Zhanpeng Zhang To: atish.patra@linux.dev, anup@brainfault.org, will@kernel.org, palmer@dabbelt.com, pjw@kernel.org, cuiyunhui@bytedance.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, yuanzhu@bytedance.com, Zhanpeng Zhang Subject: [PATCH] drivers/perf: riscv: do not restart throttled events after overflow Date: Wed, 15 Apr 2026 11:20:17 +0800 Message-ID: <20260415032017.10712-1-zhangzhanpeng.jasper@bytedance.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Perf core uses `event->hw.interrupts =3D=3D MAX_INTERRUPTS` to keep throttled events stopped until it explicitly unthrottles them later. However, current RISC-V Perf/PMU system unconditionally restarts all the counters at the end of overflow handler, which bypasses the perf core's throttle mechanism. Therefore, an unreasonable small sampling period such as `perf top -c 20` may cause an IRQ storm and eventually leads to soft lockup. Fix this by filtering the counter start/restart mask: do not restart counters for events already marked as throttled by the perf core. This retains the throttle effect and prevents interrupt storms in such workloads. Signed-off-by: Zhanpeng Zhang --- drivers/perf/riscv_pmu_sbi.c | 45 ++++++++++++++++++++++++++++++++++-- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 385af5e6e6d0..664f9b86c468 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -60,6 +60,33 @@ asm volatile(ALTERNATIVE( \ #define PERF_EVENT_FLAG_LEGACY BIT(SYSCTL_LEGACY) =20 PMU_FORMAT_ATTR(event, "config:0-55"); +static inline bool rvpmu_perf_event_is_throttled(struct perf_event *event) +{ + return event->hw.interrupts =3D=3D MAX_INTERRUPTS; +} + +/* + * Return a mask of counters that must not be restarted. + * `base` is the starting bit index to limit the mask to this long word. + */ +static inline unsigned long rvpmu_get_throttled_mask(struct perf_event **e= vents, + unsigned long mask, + int base) +{ + unsigned long tmp =3D mask, throttled =3D 0; + int bit =3D -1; + int nr_bits =3D min_t(int, BITS_PER_LONG, RISCV_MAX_COUNTERS - base); + + for_each_set_bit(bit, &tmp, nr_bits) { + struct perf_event *event =3D events[bit]; + + if (!event || rvpmu_perf_event_is_throttled(event)) + throttled |=3D BIT(bit); + } + + return throttled; +} + PMU_FORMAT_ATTR(firmware, "config:62-63"); =20 static bool sbi_v2_available; @@ -1005,6 +1032,8 @@ static inline void pmu_sbi_start_ovf_ctrs_snapshot(st= ruct cpu_hw_events *cpu_hw_ for_each_set_bit(idx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) { if (ctr_ovf_mask & BIT(idx)) { event =3D cpu_hw_evt->events[idx]; + if (!event || rvpmu_perf_event_is_throttled(event)) + continue; hwc =3D &event->hw; max_period =3D riscv_pmu_ctr_get_width_mask(event); init_val =3D local64_read(&hwc->prev_count) & max_period; @@ -1017,13 +1046,25 @@ static inline void pmu_sbi_start_ovf_ctrs_snapshot(= struct cpu_hw_events *cpu_hw_ } =20 for (i =3D 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) { + int base =3D i * BITS_PER_LONG; + unsigned long throttled; + unsigned long used; + unsigned long start_mask; + + used =3D cpu_hw_evt->used_hw_ctrs[i]; + throttled =3D rvpmu_get_throttled_mask(cpu_hw_evt->events + base, + used, base); + start_mask =3D used & ~throttled; + if (!start_mask) + continue; + /* Restore the counter values to relative indices for used hw counters */ for_each_set_bit(idx, &cpu_hw_evt->used_hw_ctrs[i], BITS_PER_LONG) sdata->ctr_values[idx] =3D cpu_hw_evt->snapshot_cval_shcopy[idx + i * BITS_PER_LONG]; /* Start all the counters in a single shot */ - sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx * BITS_PER_LONG, - cpu_hw_evt->used_hw_ctrs[i], flag, 0, 0, 0); + sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG, + start_mask, flag, 0, 0, 0); } } =20 --=20 2.50.1 (Apple Git-155)