From nobody Tue Jun 16 01:36:50 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [194.37.255.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3AB41F2B8D; Wed, 15 Apr 2026 08:17:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=194.37.255.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776241047; cv=none; b=Iz6FcTUSRDxm8GK/YAbKb8qG05trPsaYBMJNRDemOo9CPTMzwxtFAZwJaKw0teGJaqKWsfKVo6czTyyRtUR9eUr8WuqfHYhgxmF6yLkdiL5KmVVVsm1rTZg0/NX6u1o0oBIzLBpkDyptgWxWmD+M4OJay4TNOoCtSkPFYTYLYcE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776241047; c=relaxed/simple; bh=SDHu4CF6hiHHjw7wIYF2M+BZ1AnJr501zKLvFcrIIPQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:Cc; b=fWZ2LygHYZCZP/Z4vPIoUOb9QlpbFVEZfSv2EXhghbDnVNJbKGLVIymmIM1MiQs+RWHW19WGcJSa7xkYdZ/ybHOhpL4XhAQfQb4TU2pxNY9uNBtaXNggSzW0geg2J+I4yVB5Avu4uA8ntuNWwJUz/k3vcwzXTIKClh67UXQWXoM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dev.tdt.de; spf=pass smtp.mailfrom=dev.tdt.de; dkim=temperror (0-bit key) header.d=dev.tdt.de header.i=@dev.tdt.de header.b=UuLOndoL; arc=none smtp.client-ip=194.37.255.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=dev.tdt.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=dev.tdt.de Authentication-Results: smtp.subspace.kernel.org; dkim=temperror (0-bit key) header.d=dev.tdt.de header.i=@dev.tdt.de header.b="UuLOndoL" Received: from [194.37.255.9] (helo=mxout.expurgate.net) by relay.expurgate.net with smtp (Exim 4.92) (envelope-from ) id 1wCvC5-003sbl-Pg; Wed, 15 Apr 2026 10:01:53 +0200 Received: from [195.243.126.94] (helo=securemail.tdt.de) by relay.expurgate.net with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1wCvC5-000FI6-99; Wed, 15 Apr 2026 10:01:53 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=dev.tdt.de; s=z1-selector1; t=1776240112; bh=JqZmvXp+hLfJuRdo0qRIk/QxAIHQamNDzRshObedo7Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=UuLOndoL2Wun9SH8+2lA3BbkEyAX3zmBvKD4cZkHhCI2pKWS6up1mF8kGllk7RrOV 3RNJK/dNhErzDjkdHe6I9bbEStj73AudXbyiSAZnDTjgBDLgKdoO+JL6L5htNtmUVM +ECRI/MWLxxC06endHLHcIwqfSOTVrEkJbsj4xE4T+bVf13w/uC4VKEheYzhs6HDGj yvNG1I25vEuwaoDFXo+ghTsxLNKRBKdt+sj+eY9c7ZVqIH70bsKdc6IkQIQVcSIN+b Uasv4SonRXflWoWHD+iubcxoF6DKotLOg7q5Cbx2FSWnVQdU10mPIg01iRC9UT5Il2 faIFd37B91Avg== Received: from securemail.tdt.de (localhost [127.0.0.1]) by securemail.tdt.de (Postfix) with ESMTP id CB24B240047; Wed, 15 Apr 2026 10:01:52 +0200 (CEST) Received: from mail.dev.tdt.de (unknown [10.2.4.42]) by securemail.tdt.de (Postfix) with ESMTP id AD752240045; Wed, 15 Apr 2026 10:01:52 +0200 (CEST) Received: from [10.2.3.40] (unknown [10.2.3.40]) by mail.dev.tdt.de (Postfix) with ESMTPSA id 8FEB724028; Wed, 15 Apr 2026 10:01:52 +0200 (CEST) From: Florian Eckert Date: Wed, 15 Apr 2026 10:01:47 +0200 (CEST) Subject: [PATCH v4 1/7] MAINTAINERS: Remove bouncing intel-gw maintainer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260415-pcie-intel-gw-v4-1-ad45d2418c8e@dev.tdt.de> References: <20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de> In-Reply-To: <20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de> To: Lorenzo Pieralisi , =?utf-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Johan Hovold , Sajid Dalvi , Ajay Agarwal , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Florian Eckert , Eckert.Florian@googlemail.com, ms@dev.tdt.de X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776240111; l=809; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=SDHu4CF6hiHHjw7wIYF2M+BZ1AnJr501zKLvFcrIIPQ=; b=ZnlMONcsBYKLjUgojYYduutUgV39nY/QoNZKZMNL9q9YIHcqMXbjoIdjST8qNrjiA8nnTnpTa n+jiTBPUVyxDfyP+Nmthasw0/1VnYGTeLXUWxmapzqPE8EU/18DdOZT X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= X-purgate: clean X-purgate-type: clean X-purgate-ID: 151534::1776240113-2EC1419A-5196C29B/0/0 The maintainer's email address has been bouncing for months. Mark the PCI intel-gw driver as orphaned. Signed-off-by: Florian Eckert --- MAINTAINERS | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index d1cc0e12fe1f004da89b1aa339116908f642e894..725f333f265bef416b5144c5664= 9cb6eae736e40 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20518,9 +20518,8 @@ F: Documentation/devicetree/bindings/pci/intel,keem= bay-pcie* F: drivers/pci/controller/dwc/pcie-keembay.c =20 PCIE DRIVER FOR INTEL LGM GW SOC -M: Chuanhua Lei L: linux-pci@vger.kernel.org -S: Maintained +S: Orphan F: Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml F: drivers/pci/controller/dwc/pcie-intel-gw.c =20 --=20 2.47.3 From nobody Tue Jun 16 01:36:50 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [194.37.255.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78A9022CBE6; Wed, 15 Apr 2026 08:17:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=ed25519-sha256; t=1776240111; l=814; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=xn9R5Y4c2FVuxWGJ+XDVZ0hhgrzdWZnr3TAJrrkBg1E=; b=30wXOiI8KcmHESyl9H/yuDXVFd2GzUoEDNdoss5l4AoHLR9luLObnEkIc3lsm58l7iNObn62n XTeyr7DHItIDSrCMw0GYQRdqsHEnmXKdfCwtZHBNdjiHnJeE7DF3XfP X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= X-purgate-ID: 151534::1776240113-5515C19A-8E439D5D/0/0 X-purgate-type: clean X-purgate: clean The C preprocessor define 'PCIE_APP_INTX_OFST' is not used in the sources and can therefore be deleted. Signed-off-by: Florian Eckert --- drivers/pci/controller/dwc/pcie-intel-gw.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index c21906eced61896c8a8307dbd6b72d229f9a5c5f..80d1607c46cbbb1e274b37a0bb9= 377a877678f5d 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -47,7 +47,6 @@ #define PCIE_APP_IRN_INTD BIT(16) #define PCIE_APP_IRN_MSG_LTR BIT(18) #define PCIE_APP_IRN_SYS_ERR_RC BIT(29) -#define PCIE_APP_INTX_OFST 12 =20 #define PCIE_APP_IRN_INT \ (PCIE_APP_IRN_AER_REPORT | PCIE_APP_IRN_PME | \ --=20 2.47.3 From nobody Tue Jun 16 01:36:50 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [91.198.224.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BA54E3B7751; Wed, 15 Apr 2026 08:19:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 15 Apr 2026 10:01:54 +0200 (CEST) Received: from mail.dev.tdt.de (unknown [10.2.4.42]) by securemail.tdt.de (Postfix) with ESMTP id 8330D240040; Wed, 15 Apr 2026 10:01:54 +0200 (CEST) Received: from [10.2.3.40] (unknown [10.2.3.40]) by mail.dev.tdt.de (Postfix) with ESMTPSA id C385324028; Wed, 15 Apr 2026 10:01:52 +0200 (CEST) From: Florian Eckert Date: Wed, 15 Apr 2026 10:01:49 +0200 (CEST) Subject: [PATCH v4 3/7] PCI: intel-gw: Move interrupt enable to own function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Message-ID: <20260415-pcie-intel-gw-v4-3-ad45d2418c8e@dev.tdt.de> References: <20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de> In-Reply-To: <20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de> To: Lorenzo Pieralisi , =?utf-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Johan Hovold , Sajid Dalvi , Ajay Agarwal , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Florian Eckert , Eckert.Florian@googlemail.com, ms@dev.tdt.de X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776240111; l=2926; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=ZYKI9htHzLsLWQm9mMvJbP0KpPmuZ1vngPu0F8zCXMI=; b=jcsd9M7td+8J8ulKtrrL+BPo6v8bhL6aK4wA3oMZfabsnaPpY8ewS3sf0kgvOvqJNKS5qRymy awd53nP3yC4B3UgMH3YTeBpnIMkv7DXnkejsQQbwZQLswio7syQQSmF X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= Content-Transfer-Encoding: quoted-printable X-purgate-type: clean X-purgate: clean X-purgate-ID: 151534::1776240115-3DFF02EC-420E88E8/0/0 To improve the readability of the code, move the interrupt enable instructions to a separate function. That is already done for the disable interrupt instruction. In addition, all pending interrupts are cleared and disabled, just as this is done in the disable function 'intel_pcie_core_irq_disable()'. After that, all relevant interrupts are enabled again. The 'PCIE_APP_IRNEN' definition contains all the relevant interrupts that are of interest. This change is also done in the MaxLinear SDK [1]. As I unfortunately don=E2=80=99t have any documentation for this IP core, I suspect that the intention is to set the IP core for interrupt handling to a specific state. Perhaps the problem is that the IP core did not reinitialize the interrupt register properly after a power cycle. In my view, it can=E2=80=99t do any harm to switch the interrupt off and th= en on again to set them to a specific state. The reason why the MaxLinear SDK is used as a reference here is, that this pcie dwc IP is used in the URX851 and URX850 SoC. This SoC was originally developed by Intel when they acquired Lantiq=E2=80=99s home networking divi= sion in 2015 [2]. In 2020 the home network division was sold to MaxLinear [3]. Since then, this SoC belongs to MaxLinear. They use their own SDK, which runs on kernel version '5.15.x'. [1] https://github.com/maxlinear/linux/blob/updk_9.1.90/drivers/pci/control= ler/dwc/pcie-intel-gw.c#L431 [2] https://www.intc.com/news-events/press-releases/detail/364/intel-to-acq= uire-lantiq-advancing-the-connected-home [3] https://investors.maxlinear.com/press-releases/detail/395/maxlinear-to-= acquire-intels-home-gateway-platform Signed-off-by: Florian Eckert --- drivers/pci/controller/dwc/pcie-intel-gw.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index 80d1607c46cbbb1e274b37a0bb9377a877678f5d..e88b8243cc41c607c39e4d58c4d= cd8c8c082e8b0 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -195,6 +195,13 @@ static void intel_pcie_device_rst_deassert(struct inte= l_pcie *pcie) gpiod_set_value_cansleep(pcie->reset_gpio, 0); } =20 +static void intel_pcie_core_irq_enable(struct intel_pcie *pcie) +{ + pcie_app_wr(pcie, PCIE_APP_IRNEN, 0); + pcie_app_wr(pcie, PCIE_APP_IRNCR, PCIE_APP_IRN_INT); + pcie_app_wr(pcie, PCIE_APP_IRNEN, PCIE_APP_IRN_INT); +} + static void intel_pcie_core_irq_disable(struct intel_pcie *pcie) { pcie_app_wr(pcie, PCIE_APP_IRNEN, 0); @@ -316,9 +323,7 @@ static int intel_pcie_host_setup(struct intel_pcie *pci= e) if (ret) goto app_init_err; =20 - /* Enable integrated interrupts */ - pcie_app_wr_mask(pcie, PCIE_APP_IRNEN, PCIE_APP_IRN_INT, - PCIE_APP_IRN_INT); + intel_pcie_core_irq_enable(pcie); =20 return 0; =20 --=20 2.47.3 From nobody Tue Jun 16 01:36:50 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [91.198.224.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C097C3CEBA7; Wed, 15 Apr 2026 08:19:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.198.224.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776241194; 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Wed, 15 Apr 2026 10:01:54 +0200 (CEST) Received: from mail.dev.tdt.de (unknown [10.2.4.42]) by securemail.tdt.de (Postfix) with ESMTP id B0AEB240040; Wed, 15 Apr 2026 10:01:54 +0200 (CEST) Received: from [10.2.3.40] (unknown [10.2.3.40]) by mail.dev.tdt.de (Postfix) with ESMTPSA id 8167423F30; Wed, 15 Apr 2026 10:01:54 +0200 (CEST) From: Florian Eckert Date: Wed, 15 Apr 2026 10:01:50 +0200 (CEST) Subject: [PATCH v4 4/7] PCI: intel-gw: Enable clock before phy init Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Message-ID: <20260415-pcie-intel-gw-v4-4-ad45d2418c8e@dev.tdt.de> References: <20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de> In-Reply-To: <20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de> To: Lorenzo Pieralisi , =?utf-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Johan Hovold , Sajid Dalvi , Ajay Agarwal , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Florian Eckert , Eckert.Florian@googlemail.com, ms@dev.tdt.de X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776240111; l=2721; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=e2R433hJ5rO3HTn7PeimYHVCAsltELW5gkTR8+BYSdw=; b=jhTTvuH4kGGPcppcdUxMOsv396KZls8NkMVKLAn92E7cMkW5+WepgfPLavzZf+FYVVu+xhxjo ptJNh+mxsYkAy4g218lthbBadJw+Hs/jJvMLMG8Pf0zSJgpc2qPswyy X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= Content-Transfer-Encoding: quoted-printable X-purgate-ID: 151534::1776240115-54C8D2EC-2FD84FEA/0/0 X-purgate: clean X-purgate-type: clean To ensure that the boot sequence is correct, the dwc pcie core clock must be switched on before phy init call [1]. This changes are based on patched kernel sources of the MaxLinear SDK. The reason why the MaxLinear SDK is used as a reference here is, that this pcie dwc IP is used in the URX851 and URX850 SoC. This SoC was originally developed by Intel when they acquired Lantiq=E2=80=99s home networking divi= sion in 2015 [2]. In 2020 the home network division was sold to MaxLinear [3]. Since then, this SoC belongs to MaxLinear. They use their own SDK, which runs on kernel version '5.15.x'. [1] https://github.com/maxlinear/linux/blob/updk_9.1.90/drivers/pci/control= ler/dwc/pcie-intel-gw.c#L544 [2] https://www.intc.com/news-events/press-releases/detail/364/intel-to-acq= uire-lantiq-advancing-the-connected-home [3] https://investors.maxlinear.com/press-releases/detail/395/maxlinear-to-= acquire-intels-home-gateway-platform Signed-off-by: Florian Eckert --- drivers/pci/controller/dwc/pcie-intel-gw.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index e88b8243cc41c607c39e4d58c4dcd8c8c082e8b0..6d9499d954674a26a74bff56b7f= b5759767424c0 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -291,13 +291,9 @@ static int intel_pcie_host_setup(struct intel_pcie *pc= ie) =20 intel_pcie_core_rst_assert(pcie); intel_pcie_device_rst_assert(pcie); - - ret =3D phy_init(pcie->phy); - if (ret) - return ret; - intel_pcie_core_rst_deassert(pcie); =20 + /* Controller clock must be provided earlier than PHY */ ret =3D clk_prepare_enable(pcie->core_clk); if (ret) { dev_err(pcie->pci.dev, "Core clock enable failed: %d\n", ret); @@ -306,13 +302,17 @@ static int intel_pcie_host_setup(struct intel_pcie *p= cie) =20 pci->atu_base =3D pci->dbi_base + 0xC0000; =20 + ret =3D phy_init(pcie->phy); + if (ret) + goto phy_err; + intel_pcie_ltssm_disable(pcie); intel_pcie_link_setup(pcie); intel_pcie_init_n_fts(pci); =20 ret =3D dw_pcie_setup_rc(&pci->pp); if (ret) - goto app_init_err; + goto err; =20 dw_pcie_upconfig_setup(pci); =20 @@ -321,17 +321,18 @@ static int intel_pcie_host_setup(struct intel_pcie *p= cie) =20 ret =3D dw_pcie_wait_for_link(pci); if (ret) - goto app_init_err; + goto err; =20 intel_pcie_core_irq_enable(pcie); =20 return 0; =20 -app_init_err: +err: + phy_exit(pcie->phy); +phy_err: clk_disable_unprepare(pcie->core_clk); clk_err: intel_pcie_core_rst_assert(pcie); - phy_exit(pcie->phy); =20 return ret; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20260415-pcie-intel-gw-v4-5-ad45d2418c8e@dev.tdt.de> References: <20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de> In-Reply-To: <20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de> To: Lorenzo Pieralisi , =?utf-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Johan Hovold , Sajid Dalvi , Ajay Agarwal , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Florian Eckert , Eckert.Florian@googlemail.com, ms@dev.tdt.de X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776240111; l=3153; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=1QhwwO0tMMhb5/PF/9cK8bvzkNyUt/Wf2sydrtsZXUc=; b=xZWea6SKVdk8phIcykeaa/lhRj/xE1Y9ygqH+pY5UY96jz7IKdcP9cj7gN61L3J8+881a41Sc /PFBb6JmNuoDX1FbkB+JcTEbKiSEPrGm/QuV7y8lPzoIZJSkQ8EVhRO X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= X-purgate-type: clean X-purgate: clean X-purgate-ID: 151534::1776240115-FBFF42EC-C76EFE1C/0/0 The pcie-intel-gw driver has no start_link callback function. This commit adds the missing callback function so that the driver works again and does not abort with the following error messages during probing. [ 2.512015] intel-gw-pcie d1000000.pcie: host bridge /soc/pcie@d1000000 = ranges: [ 2.517868] intel-gw-pcie d1000000.pcie: MEM 0x00dc000000..0x00ddff= ffff -> 0x00dc000000 [ 2.528450] intel-combo-phy d0c00000.combo-phy: Set combo mode: combophy= [1]: mode: PCIe single lane mode [ 2.551619] intel-gw-pcie d1000000.pcie: No outbound iATU found [ 2.556060] intel-gw-pcie d1000000.pcie: Cannot initialize host [ 2.561901] intel-gw-pcie d1000000.pcie: probe with driver intel-gw-pcie= failed with error -22 [ 2.571041] intel-gw-pcie c1100000.pcie: host bridge /soc/pcie@c1100000 = ranges: [ 2.577736] intel-gw-pcie c1100000.pcie: MEM 0x00ce000000..0x00cfff= ffff -> 0x00ce000000 [ 2.588299] intel-combo-phy c0c00000.combo-phy: Set combo mode: combophy= [3]: mode: PCIe single lane mode [ 2.611471] intel-gw-pcie c1100000.pcie: No outbound iATU found [ 2.615934] intel-gw-pcie c1100000.pcie: Cannot initialize host [ 2.621759] intel-gw-pcie c1100000.pcie: probe with driver intel-gw-pcie= failed with error -22 Fixes: c5097b9869a1 ("Revert "PCI: dwc: Wait for link up only if link is st= arted"") Fixes: da56a1bfbab5 ("PCI: dwc: Wait for link up only if link is started") Signed-off-by: Florian Eckert --- drivers/pci/controller/dwc/pcie-intel-gw.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index 6d9499d954674a26a74bff56b7fb5759767424c0..afd933050c92ee31c477e0b1738= ab1136bdcfbf6 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -284,6 +284,16 @@ static void intel_pcie_turn_off(struct intel_pcie *pci= e) pcie_rc_cfg_wr_mask(pcie, PCI_COMMAND, PCI_COMMAND_MEMORY, 0); } =20 +static int intel_pcie_start_link(struct dw_pcie *pci) +{ + struct intel_pcie *pcie =3D dev_get_drvdata(pci->dev); + + intel_pcie_device_rst_deassert(pcie); + intel_pcie_ltssm_enable(pcie); + + return 0; +} + static int intel_pcie_host_setup(struct intel_pcie *pcie) { int ret; @@ -310,25 +320,12 @@ static int intel_pcie_host_setup(struct intel_pcie *p= cie) intel_pcie_link_setup(pcie); intel_pcie_init_n_fts(pci); =20 - ret =3D dw_pcie_setup_rc(&pci->pp); - if (ret) - goto err; - dw_pcie_upconfig_setup(pci); =20 - intel_pcie_device_rst_deassert(pcie); - intel_pcie_ltssm_enable(pcie); - - ret =3D dw_pcie_wait_for_link(pci); - if (ret) - goto err; - intel_pcie_core_irq_enable(pcie); =20 return 0; =20 -err: - phy_exit(pcie->phy); phy_err: clk_disable_unprepare(pcie->core_clk); clk_err: @@ -386,6 +383,7 @@ static int intel_pcie_rc_init(struct dw_pcie_rp *pp) } =20 static const struct dw_pcie_ops intel_pcie_ops =3D { + .start_link =3D intel_pcie_start_link, }; =20 static const struct dw_pcie_host_ops intel_pcie_dw_ops =3D { --=20 2.47.3 From nobody Tue Jun 16 01:36:50 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [91.198.224.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F41C13CE490; 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Wed, 15 Apr 2026 10:01:55 +0200 (CEST) Received: from mail.dev.tdt.de (unknown [10.2.4.42]) by securemail.tdt.de (Postfix) with ESMTP id 05089240041; Wed, 15 Apr 2026 10:01:55 +0200 (CEST) Received: from [10.2.3.40] (unknown [10.2.3.40]) by mail.dev.tdt.de (Postfix) with ESMTPSA id CFD2323F30; Wed, 15 Apr 2026 10:01:54 +0200 (CEST) From: Florian Eckert Date: Wed, 15 Apr 2026 10:01:52 +0200 (CEST) Subject: [PATCH v4 6/7] PCI: intel-gw: Move driver atu base assignment to probe function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Message-ID: <20260415-pcie-intel-gw-v4-6-ad45d2418c8e@dev.tdt.de> References: <20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de> In-Reply-To: <20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de> To: Lorenzo Pieralisi , =?utf-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Johan Hovold , Sajid Dalvi , Ajay Agarwal , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Florian Eckert , Eckert.Florian@googlemail.com, ms@dev.tdt.de X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776240111; l=4090; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=kL2musMQ5PHaQWBVzchER4SxtQ6ESnYIALm57Dd11Ys=; b=yGKeqrvY4u8dzv1D8UT8QnnloC0dXDRyM6dnpMCLGN/vJGhFlhzhNZTa+NLSFvpg8AV974zSQ IlxSBsS7KlGAobAjh9XoXc6Vg7qe197rxqjg+Km+B831cHauXJDoqzZ X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= Content-Transfer-Encoding: quoted-printable X-purgate: clean X-purgate-ID: 151534::1776240115-3CFFE2EC-B150F9D6/0/0 X-purgate-type: clean If no ATU resource is defined in the devicetree, then driver=C2=B4s default value '0x300000' [1] is set. This is done during probing in the function 'dw_pcie_get_resources()' [2] by dwc core. The driver overwrites this again when its own init callback 'pp->ops->init()' [3] function 'intel_pcie_host_setup()' [4] is called. This is done, because the 'atu_base' offset for this IP is '0xC0000'rather than '0x300000'. callstack: intel_pcie_probe() dw_pcie_host_init() dw_pcie_host_get_resources() dw_pcie_get_resources() [2] pp->ops->init =3D intel_pcie_rc_init() [3] intel_pcie_host_setup() [4] However, this is a problem because, the callback 'pp->ops->init' is called after 'dw_pcie_get_resources()' in dwc core (see callstack). The 'atu_base' must be set before, so that this value is not set by dwc core. Therefore the assignment of 'atu_base' is moved to driver=C2=B4s probe function. While we=E2=80=99re at it, the change also adds the option to load ATU info= rmation from the device tree. For reasons of backwards compatibility, this is not mandatory. If =E2=80=98atu=E2=80=99 is not specified in the devicetree, the= n driver=E2=80=99s default value is still used and set in driver=C2=B4s probe function. If the= 'atu' resource is present in the devicetree, then dwc core loads it via the function 'dw_pcie_get_resources()' and not in the driver=C2=B4s probe funct= ion. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /drivers/pci/controller/dwc/pcie-designware.h?h=3Dv7.0#n292 [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /drivers/pci/controller/dwc/pcie-designware.c?h=3Dv7.0#n150 [3] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /drivers/pci/controller/dwc/pcie-designware-host.c?h=3Dv7.0#n588 [4] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /drivers/pci/controller/dwc/pcie-intel-gw.c?h=3Dv7.0#n301 Signed-off-by: Florian Eckert --- drivers/pci/controller/dwc/pcie-intel-gw.c | 28 ++++++++++++++++++++++++++= -- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/contr= oller/dwc/pcie-intel-gw.c index afd933050c92ee31c477e0b1738ab1136bdcfbf6..59b11e45944e199aac0f599f96d= 6cc90e2104708 100644 --- a/drivers/pci/controller/dwc/pcie-intel-gw.c +++ b/drivers/pci/controller/dwc/pcie-intel-gw.c @@ -310,8 +310,6 @@ static int intel_pcie_host_setup(struct intel_pcie *pci= e) goto clk_err; } =20 - pci->atu_base =3D pci->dbi_base + 0xC0000; - ret =3D phy_init(pcie->phy); if (ret) goto phy_err; @@ -395,6 +393,7 @@ static int intel_pcie_probe(struct platform_device *pde= v) struct device *dev =3D &pdev->dev; struct intel_pcie *pcie; struct dw_pcie_rp *pp; + struct resource *res; struct dw_pcie *pci; int ret; =20 @@ -419,6 +418,31 @@ static int intel_pcie_probe(struct platform_device *pd= ev) pci->ops =3D &intel_pcie_ops; pp->ops =3D &intel_pcie_dw_ops; =20 + /* + * If the 'atu' resource is not available in the devicetree, + * then use the driver default value for backward compatibility. + * The 'atu' should always be set in the devicetree, as this is + * hardware specific setting that should not be defined in the + * source. + */ + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); + if (!res) { + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); + pci->dbi_base =3D devm_pci_remap_cfg_resource(pci->dev, res); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); + pci->dbi_phys_addr =3D res->start; + pci->atu_base =3D devm_ioremap(dev, res->start + 0xC0000, SZ_4K); + if (!pci->atu_base) { + dev_err(dev, "failed to remap ATU space\n"); + return -ENOMEM; + + } + pci->atu_size =3D SZ_4K; + pci->atu_phys_addr =3D res->start + 0xC0000; + dev_warn(dev, "devicetree ATU resource is missing; driver`s default valu= e is being used\n"); + } + ret =3D dw_pcie_host_init(pp); if (ret) { dev_err(dev, "Cannot initialize host\n"); --=20 2.47.3 From nobody Tue Jun 16 01:36:50 2026 Received: from mxout70.expurgate.net (mxout70.expurgate.net [91.198.224.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D45C1307AE3; Wed, 15 Apr 2026 08:19:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.198.224.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776241179; cv=none; b=M84/8y2/Gib7rTVV9QUn200oiqdKzdt8zUMMFrUbOz/mzFckq8gDctDmL6pIAQGuN1sU15SkF+lCBa71U6BSsVOis6p9Bu2sqRtvxdQnuBUT02rwE7S9QOWLIOsOE8ePoxEs9ahI/bWlqmApbGNVWy1p4WZcXhCHFYBZdPCWvBg= ARC-Message-Signature: i=1; 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Wed, 15 Apr 2026 10:01:55 +0200 (CEST) Received: from [10.2.3.40] (unknown [10.2.3.40]) by mail.dev.tdt.de (Postfix) with ESMTPSA id 0513A24043; Wed, 15 Apr 2026 10:01:55 +0200 (CEST) From: Florian Eckert Date: Wed, 15 Apr 2026 10:01:53 +0200 (CEST) Subject: [PATCH v4 7/7] dt-bindings: PCI: intel,lgm-pcie: Add atu resource Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Message-ID: <20260415-pcie-intel-gw-v4-7-ad45d2418c8e@dev.tdt.de> References: <20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de> In-Reply-To: <20260415-pcie-intel-gw-v4-0-ad45d2418c8e@dev.tdt.de> To: Lorenzo Pieralisi , =?utf-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Johan Hovold , Sajid Dalvi , Ajay Agarwal , Krzysztof Kozlowski , Conor Dooley Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Florian Eckert , Eckert.Florian@googlemail.com, ms@dev.tdt.de X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776240111; l=1906; i=fe@dev.tdt.de; s=20260205; h=from:subject:message-id; bh=AXbWkqnfnXkg5GGOJ+SWn5GjqEnEK81zcfXBynbMX+Y=; b=qFOx4AXlU6qSrD3pRQNg40Jd30cjP0KfB+h/7s4PlP5d82gz0VP/G6ioWegoM4YyaqwVC00Xn /qqaFH1/FWFDGZIvbV+4GNNWjwhOkBlo2ezoDPCSkMYzMaWAdVhxBzo X-Developer-Key: i=fe@dev.tdt.de; a=ed25519; pk=q7Pvv3Au2sAVRhBz5UF7ZqUPNxUwXQ78Jdqu8E6Negk= Content-Transfer-Encoding: quoted-printable X-purgate: clean X-purgate-ID: 151534::1776240116-3D7F12EC-F235BB83/0/0 X-purgate-type: clean The 'atu' information is already set in the dwc core, if it is specified in the devicetree. The driver uses its own default, if not set in the devicetree. This information is hardware specific and should therefore be maintained in the devicetree rather than in the source. To be backward compatible, this field is not mandatory. If 'atu' resource is not specified in the devicetree, the driver=E2=80=99s default v= alue is used. Signed-off-by: Florian Eckert --- Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml b/Doc= umentation/devicetree/bindings/pci/intel-gw-pcie.yaml index 54e2890ae6314ac6847fc23f49440d05d66d87d4..9b7a8ef77585677841c7064c500= 1110bc2b65db1 100644 --- a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml @@ -27,16 +27,19 @@ properties: - const: snps,dw-pcie =20 reg: + minItems: 3 items: - description: Controller control and status registers. - description: PCIe configuration registers. - description: Controller application registers. + - description: Internal Address Translation Unit (iATU) registers. =20 reg-names: items: - const: dbi - const: config - const: app + - const: atu =20 ranges: maxItems: 1 @@ -95,8 +98,9 @@ examples: #size-cells =3D <2>; reg =3D <0xd0e00000 0x1000>, <0xd2000000 0x800000>, - <0xd0a41000 0x1000>; - reg-names =3D "dbi", "config", "app"; + <0xd0a41000 0x1000>, + <0xd0ec0000 0x1000>; + reg-names =3D "dbi", config", "app", "atu"; linux,pci-domain =3D <0>; max-link-speed =3D <4>; bus-range =3D <0x00 0x08>; --=20 2.47.3